ESD Design Rule Verification

ESD Design Rule Verification Roland Reitbauer 1, Wolfgang Reinprecht 1, Thomas Mörth 1 (1) austriamicrosystems AG, A-8141 Unterpremstätten, Austria Zusammenfassung In den vergangenen Jahren haben sich Verifikationstools entwickelt, die es ermöglichen mit vorgefertigten Funktionen individuelle Prüfalgorithmen für ESD Designregeln aufzusetzen. Diese Funktionen greifen auf die Netzliste einer Schaltung zu, um daraus die gesuchten Informationen zu sammeln und zur Bearbeitung bereitzustellen. Funktionen, die eine statische Spannungsanalyse ermöglichen sind dabei von besonderer Bedeutung, weil damit ohne Simulationsaufwand Überspannungen an Devices gefunden werden können. Abstract In the past years verification tools have been developed for setting up individual ESD design rule checks by using provided functions. These functions access the netlist of a design to collect the desired data which is returned for processing. Functions which offer a static voltage analysis play a major role for finding overvoltage conditions on devices without any simulation effort. 1 Introduction In order to avoid ESD failures due to known design rule violations, it is absolutely necessary to verify a circuit design for ESD rule compliance in advance. The best way to do this is an automated checking tool within the design environment [1]. The root cause for ESD damages are often poorly connected or wrongly dimensioned devices, which need to be detected and corrected prior to tapeout. A manual inspection of a design database which extends over many hierarchy levels is very time consuming and inefficient [2]. For this reason it makes sense to rely on software tools which allow an automated verification flow. The platform of the presented checking approach is denoted with PERC Programmable Electrical Rule Check. PERC enables a fast implementation of specific ESD design rule checks which can be started by an interface in the design environment. After the error report is available, device crossprobing is used to highlight the error locations in the database. PERC provides a set of iterative functions which offer access to all devices and nets of a design netlist. The preparation and the scanning of the netlist data is done automatically by these predefined functions, but the way how they are applied is determined by the different rule checks. To find the device of interest, the model type and connectivity criteria need to be specified. With these inputs PERC returns every matching netlist object for the purpose of being investigated by customizable ESD rule checks. If the rule conditions are violated, the processed netlist object becomes part of the error report. Each rule check is initialized by certain initialization commands. They allow voltage level assignments to top level pins or to other ESD relevant nodes. Furthermore they offer the possibility to define net paths on which the assigned net names and values are propagated to other nodes. The propagation of supply names to internal nodes allows an association of each signal to its corresponding power domain. The voltage value propagation is used to check if devices would be overstressed within the applied voltage ranges. In the first part of this work some ESD concept checks for verifying the needed protections on I/O and supplies are presented. Then is described how the right voltage levels are automatically found and assigned to supply nets, focussing on isolated domains in high voltage concepts. The final part covers voltage checks on devices being connected to pads or to internal domain interfaces. 2 Setup Before the ESD rule checks can be applied on a design, a CDL netlist must be taken from the schematic, or a SPICE netlist must be extracted from the layout. Other required inputs for the check are the top cell name, the supply pin names and the ground pin names. In addition, there is the possibility to define several netlist reduction options. In order to simplify the rule checks it is very helpful to reduce parallel and serial devices

in advance or to filter short resistors. By starting the check in the design environment, all settings can be done in a graphical user interface. 3 ESD Protection Concept At the beginning of every ESD design review following questions have to be considered: What are the power domains? What voltage level do they have and how are they protected? Which I/O belongs to which power domain? Supply protections and I/O devices are of main interest in the first stage of an ESD review, as they must be capable to discharge an ESD event in the periphery of the chip. So the first task of the ESD design rule check is to find these protection devices and to deliver an output, in which an overview of the whole ESD protection concept is presented. This is done by grouping all I/O according to their corresponding supplies in a text file. In order to detect ESD clamps, the rule checks have to take into account all possible device topologies which can be used as protection circuits in the respective technology. 3.1 Clamp Types This work describes how following clamp protections are found: Gate coupled NMOS (GCNMOS) High voltage protection with trigger diode In case of SCR or active triggered protections, the rule check can easily be extended to identify these topologies too. Figure 1 shows the flow for finding GCNMOS clamp protections between and. The highlighted part indicates the netlist object, which is automatically returned by PERC from a provided check function (perc::check_net). In the example of Figure 1 the netlist object is a supply net, which gets checked in a condition procedure for the connection of the right protection device. The first step in the condition is to put all devices in a list which meet certain criteria. A PERC command gets applied for collecting these devices. When selecting an appropriate device, neighbour devices are checked to form the desired topology. If all specified conditions are fulfilled, the device on the investigated net is considered as protection device. This iteration is repeated by PERC until the condition procedure for all supply nets has been processed. Figure 1: Searching Flow for Finding Clamp Protections (GCNMOS) in Low Voltage Domains The starting point for a rule check does not always have to be a net, as described in the previous flow, but can also be a device, as illustrated in Figure 2. The flow chart there shows a PMOS device as starting netlist object to find the topology of high voltage protections. In each iteration loop a standard PERC function gives access to the desired device (perc::check_device), which gets selected according to the specified options. The required topology is verified in a condition procedure. If a valid clamp topology is detected, its voltage class gets evaluated and associated to the clamp domain nets. No For each HV PMOS which fulfills following conditions: D connected to G connected to internal node S and B connected to Is resistor connected between G and S? Yes Is trigger diode with special subtype connected with cathode to G and with anode to D? Yes Check Power Clamp Rules; Store domain information (//Voltage Class) in a list No Figure 2: Searching Flow for Finding Clamp Protections in High Voltage Domains

3.2 I/O Protections After verifying the supply nets for having clamp protections, all I/O nets get investigated. They need to have either forward diodes or driver devices to and in order to provide an ESD path to the clamp protection on the supply. If a clamp topology is found on an I/O, a device to is not required, as the I/O is then locally protected. If only a device to is connected, but nothing between I/O and, the I/O is considered as reverse polarity because it does not get clamped to substrate. The negative level that can arise during ESD is then given by the breakdown voltage of the device between I/O and. Figure 3: Voltage Definition Flow for Supply Nets of Substrate Based Power Domains Following three checks are performed while searching for I/O devices. Verify if each I/O has devices connected to supply nets, so that ESD paths are provided in positive and negative direction Verify if the I/O devices are connected to a central clamp protection on the supply or if they form a local clamp Verify if the I/O devices have the required size and device type to be ESD robust After finding the protection elements on supplies and I/O, they are listed in an ESD concept report. This report is a text output which gives an overview of the found power domains by listing their protection devices. 3.3 Supply Voltage Assignment In order to be able to check absolute maximum voltage (absmax rating) violations of devices, voltage values are assigned to all supply nets. The voltage of each power domain is given by the device subtype of the connected clamp protection. If a power domain is substrate based, its ground net can be set to 0 and its power net can be set to the voltage class of the connected clamp (domain level). In contrast to this, the voltage assignments for isolated power domains must be calculated as described in flow chart of Figure 4. The voltage between isolated ground and substrate can only be determined if the corresponding power supply level has been identified first. For this reason the voltage definition flow in Figure 3 has to be started at the beginning. This ensures that the power supply levels are already known when the voltage levels of isolated ground nets are calculated. Figure 4: Voltage Definition Flow for Supply Nets of Isolated Power Domains The numbered boxes of Figure 3 and Figure 4 correspond to the numbered voltage settings in Figure 5. The first voltage definition step is indexed by (1). The values referred by (2) are calculated for isolated ground nets and the value marked with (3) is set on power nets of isolated domains with missing reference to substrate. Figure 5: Example of Voltage Assignments to Supplies

4 Voltage Violation Checks As soon as all nets with a clamp protection are assigned with the corresponding voltage levels, absmax rating violations of devices can be verified. In order to be able to do this for all devices, the voltages are propagated by PERC from the supply nets to other nodes. Thereby several options can be set to define the allowed propagation paths. These options are, for instance, device types, which allow a propagation of the voltage value between the specified device pins. Other device types or pins which are not listed in the options are not considered for a voltage path. Furthermore break conditions need to be specified to stop the propagation on supply nets and internal protected nodes. Without stopping the propagation there, each node would receive all available voltages, which would make no sense. After running the propagation, voltage levels can be obtained on every net. Each node gets voltages propagated from the supplies, where it belongs to. With the highest and lowest value, the maximum possible voltage difference across a device can be calculated. In order to be able to verify if a device is within the allowed voltage range, the device voltage class has to be known. For this, all device types of the used technology are listed in the rule file and grouped according to their voltage classes. This way each device of interest can be associated with its safe voltage range. If this range is exceeded by the propagated voltages, the device is outside of absmax rating condition and must be flagged as an error. 4.1 Voltage Check on Pad Devices In general the propagation path is defined to contain diodes, resistors and MOS junctions. By building voltage paths through these devices, all nodes with a DC path to the supplies receive propagated values. I/O nets with a valid ESD path to the supplies belong to such nodes. The power supply level and the ground supply level are propagated to each I/O. The difference of the propagated values indicates their voltage range. In case of the PMOS in Figure 6, the highest value on bulk (B) is 50 and the lowest value propagated to drain (D) is 45. By taking these values, a maximum voltage difference of 5 between the regarding device pins would be the result. But in isolated domains the propagated values only reflect the voltage range correctly within the same domain. As bulk (B) and drain (D) in Figure 6 belong to different domains, substrate gets involved in the ESD path, which causes a voltage difference of 50 instead of 5. (50 45) D 50 50 (50 0) 50V (50 0) 45 45 50V 5V S _ 0 + B 5V (50 45) Figure 6: PMOS Junction Breakdown between Bulk and Drain - Bold Values: Defined Voltages; Bracketed Values: Propagated Voltages Therefore it is important to analyse first the domains where the ESD exposed device pins belong to, before calculating the maximum voltage difference in between. This is done by comparing the domain nets in a list of net pairs. Power and ground net of each isolated power clamp build a net pair. If anti-parallel diodes are in place, a net pair is built between one power net and both ground nets, like illustrated in Figure 7. Two power nets belong to the same isolated domain if they are listed with the same ground nets. Two ground nets belong to the same domain, if they are linked to a common power net. If a correlation is found, the ESD path remains within the isolated domains during an ESD stress in between. The propagated values can then be used to calculate the maximum voltage difference. If the domain net pairs of two isolated domains do not match, an ESD stress in between would be discharged to substrate. In this case a minimum voltage of 0 must be considered for the negative stressed pad, even though the assigned or propagated value on it is higher. Figure 7: Domain Net Pairs of Isolated Domains with Anti-Parallel Diodes

4.2 Voltage Check on Internal Devices The propagation of voltage values to internal nodes also allows the detection of absmax rating violations within the core circuit. On each domain interface following information is of interest: Supply nets of driver and receiver domain Maximum voltage range across gate-bulk of the receiver devices As the supply net information gets also propagated to internal nodes, the corresponding power domains of each interface signal can be determined. The power domain information is used to find the common reference between two interface domains. This can be either substrate or two isolated grounds. In order to know this, domain net pair comparison needs to be done as described in the previous chapter. In Figure 8 is illustrated that with missing anti-parallel diodes the minimum voltage is 0. Otherwise the lowest value provided by propagation can be used as minimum voltage. If the minimum voltage is determined, the highest possible voltage difference across gate and bulk of the receiver devices can be calculated. Figure 8: Domain Interface with Propagated Maximum and Minimum Voltages In Figure 9 an interface protection between a substrate based domain and an isolated domain is illustrated. In this case the calculated voltage difference (Vdelta = Vmax - Vmin) is supposed to drop across the resistor. By retaining the resistor value the expected current through the gate clamp can be calculated. If the gate clamp has the required size for this current, the domain interface is correctly protected. Figure 9: Interface Gate Protection with Propagated Maximum and Minimum Voltages 5 Conclusion A verification flow for checking ESD protections and device voltage ranges in circuit designs has been presented. The input database for the check is a netlist file of the respective design. A platform, called PERC, provides functions to retain devices and nodes from this netlist. In addition, propagation capabilities for net names and net voltages are provided, which allow a detailed inspection of internal devices. As the power domain and voltage range of each node is known with the propagated properties, voltage violations and misconnections can be detected. For simple circuit structures the static voltage calculation is powerful enough to find possible absmax rating violations without the need for dynamic simulations. This way check results are available within a very short time, which is appreciated by the designers. References [1] Michael G. Khazhinsky, Vesselin Vassilev, Harald Gossner, Rosario Consiglio, Enrico Franell, Kelvin Hsueh, and Nitesh Trivedi, Overview of ESD Electronic Design Automation Check Requirements, International ESD Workshop 2008, pp. 339-349. [2] Hans Kunz, Gianluca Boselli, Jonathan Brodsky, Minas Hambardzumyan, and Ryan Eatmon, An Automated ESD Verification Tool for Analog Design, EOS/ESD Symposium 2010, pp. 109.