Chapter 11: Input/Output Organisation. Lesson 06: Programmed IO



Similar documents
Chapter 02: Computer Organization. Lesson 04: Functional units and components in a computer organization Part 3 Bus Structures

Computer-System Architecture

I/O. Input/Output. Types of devices. Interface. Computer hardware

Storage. The text highlighted in green in these slides contain external hyperlinks. 1 / 14

ADVANCED PROCESSOR ARCHITECTURES AND MEMORY ORGANISATION Lesson-17: Memory organisation, and types of memory

Have both hardware and software. Want to hide the details from the programmer (user).

Computer Organization & Architecture Lecture #19

CPS104 Computer Organization and Programming Lecture 18: Input-Output. Robert Wagner

Embedded Software development Process and Tools: Lesson-3 Host and Target Machines

How to design and implement firmware for embedded systems

1B11 Operating Systems. Input/Output and Devices

COMPUTER HARDWARE. Input- Output and Communication Memory Systems

Exceptions in MIPS. know the exception mechanism in MIPS be able to write a simple exception handler for a MIPS machine

Chapter 10: Virtual Memory. Lesson 08: Demand Paging and Page Swapping

Chapter 11 I/O Management and Disk Scheduling

DEPARTMENT OF COMPUTER SCIENCE & ENGINEERING Question Bank Subject Name: EC Microprocessor & Microcontroller Year/Sem : II/IV

INPUT/OUTPUT ORGANIZATION

COMPUTERS ORGANIZATION 2ND YEAR COMPUTE SCIENCE MANAGEMENT ENGINEERING UNIT 5 INPUT/OUTPUT UNIT JOSÉ GARCÍA RODRÍGUEZ JOSÉ ANTONIO SERRA PÉREZ

Lesson-16: Real time clock DEVICES AND COMMUNICATION BUSES FOR DEVICES NETWORK

DEVICE DRIVERS AND TERRUPTS SERVICE MECHANISM Lesson-14: Device types, Physical and Virtual device functions

MICROPROCESSOR. Exclusive for IACE Students iacehyd.blogspot.in Ph: /422 Page 1

Computer Systems Structure Input/Output

CSC 2405: Computer Systems II

1. Computer System Structure and Components

Machine Architecture and Number Systems. Major Computer Components. Schematic Diagram of a Computer. The CPU. The Bus. Main Memory.

CS 3530 Operating Systems. L02 OS Intro Part 1 Dr. Ken Hoganson

Devices and Device Controllers

Computer Performance. Topic 3. Contents. Prerequisite knowledge Before studying this topic you should be able to:

Chapter 3. Operating Systems

COMPUTER ARCHITECTURE. Input/Output

Chapter 2 Basic Structure of Computers. Jin-Fu Li Department of Electrical Engineering National Central University Jungli, Taiwan

Technical Note. Micron NAND Flash Controller via Xilinx Spartan -3 FPGA. Overview. TN-29-06: NAND Flash Controller on Spartan-3 Overview

Introduction to Operating Systems. Perspective of the Computer. System Software. Indiana University Chen Yu

Chapter 13. PIC Family Microcontroller

Chapter 12: Multiprocessor Architectures. Lesson 04: Interconnect Networks

University of Toronto Faculty of Applied Science and Engineering

COS 318: Operating Systems. I/O Device and Drivers. Input and Output. Definitions and General Method. Revisit Hardware

VMWare Workstation 11 Installation MICROSOFT WINDOWS SERVER 2008 R2 STANDARD ENTERPRISE ED.

An Overview of Stack Architecture and the PSC 1000 Microprocessor

Serial Communications

I/O Device and Drivers

Device Management Functions

Input / Output and I/O Strategies

Buffer Management 5. Buffer Management

Microprocessor & Assembly Language

ARM Thumb Microcontrollers. Application Note. Software ISO 7816 I/O Line Implementation. Features. Introduction

Chapter 1 Lesson 3 Hardware Elements in the Embedded Systems Chapter-1L03: "Embedded Systems - ", Raj Kamal, Publs.: McGraw-Hill Education

Storage and File Systems. Chester Rebeiro IIT Madras

Computer Architecture Prof. Mainak Chaudhuri Department of Computer Science and Engineering Indian Institute of Technology, Kanpur

Fastboot Techniques for x86 Architectures. Marcus Bortel Field Application Engineer QNX Software Systems

Central Processing Unit

(Cat. No SI) Product Data

GUJARAT TECHNOLOGICAL UNIVERSITY, AHMEDABAD, GUJARAT. COURSE CURRICULUM COURSE TITLE: COMPUTER ORGANIZATION AND ARCHITECTURE (Code: )

OpenSPARC T1 Processor

How To Write A Profibus Dpl (Profibus) Program

Obj: Sec 1.0, to describe the relationship between hardware and software HW: Read p.2 9. Do Now: Name 3 parts of the computer.

Read this before starting!

lesson 1 An Overview of the Computer System

Programming Interface. for. Bus Master IDE Controller. Revision 1.0

Chapter 10: Virtual Memory. Lesson 03: Page tables and address translation process using page tables

Computer and Set of Robots

Lesson Objectives. To provide a grand tour of the major operating systems components To provide coverage of basic computer system organization

Chapter 1 Computer System Overview

SIEMENS S

Chapter 6, The Operating System Machine Level

Introduction. What is an Operating System?

Am186ER/Am188ER AMD Continues 16-bit Innovation

ENGG*44200 Real Time System Design Lab3 Implement VoIP on ARM Outline

What is involved in input/output? How does the operating system manage I/O?

Engr. M. Fahad Khan Lecturer Software Engineering Department University Of Engineering & Technology Taxila

PROGRAMMING CONCEPTS AND EMBEDDED PROGRAMMING IN C, C++ and JAVA: Lesson-4: Data Structures: Stacks

13 Managing Devices. Your computer is an assembly of many components from different manufacturers. LESSON OBJECTIVES

State-Machine Replication

Microtronics technologies Mobile:

Computer Organization. and Instruction Execution. August 22

SIMATIC. C7-621, C7-621 AS-i Control Systems. Volume 2 Working with C7 A B C D E. Contents. User Information. Introduction. Startup.

Advanced Computer Architecture-CS501. Computer Systems Design and Architecture 2.1, 2.2, 3.2

COMPONENTS in a database environment

Application Architectures

MICROPROCESSOR AND MICROCOMPUTER BASICS

System Calls and Standard I/O

Traditional IBM Mainframe Operating Principles

PART B QUESTIONS AND ANSWERS UNIT I

IOS110. Virtualization 5/27/2014 1

Memory unit. 2 k words. n bits per word

Chapter 2 Logic Gates and Introduction to Computer Architecture

Introduction the Serial Communications Huang Sections 9.2, 10.2 SCI Block User Guide SPI Block User Guide

Learning Outcomes. Simple CPU Operation and Buses. Composition of a CPU. A simple CPU design

APPENDIX A - ON-LINE CONFIGURATION

Bandwidth Calculations for SA-1100 Processor LCD Displays

Eight Ways to Increase GPIB System Performance

Chapter 12: Multiprocessor Architectures. Lesson 09: Cache Coherence Problem and Cache synchronization solutions Part 1

Central Processing Unit (CPU)

Chapter 07: Instruction Level Parallelism VLIW, Vector, Array and Multithreaded Processors. Lesson 05: Array Processors

AQA GCSE in Computer Science Computer Science Microsoft IT Academy Mapping

Faculty of Engineering Student Number:

Quectel Cellular Engine

PIC Programming in Assembly. (

Operating Systems. Lecture 03. February 11, 2013

Transcription:

Chapter 11: Input/Output Organisation Lesson 06: Programmed IO

Objective Understand the programmed IO mode of data transfer Learn that the program waits for the ready status by repeatedly testing the status bit(s) and data transfer is only when other end ready 2

Three modes of transfer of device data, commands and status (i) Programmed IO (ii) Interrupt driven IO (iii) Direct memory access (DMA) 3

Programmed IO mode input data transfer 4

Read Input in Programmed IO mode (i) Each input is read after first testing whether the device is ready with the input (a state reflected by a bit in a status register) or whether the device input buffer is not empty 5

Input read by the processor in programmed I/O mode 6

Input read in Programmed IO mode The program waits for the ready status by repeatedly testing the status bit(s) and till all targeted bytes are read from the input device The program is in busy (non-waiting) state only after the device gets ready else in wait state 7

Programmed IO mode output data transfer 8

Output write in Programmed IO mode (ii) Each output written after first testing whether the device is ready to accept the byte(s) at its output register or output buffer is empty 9

Output write in Programmed IO mode 10

Output write in Programmed IO mode The program waits for the ready status by repeatedly testing the status bit(s) and till all the targeted bytes are written to the device The program in busy (non-waiting) state only after the device gets ready else wait state 11

Advantage and Disadvantage Programmed IO mode data transfer 12

Advantage of programmed I/O mode A program and processor dedicated to wait and repeatedly tests the status and for IO data transfer till the IO operation completes 13

Disadvantage of programmed I/O mode A program has to wait and repeatedly tests the status; Waiting period for an asynchronous event can be too large Many I/O devices generate asynchronous events events that occur at times that the processor cannot predict or control, but which the processor must respond to reasonably quickly to provide acceptable performance 14

Example of Unpredictable wait events Keyboard on a workstation or PC The processor cannot predict when the user will press a key but must react to the key-press in well under a second or the response time will be noticeable to the user The programmed I/O mode therefore not appropriate due to prolonged wait states 15

Summary 16

We Learnt Programmed IO method of IO operations The program waits for the ready status by repeatedly testing the status bit(s) and data transfer is only when other end ready 17

End of Lesson 06 on Programmed IO 18