PLOT Showcase Nov. 23 rd 2011

Transcription

1 PLOT Showcase Nov. 23 rd 2011 Accelerated Stress Testing Electronic Packaging and Interconnects Erik Veninga - TNO Technical Sciences

2 1 Contents TNO Technical Sciences Materials for Integrated Products Reliability Research In-situ Accelerated Lifetime Testing LEDs MOEST & Finite Element Modelling Examples current Projects New Accelerated Test Concept De-Rated Strength Testing Summarising

3 De missie van TNO TNO verbindt mensen en kennis om innovaties te creëren die de concurrentiekracht van bedrijven en het welzijn van de samenleving duurzaam versterken. Van idee naar innovatie: Ontwikkelen fundamentele kennis Kennisontwikkeling Kennistoepassing Kennisexploitatie Samen met universiteiten Samen met partners Samen met klanten Verankeren in de markt

4 TNO: bij wet opgericht in 1932 Artikel 4 TNO wet De Organisatie heeft ten doel ertoe bij te dragen dat op toepassing gericht technisch- en natuurwetenschappelijk onderzoek en daarmee te verbinden sociaal-wetenschappelijk en ander op toepassing gericht onderzoek op doelmatige wijze dienstbaar wordt gemaakt aan het algemeen belang en de daarbinnen te onderscheiden deelbelangen. TNO helpt bedrijven en overheden met behoefte aan specifieke R&D TNO is onafhankelijk van publieke of private belangen

5 Expertisegebieden Technical Sciences Behavioural and Societal Sciences Earth, Environmental and Life Sciences Thema s: TNO Technical Sciences in Eindhoven. Advisering Contractresearch Testen en certificeren Licenties Uitvoeren wettelijke taken

6 5 Materials for Integrated Products Structure and Bonding Performance Prediction Making Measuring Modelling

7 6 Challenges 2nd Level Interconnects LEDs Hour LED Lifetime in Practice Hours in Years Thermal Cycles [log] Hours on per Day Hours on per Day Hours in Years. Thermal cycles (on/off only).

8 7 Accelerated Lifetime Testing LED Interconnects Forward voltage as in-situ failure indicator for degradation: 60 solder joints 50 die-attach wire bonds Vf [V] V f [V] If [ma] Vf [V] OK Failed N cyc N cycles Crack in 2 nd level solder joint HB-LED Begin crack propagation Open contact

9 Lifetime of Solar Panels Lifetime solar panels typically 20 to 30 years Panels mainly qualified by industry standard tests (e.g. IEC and 61646) New approaches needed to design lifetime and reduce TTM Testing and modelling with basis in physics of failure

10 MEOST & Finite Element Modelling (FEM) Multi-physics modelling of critical overstress test conditions V Destruct V MPOSL 3p bending deflection Reverse bias Temperature cycling 10.7 mm 22 V, 19 A 9.10 mm 18.7 V, 16.2 A -70 to +180 C* V MPOSL = VDesign Destruct Design + [( V V ) 0.7] 100 Cumulative Percent Failure MEOST Bending Cycles 9 mm Deflection 8 mm Deflection

11 10 Other Examples Present Reliability Projects Remaining lifetime of electronics Performance electronics components when using new control circuitry / approach Investigation of newly discovered failure mode in High Brightness LED Performance of unusual substrate material in LED package Development of screening method to detect black pads on PCBs (Printed Circuit Boards)

12 11 Accelerated Testing and making Inferences Basic approach: 1) Identify dominant failure mechanism 2) Conduct accelerated tests at different levels 3) Estimate probability density function (PDF) 4) Model life-stress relations Making Stress Strength Inferences:

13 12 Reliability Trends Electronic products get more complex Higher reliability levels (two single digit ppm levels equipment) Reduction lead times product development / validation cycles (TTM) Traditional ways of testing can t keep up with technology trends Operational conditions moving towards accelerated test levels Designed lifetimes Product Life Cycle** Failure levels: TTT and TTM in product cycle: New Product Process* Introduction Growth Maturity Decline Preliminary investigation Detailed investigation Development Test & validation Launch & full production Stage I Stage II Stage III Stage IV TTM Stage V Product decline TTT

14 13 Possible Strategies to further shorten Accelerated Reliability Tests Increasing stress / frequencies levels till beyond current accelerated test levels Combining test loadings (incl. usage rate acceleration) Increasing rate of applying loadings Intentionally inducing interaction effects between loadings Using alternative loadings (to initiate the same failure mechanism)

15 14 Challenges when further Accelerating Tests Maintaining the correlation between failure behaviour during tests and field conditions Avoiding complex tests and analysis methods when using multi environment tests Example: Z-axis expansion when increasing test temperatures above the Tg of Printed Circuit Boards

16 15 Use of De-rated Strength Testing Moderate multi environment stresses Different sensitivity levels (use of Design of Experience) Design optimisation and prediction with modelling techniques

17 De-rated Strength Vehicle: testing 2 nd Level Interconnects LTCC Interposer on FR4 Test Board: SnAgCu v SnBi Solder Balls Daisy Chain LTCC Test Board (FR4) 125 Temperature [ C] RT Time [min] -40

18 From selection significant Factors to designed Test Conditions Design of Experiments: L12- SnAgCu Contribution Factors: Scree Creep Strain [%] 3 2,5 2 1,5 1 0,5 0 CTE LTCC [ppm/k] 4,3 6,7 Young's Modulus [GPa] Thickness LTCC [µm] Stand-off [mm] 0,36 0,6 Substrate size [mmxmm] 8x8 12x12 Final diameter [mm] 0,6 0,8 Matrix Full Depopulated MSS Creep Strain [%] 0,2 0,18 0,16 0,14 0,12 0,1 0,08 0,06 0,04 0,02 0 Thickness LTCC Stand-off Substrate size Final diameter Factor K Matrix Factor H Young's Modulus Factor I CTE LTCC Factor J Significant Factors > De-rated Design Model: Regression Analysis 4 SnAgCu SnBi Coefficients Standard Error t Stat P-value Lower 95% Upper 95% Lower 95,0% Upper 95,0% Intercept 1,643 0, , , , , , , Thickness LTCC [µm] 0, , , ,94115E-05 0, , , , Stand-off [mm] -4, , , , , , , , Substrate size [mm x mm] 0, , , , , , , , Final diameter [mm] -2,165 0, , , , , , , Creep Strain [%] Linear Model 3,5 3 2,5 2 1,5 1 0,5 R 2 = 0, ,5 1 1,5 2 2,5 3 3,5 4 Creep Strain [%] FEM

19 18 Designed Test Times: SnBi Example Test Cycles to Failure of De-Rated Test Strengths Nominal Design SnBi Substrate thickness: 600 um Stand-off: 0.53 mm Substrate size: 10mmx10mm Nf [-] SnBi Design De-rating Factor [%]

20 19 Summarising

21 20 Thank you for your attention!

22 21 Erik Veninga TNO Technical Sciences Materials for Integrated Products De Rondom 1, P.O. Box HE Eindhoven Tel: +31 (0) / Mob: +31 (0) l