United States Patent [191 [11] Patent Number: 4,779,221 Magliocco et al. [45] Date of Patent: Oct. 18, 1988

Transcription

1 United States Patent [191 [11] Patent Number: 4,779,221 Magliocco et al. [45] Date of Patent: Oct. 18, 1988 [54] TIMING SIGNAL GENERATOR 4,063,308 12/1977 Collins et a /900 4,231,104 10/1980 St. Clair..... [75] Inventors: Paul D. Magliocco, Mllpltas; Steven R. Bristow, San Jose, both of Calif. Primary EXamm" GafBIh D- Shaw _, Assistant Examiner -John G. Mills, III. [73] Ass'gnee: Mergatest Corpomnon San Jose Attorney, Agent, or Firm-Alan H. MacPherson; Paul J. Ca 1f Winters; Norman R. Klivans [21] App]. No.: 8,212 [57] ABSTRACT [22] Filed: Jan A unique timing system is provided which allows for a [51] Int. Cl G06F 9/00 user to program timing events with variable periods and [52] US. Cl edges from a?xed frequency clock, and having resolu [58] Field of Search /200, 900 tion greater than that of the?xed reference frequency. [56] References Cited Delay elements, which are inherently expensive, inac curate, and require repeated calibration, are minimized. U.S. PATENT DOCUMENTS 3,473,325 11/ 1969 Deters et a / Claims, 4 Drawing Sheets 11 /10 Oscillator LOAD >Tosc / / 'rc / 18 -> w A (Cquotient-l) (2+1 MUX 7 Memory > Counter 7 3 >Tload 7 Select Cremainder CPU /3/ /4 /6 6-2 Carry.I carry 6 1 Memory Adder Sum Register F v >Tof f s e: Sgincidenoe Tload m 13 out Bquot ient Eremainder Toffset 200

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6 1 TIMING SIGNAL GENERATOR 4,779,221 BACKGROUND OF THE INVENTION This invention pertains to timing signal generation, particularly suitable for use in a computerized test sys tem such as that used for testing integrated circuits. Means for testing integrated circuits are well known in the art. Modern systems include the use of a digital computer which is programmed to generate speci?c timing signals for application to a device under test (DUT), and appropriate supply, ground, and other volt ages required to simulate the actual operating environ ment of the DUI. As integrated circuit devices grow larger, the need for more accurate, high speed, inexpen sive, and repeatable testing techniques, including means for generating the appropriate timing signals, are re quired. However, in order to obtain high speed, accu rate, and repeatable timing signals, techniques have been employed which become increasingly expensive. Furthermore, many of these techniques, even though expensive, are not really as accurate or repeatable as desired. One such prior art technique for generating timing signals is described in US. Pat. No. 4,231,104 issued Oct. 28, 1982, St. Clair. St. Clair provides that an oscil lator, such as a crystal oscillator, is used to provide a clock signal. This clock signal is applied to a period generator circuit, which allows a period of desired length to be generated from the crystal oscillator. St. Clair utilizes a counter to count an integral number of clocks from the crystal oscillator and a delay line to interpolate between clock cycles in order that the per iod generated need not have a period equal to an inte gral numberp of clock cycles of the crystal oscillator. Furthermore, St. Clair, due to the manner in which he generates his timing signal edges, requires the period generated to provide two output signals: Tm, which is a delayed version of the crystal oscillator clock signal, 40 and Tom, the actual period signal. St. Clair requires the use of a delay line in order to provide these signals Tgyn and To, so that they are interpolated and thus not nec essarily aligned with the crystal oscillator clock edge. Such delay lines typically comprise a rather long trace 45 on a printed circuit board, thus requiring a rather large area on the printed circuit board and thus being expen sive. Other types of delay lines which can be used are lumped inductor capacitor ladders or networks, which again are expensive. Furthermore, regardless of the type of delay line used, the delay line circuit must be carefully calibrated, thereby requiring additional cali bration circuitry which is expensive and in itself diffi cult to maintain. Furthermore, even once a I5 delay line circuit is calibrated, it is still subject to errors which are dependent on duty cycle and which cannot be removed by further calibration. The delay line circuit can easily drift out of calibration requiring extensive maintenance of the circuit for recalibration, and errors may be in duced due to jitter caused by attenuation of the tim ing signal with an attendant alteration of the rise and fall times, and cross talk between the timing signal passing through the delay line and surrounding signals in the system. Yet another problem with prior art systems is their need to broadcast" variable length Tm signal to many locations in a typical, large system, with inherent degradation in timing occurring due to transmission line effects, and variations among the several transmission 2 lines used for broadcasting to various locations within the system. St. Clair also provides a waveform generator which receives as input signals the Tm and To, signals from the period generator. The waveform generator of St. Clair FIG. 2 includes two edge generator circuits and a wave formatter (60). Each of St. Clair s edge generators includes memory which de?nes the placement of the edge within a period based on coincidence with a counter contained within the waveform generator. Fur thermore, for each edge generator St. Clair provides an additional delay line in order to place the edge at a point which is interpolated between points provided by the period generator. As previously mentioned, these delay line circuits have severe disadvantages. Furthermore, in St. Clair s structure, the delay lines contained within the waveform generator have the potential of delaying the signal up to two times the period of the crystal oscilla tor. This introduces additional error. An additional disadvantage to St. Clair s waveform generator is the fact that each edge generator within the waveform generator can provide only a single edge during a given period. In addition, by the use of the various delay lines in St. Clair, timing signals within the circuit are not synchro nized with the crystal oscillator, thereby making design. calibration, and debugging of such a timing system quite complex and frustrating. SUMMARY In accordance with the teachings of this invention, a unique timing system is provided which allows for a user to program timing events with variable periods and edges from a?xed frequency clock, and having resolu tion greater than that of the?xed reference frequency. In accordance with the teachings of this invention, delay elements, which are inherently expensive, inaccu~ rate, and require repeated calibration, are minimized. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram of one embodiment of a period generator constructed in accordance with the teachings of this invention; FIG. 2 is a block diagram of one embodiment of an edge generator constructed in accordance with the teachings of this invention; FIG. 3 is a timing diagram depicting one embodiment of the operation of the strucutures of FIG. 1 and FIG. 2; and FIG. 4 is a block diagram of another embodiment of an edge generator constructed in accordance with the teachings of this invention. DETAILED DESCRIPTION FIG. 1 is a block diagram of one embodiment of a period generator constructed in accordance with the teachings of this invention. Although we refer to the structure of FIG. 1 as a period generator", it will be readily appreciated by those of ordinary skill in the art in light of the teachings of this invention that the period generator of FIG. 1, unlike prior art period generators, does not provide output signals which provide an actual period, but rather provide digital information which de?ne the period. This digital information is used by the edge generator of FIG. 2 (described later) in order to provide the resultant output signals from the edge gen erator of FIG. 2.

7 4,779,221 3 Referring to FIG. 1, oscillator l is any suitable oscil lator, such as a crystal oscillator. For the purpose of this description, certain time periods will be described, al though it is to be understood that the structure of this invention can be implemented using any desired timing periods. For example, oscillator 1 is a crystal oscillator providing a very stable l6 nanosecond period, as is well known in the art. Period generator 100 also includes CPU 18 which serves to load memories 2 and 3 with appropriate information de?ning the period desired to be generated. In order to store appropriate data in mem ories 2 and 3, CPU 18 divides the desired period by the period of oscillator l and determines a C quotient which is the integral number of oscillator 1 clock periods which will?t in the desired period, and the C remain der, which is the interpolation required between clock cycles of oscillator 1. The C quotient is stored in mem ory 2, and the C remainder is stored in memory 3 which are, for example, emitter coupled logic RAMs. In es sence, the actual number stored in memory 2 is a num 20 ber which causes counter 5 to count C quotient clock ticks per period. Counter 5 includes an input lead which receives the oscillator signal from oscillator 1. Counter 5 also in cludes a bus for receiving the number stored in memory 25 2, and a load input lead which causes counter 5 to load the data provided by memory 2 upon receipt of a T1004 signal which is generated when counter 5 has counted C quotient clock signals during this period. Counter 5 provides two output signals, a terminal count signal TC 30 and a terminal count +l signal TC+ l. The TC signal goes active when counter 5 has received C quotient clock signals from oscillator 1, and the TC+1 output signal goes active when counter 5 has received (C quo tient+ l) clock signals from oscillator 1 following the 35 most recent Tlmd signal. It is necessary to provide both output signals TC and TC+ l, with one of the two output signals chosen as a function of C remainder, as described below. Adder 4 serves to provide the summation of C re mainder values required to provide proper interpolation from period to period. For example, for an unchanging period, if C remainder is 2 nanoseconds, during the?rst period the interpolation must be 2 nanoseconds, during the second period, it must be 4 nanoseconds, during the 45 third period it must be 6 nanoseconds, etc. until the interpolation becomes equal to or greater than the per iod of oscillator l, in the example of FIG. 3, l6 nanosec onds. In this event, the T0,, y signal becomes active, causing multiplexer 7 to select the TC + 1 output signal from counter 5 as the Tioad signal. For an embodiment where the period of oscillator l is 16 nanoseconds, and the desired resolution of the period is l nanosecond, adder 4 is a 4-bit adder and C remainder is a 4-bit num ber. This increases by 1 bit for each doubling of the 55 period of oscillator l, or halving of the resolution of the period. Adder 4 provides a carry and a sum output signal to register 6. Register 6 stores the sum received from adder 4 which indicates the interpolation factor required for this period. This interpolation factor is provided on bus 6-1 as data word T-offset. The Tmrry signal is also stored in register 6 and provided on output lead 6-2 to the select input lead of multiplexer 7, which causes multiplexer 7 to select either the TC or TC-l-l signal from counter 5, as required. The To?rmdata is also 65 applied to one input lead of adder 4, causing adder 4 to add the T-offset value with the C remainder value to provide a new carry and sum result for the next period. 4 Thus, period generator 100 provides output signals Tm, the clock signal from oscillator l, and T1004, a signal which restarts the edge generator counter for each period, although not necessarily at the precise beginning of that period, as is more fully described below with regard to the edge generator of FIG. 2. The relationship between the T10 signal and when a new period starts is de?ned by the Tome, data. In accordance with the teachings of this invention, a?xed frequency clock and a digital data word are used to broadcast period and length timing reference information to a plurality of locations, while avoiding the degradation in the clock signal for changing period length, since trans mission line errors for?xed frequency clock signals are easily compensated, as is well known in the art. In one embodiment of this invention, C quotient is the actual quotient as determined by the CPU. In this event, counter 5 counts from 1 to C quotient in response to the output signal from oscillator 1. The TC signal goes active when counter 5 reaches the value of C quotient. and the TC+1 signal goes active when counter 5 reaches C quotient +1. In an alternative embodiment of this invention, memory 2 stores C quotient l, and counter 5, following each load signal, decrements from C quotient 1 to O. In this event, output signal TC goes active when counter 5 reaches 0, and TC + 1 signal goes active when counter 5 reaches l count beyond 0, i.e. rolls over to all ones. This is a particularly attractive approach, since it is quite easy to detect a binary num ber which consists of either all zeros (TC active) or all ones (TC+1 active). FIG. 2 depicts one embodiment of an edge generator constructed in accordance with the teachings of this invention. As will become apparent to those of ordinary skill in the art from the following discussion, edge gen erator 2 is capable of providing a plurality of edges during a signal period, utilizing a single hardware cir cuit and a single delay line. Memory 10 is loaded by CPU 18 prior to testing of a DUT with values calcu lated assuming Toff ; is equal to zero. Edge generator 200 serves to adjust the placement of edges when Tome, is not equal to zero. Memory 10 can include a plurality of data words de?ning a plurality of edges within a period. Also, memory 10 can include a plurality of such sets of data in order to have readily available such a plurality of edge de?nitions for a plurality of different period types. Counter 8 serves to address memory 10 to select the desired data word from memory 10. Counter 8 receives from CPU 18 the base address (i.e. the?rst address within a set of addresses). Alternatively, counter 8 receives this information from a high speed pattern generator, well known in the art. Counter 8 also receives the To signal which allows counter 8, when enabled by active LOAD or INC signals, to change its output state. When the LOAD signal is active, indicat ing a new period, new data from CPU 18 (alternatively a pattern generator, not shown) is loaded into counter 8 in order to access a new page of memory 10. Similarly, when the INC signal is active, counter 8 increments its count to access the next word of the selected page within memory 10, causing memory 10 to provide a data output word de?ning the next edge required to be generated in that period. The data output word from memory 10 can specify that an edge is to be generated within an integral num ber of Tm cycles from the Tload signal, and an interpola tion factor which allows the edge to be generated be tween two adjacent To signals. Furthermore, since

8 4,779,221 5 Tzoad is in fact offset from the period beginning by Toff. m, the Elime data signal from memory 10 and the Tome, value received from period generator 100 of FIG. 1 are added by adder 12 to provide an output signal Ewan-en, and Emmamde, which de?nes precisely where the edge is to be placed with respect to Tom output signal which is enabled by Tload. To affect this, register 11 stores T017, in response to the T1,, signal when clocked by the To,C signal, in order that the Toff, value will be readily available to adder 12. The most signi?cant bits from adder 12 provide the Ewan-em value from adder l2 and the least signi?cant bits provide the Eremm'mje, value from adder 12. In the example where oscillator 1 has a 16 nanosecond period and desired edge placement reso lution is l nanosecond, Equmiem is determined by the longest period desired to be generated and Eremmde, is 4 bits long. Thus, Equotiem de?nes the number of TN signals which must be counted prior to generation of the edge, and Eremainde, de?nes the amount of delay which must be provided by delay line 14 prior to gener 20 ation of the edge. Counter 9 counts Tm signals follow ing its clear by a Tgoad signal. Counter 9 provides a Tmum output signal applied to coincidence detector 13. Coincidence detector 13 provides an output pulse to delay line 14 when T count equals Equo?'em. The amount 25 that this pulse is delayed by delay line 14 is determined by the value of Eremaindw. This provides the desired To, signal which is, for example, applied to a wave formatter (not shown) in order to produce the desired wave form. Such wave formatters are well known in 30 the art and thus will not be described here. The output pulse from coincidence detector 13 is also applied via lead 15 to the INC input lead of counter 8, enabling counter 8 to increment and address the next word of the selected page of memory 10, as previously described. 35 FIG. 3 depicts various timing signals for the embodi ments of FIGS. 1 and 2, when To is 16 nsec, the period length is 52 nsec and T0, pulses are generated at 0 nsec and 24 nsec from a period start. Of importance, a cycle marker is shown in FIG. 3 for reference only, and does not actually appear as an output signal anywhere in the circuit FIG. 4 depicts another embodiment of an edge gener ator 400 constructed in accordance with the teachings of this invention. The structure of FIG. 4 serves to 45 minimize the width of the adder used, thereby simplify ing the circuit and enhancing the speed. The structure of FIG. 4 separates the output bits from memory 10 to provide E?m MSB and Eu'me LSB. The Eame LSB is the interpolation factor stored in memory 10 as loaded by CPU 18. CPU 18 computes Etime LSB and E?me MSB assuming T05, is zero. Edge generator 400 serves to adjust the placement of the edges when Tome; is not equal to zero. En-m LSB and Toff, are added by adder 120 which provides an Eremamder output signal and a 55 carry signal. The Eume MSB is applied to coincidence detector 130 which operates to detect when the number of To clock signals counted by counter 9 is equal to Ema MSB. At this time, coincidence detector 130 pro vides an output signal indicating that an edge is to be generated. The carry signal from adder 120 serves to indicate when the output signal from coincidence detec tor 130 should be delayed a single To count. When required, this single count delay is provided by digital delay circuit 98 which is well known in the art, and in 65 one embodiment comprises a one bit shift register and a multiplexer whih selects either the input signal or the output signal from the one bit shift register. Thus, digi 6 tal and delay circuit 98 delays the output signal from coincidence detector 130 by a single To count, and provides the E remainder signal to delay line 14 follow ing this digital delay. The speci?c embodiments of this invention described in this speci?cation are intended to serve by way of example and are not a limitation on the scope of my invention. Numerous other embodiments of this inven tion will become apparent to those of ordinary skill in the art in light of the teachings of this speci?cation. I claim: 1. A timing system comprising: means for receiving a?xed frequency clock signal; a?rst memory for storing a value which de?nes the number of said clock signals within an output per iod to be generated; a second memory for storing a value which de?nes the fraction of a period of said clock signal needed to be added to said number of said clock signals within an output period in order to provide said output period to be generated; a counter having a first input terminal for receiving said clock signal, a second input terminal for re ceiving a LOAD signal to cause said counter to begin to count clock signals for a new period, a?rst output lead for providing a?rst output signal when said number of said clock signals has been counted, and a second output lead for providing a second output signal when one additional clock signal is counted following said?rst output signal; means for selecting said?rst or said second output signal of said counter as said LOAD signal; an adder for providing a?rst output signal de?ning the fractional portion of a period of said clock signal required to generate said period to be gener ated and adding said value in said second memory and said?rst output signal of the previous adder operation, said adder also providing a second out put signal de?ning when the sum of said value in said second memory and said?rst output signal of the previous adder operation is greater than or equal to the period of said clock signal; means for applying said second output signal of said adder to said means for selecting such that when said second output signal of said adder indicates said sum is greater than or equal to the period of said clock signal said means for selecting selects said second output signal of said counter as said LOAD signal and when said second output signal of said adder indicates said sum is less than the period of said clock signal said means for selecting selects said?rst output signal of said counter as said LOAD signal; wherein said LOAD signal de?nes the start of a new period synchronized to the closest previous clock signal and said?rst output signal of said adder de?nes the relationship between said LOAD signal and the actual start of said period to be generated. 2. The structure of claim 1 wherein said?rst and second memories are loaded from a CPU. 3. The structure of claim 1 wherein said?rst and second memories each contain a plurality of values, each said value de?ning a different period to be gener ated. 4. The structure of claim 1 wherein addressing of said?rst and second memories is controlled by a counter. 5. The structure of claim 3 wherein addressing of said?rst and second memories is controlled by a CPU.

9 7 6. The structure of claim 3 wherein addressing of said?rst and second memories is controlled by a high-speed pattern generator. 7. The structure as in claim 1 wherein said?rst output signal of said adder is a sum and said second output signal of said adder is a carry 4,779, The structure as in claim 1 wherein said means for applying is a register. 9. The structure as in claim 7 wherein said register is enabled to load by said LOAD signal. 10. The structure as in claim 8 wherein said LOAD signal is synchronous with said clock signal. 11. The structure as in claim 1 wherein operation is synchronous with said clock signal. # 1 i I i