PXI Express Integrating PCI Express into the PXI Backplane

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2 PXI Express Integrating PCI Express into the PXI Backplane National Instruments This session introduces PXI Express. 2

3 PCI Express Overview Serial interconnect at 2.5 Gbits/s PCI transactions are packetized and then serialized Low-voltage differential signaling, point-to-point, 8B/10B encoded x1 (by 1) has bandwidth of 250 Mbytes/s/direction x16 (by 16) has bandwidth of 4 Gbytes/s/direction Uses same software model as PCI Ensures software compatibility Roadmap for longevity with Gen-2 clocking (5 Gbits/s) PCI Express was introduced to improve upon the PCI bus platform. The most notable PCI Express advancement over PCI is its point-to-point bus topology. The shared bus used for PCI is replaced with a shared switch, which provides each device its own direct access to the bus. Unlike PCI, which divides bandwidth between all devices on the bus, PCI Express provides each device with its own dedicated data pipeline. Data is sent serially in packets through pairs of transmit and receive signals called lanes, which enable 250 MBytes/s bandwidth per direction, per lane. Multiple lanes can be grouped together into x1 ( by-one ), x2, x4, x8, x12, x16, and x32 lane widths to increase bandwidth to the slot. PCI Express dramatically improves data bandwidth compared to PCI buses, minimizing the need for onboard memory and enabling faster data streaming. For instance, with a x16 slot, users can achieve up to 4 GB/s of dedicated bandwidth as opposed to the 132 MB/s shared across all devices of the 32 bit, 33 MHz PCI. 3

4 PCI Express Desktop Cards PCIe-GPIB Instrument Control (x1) PCIe-1429 Image Acquisition (x4) PCIe Graphics Card (x16) Examples of Different PCI Express Link Widths: x1, x4, and x16 Here is a picture of several different PCI Express card types. The different connector sizes from a x1 (read by 1 ), x4, and x16 provide scalable bandwidth that is available per device. Most PCI Express desktop computers provide a x16 slot for PCI Express graphics cards, and this slot provides bandwidth of 4 GBytes/s. For implementation in industrial vision and other applications that require significant bandwidth, a x4 implementation provides 1 GBytes/s. 4

5 Bandwidth vs. Latency Increasing (Improving) Bandwidth Max Bandwidth (MB/s) Good Better Best PCI Express (x4) PCI/PXI (32/33) Gigabit Ethernet USB 2.0 IEEE 1394a Fast Ethernet VME/VXI GPIB (HS 488) USB 1.1 GPIB (488.1) Approximate Latency (µs) Decreasing (Improving) Latency When considering the technical merits of alternative buses, bandwidth and latency are two of the most important bus characteristics. Bandwidth measures the rate at which data is sent across the bus, typically in MBytes/s, while latency measures the inherent delay in data transmission across the bus. By analogy, if we were to compare an instrumentation bus to a road, bandwidth would correlate to the width of the road and the speed of travel, while the latency would correlate to the number of stoplights in the road. A bus with high bandwidth would be able to transmit more data in a given period than a bus with low bandwidth. A bus with low, meaning good, latency would introduce less of a delay between the time data was transmitted on one end and processed on the other end. Most users recognize the importance of bandwidth since it affects whether data can be sent as fast as it is acquired and how much onboard memory their instruments will need. Latency, while less observable, has a direct impact on applications such as digital multimeter (DMM) measurements, switching, and instrument configuration, since it affects how quickly a command sent from one node on the bus, such as the PC controller, arrives at and is processed at another node, such as the instrument. 5

6 Dedicated Bandwidth per Device Unlike PCI, which divides bandwidth between all devices on the bus, PCI Express provides each device with its own dedicated data pipeline. Thus, as multiple PCI Express devices are added to a system, the total bus throughput scales linearly. 6

7 PCI Express Industry Adoption First PCI Express desktops shipped mid 2004 First ExpressCard laptops shipped January 2005 PCI and PCI Express are side-by-side in all Intel/Dell roadmaps Primary consumer drive is graphics processing (gamers, video editing) PCIe x16 replacing AGP As with any new bus, there will be a delayed adoption by the marketplace. PCI Express desktops began shipping mid 2004, and ExpressCard laptops started shipping in early All of the roadmaps from Intel and Dell currently have the PCI and PCIe slots side-by-side for many years to come this is a good thing for technology continuity and will help you preserve and continue your existing investment in PCI. Also, one of the initial drivers for PCI is the graphics processing capabilities from the higher bandwidth. 7

8 Dell Dimension Slots (January 2006) Dimension 1100 Dimension 3000 Dimension 3100 Dimension 4700 Dimension 5150 Dimension 5100c Dimension 9150 Dimension XPS 600 PCI Slots PCI Express Slots This table illustrates that fact that desktop PCs have a mix of both PCI and PCI Express slots. Both PCI and PCI Express will be integrated into chipsets through Thus, mainstream PCs will include both PCI and PCI Express slots during this same period. Again, this will help you preserve and continue your existing investment in PCI. 8

9 High-Speed Bus Interface Forecast High Speed Bus Interface Shipments Interfaces (Millions) PCI Express Hypertransport Fibrechannel 10G Ethernet Rapid I/O Starfabric Infiniband Switch Semiconductor Price Forecasts 2004 Cost 2008 Est Cost PCI Express x4 Switch $ $ 2.42 Gigabit Ethernet Switch $ $ 1.68 Advanced Switching Switch $ $ 5.40 Infiniband Switch $ $ Gigabit Ethernet Switch $ 1, $ Source: Advanced Bus and Interface Markets and Trends, 2004 As technology adoption increases, the price per component decreases, and this fuels even greater adoption. With PCI Express the future growth in interface units is expected to increase rapidly while the cost of components is expected to decrease. PCI Express technology is also forecasted to outpace the growth of all other high speed bus interface shipments and dominate the PC bus peripheral market as the dominant technology, while providing a x4 switch cost comparable to Gigabit Ethernet. Note: Gigabit Ethernet is not included on the High Speed Bus interfaces graph because it is a peripheral device technology that uses bandwidth of the interface bus. 9

10 PCI Express Advantages Software compatibility High throughput (up to > 4 GB/s) Scalable bandwidth Dedicated bandwidth per slot Peer-to-peer communication Long life (20+ years in mainstream market) The main advantages of PCI Express are the following: Software compatibility High throughput (up to > 4 GBytes/s) Scalable bandwidth Dedicated bandwidth per slot Peer-to-peer communication Long life (20+ years in mainstream market) 10

11 Step #1: PCI Express Control of PXI Laptop ExpressCard PCI Express Desktop PCI Express PCI Express 110 MB/s sustained throughput Taking advantage of PCI Express in the PXI platform is a two step process. The first step is to use PCI Express across a cable, or cabled PCI Express, to control PXI systems (both existing and new). Using cabled PCI Express, you can achieve the highest sustained throughput for remote control of PXI (110 Mbytes/s) from both desktop and laptop PCs. 11

12 Step #2: Integrating PCI Express into the PXI Backplane 6 GB/s backplane Enhanced synchronization capabilities 100 MHz differential clock, differential triggering Backwards compatibility Complete software compatibility Hybrid slot definition - install modules with either PCI or PCI Express signaling in a single slot The next step is to integrate the PCI Express bus into the PXI backplane. The PXI Express backplane integrates PCI Express while still preserving compatibility with current PXI modules, users benefit from increasing bandwidth while maintaining backward compatibility with existing systems. PXI Express specifies hybrid slots to deliver signals for both PCI and PCI Express. With PCI Express electrical lines connecting the system slot controller to the hybrid slots of the backplane, PXI Express provides a high bandwidth path from the controller to backplane slots. Using an inexpensive PCI Express-to-PCI bridge, PXI Express provides PCI signaling to all PXI and PXI Express slots to ensure compatibility with PXI modules on the backplane. With the ability to support up to a x16 PCI Express link in addition to a x8 link, the system controller slot provides a total of 6 GB/s bandwidth to the PXI Express backplane, representing more than a 45X improvement in PXI backplane throughput. 12

13 Increased BW Enables New Applications PXI applications requiring PCI bandwidth General purpose automated test (DMMs, switching, baseband instruments, etc) General purpose data acquisition (AI, AO, DIO, etc) Bus interfaces (CAN, 1553, ARINC, etc) Motion control PXI applications requiring PCI Express bandwidth High frequency, resolution IF / RF systems High speed digital interfaces High channel count data acquisition High speed imaging The integration of PCI Express into PXI will allow the platform to reach new applications. Examples include the following: High frequency, resolution IF / RF systems High speed digital interfaces High channel count data acquisition High speed imaging However, many existing PXI applications will not benefit from the enhanced performance of PXIe. For example, hardware such as digital multimeters (DMMs), switches, industrial I/O, bus interfaces, and many mainstream generators and analyzers will not benefit from the additional backplane bandwidth. Thus, one of the most valuable aspects of the PXI Express specification is its ability to route both PCI and PCI Express signaling to new slots. As a result, engineers should not expect instrument manufacturers to redesign all current boards for PXI Express; rather, many instrument manufacturers will continue to base PXI products on PCI signaling since the current PCI architecture serves the need and PCI signaling is provided to all slots. 13

14 PXI PXI Express Star Trigger 100 MHz Differential CLK SYNC MHz CLK PXIe System Controller PXIe System Timing Controller SYNC Control PXIe Peripheral Hybrid Peripheral PXI Peripheral Differential Star Triggers PXI Trigger Bus (8 TTL Triggers) PXI Express not only retains the timing and synchronization features of PXI, but it also adds several new synchronization features by taking advantage of the existing differential connectors required in PXI and technological advances that provide higher performance, low-cost differential signaling. Building on these existing capabilities in PXI, PXI Express provides the additional timing and synchronization features of a differential system clock, differential signaling, and differential star triggers, as shown in Figure 4. By using differential clocking and synchronization, PXI Express systems benefit from increased noise immunity for instrumentation clocks and the ability to transmit at higher frequency clocks. In addition to allowing engineers to improve the performance of the system, high-frequency clocks also match well with modern processes and allow lower cost products to remove clock multiplication circuits. With the industry s best synchronization and latency, PXI Express improves the measurement accuracy and test time of high bandwidth applications. 14

15 PXI and Hybrid Slots Ensure Compatibility The first PXI Express chassis will provide PXI peripheral slots. Additionally, by taking advantage of the available pins on the high-density PXI backplane, the PXI Express hybrid slots are capable of delivering signals for both PCI and PCI Express. In doing so, these PXI Express hybrid slots provide backward compatibility that is not available with desktop PC card-edge connectors, where a single slot cannot support both PCI and PCI Express signaling. Thus, the hybrid slot allows you to install a PXI module that uses PCI signaling or a future high-performance PXI Express module that uses PCI Express signaling. In addition to providing hardware compatibility through hybrid slots, PXI Express systems also provide software compatibility so that engineers can preserve their investment in existing software. PCI Express software compatibility is guaranteed through the PCI Special Interest Group (PCI- SIG) which includes companies like Intel and Dell. Because PCI Express uses the same driver and OS model as PCI, the specification guarantees that engineers have complete software compatibility among PCI-based systems, for example PXI, and PCI Express-based systems, such as PXI Express. As a result, both vendors and customers do not need to change driver or application software for PCI Express-based systems. By maintaining software compatibility between PCI and PCI Express technology, the specification drastically reduces cost for vendors and integrators to insert new PCI Express technology into existing test systems. With hardware compatibility provided by the hybrid slot and software compatibility, the cost of adding PXI Express technology is minimal. 15

16 Compatibility of PXI and Hybrid Slots x8 PCIe (up to 2 GB/s) Differential Clk. 100 & Star Triggers Power Trigger Bus Star Trigger Clk /33 PCI (132 MB/s per system) Reserved Pins 64/66 PCI Local Bus (typically unused) Hybrid PXI A PXI Express hybrid slot provides compatibility with PXI modules with PCI signaling and will support future PXI Express modules with PCI Express signaling. Additionally, a hybrid slot supports both PXI timing and synchronization features and PXI Express timing and synchronization features. The hybrid slot is defined in the PXI Express Specification. 16

17 Creating a Hybrid Slot Compatible PXI Module XJ4 J2 J1 1. Start with a PXI peripheral module 2. Depopulate J2 3. Populate XJ4 In order for a PXI peripheral module to be hybrid slot compatible, the J2 connector is depopulated and the XJ4 connector is populated. ECN-1 of Revision 2.2 of the PXI-1 Hardware Specification in May 2005 introduced this process. PXI peripheral module vendors will begin transitioning their products (existing and future) to be hybrid slot compatible. It is also possible to modify most PXI peripheral modules that are not hybrid slot compatible to be hybrid slot compatible. 17

18 Hybrid Slot Flexibility PXI Express Peripheral Module 32-bit CompactPCI Module Hybrid Slot Compatible PXI Module A hybrid slot can support a wide range of PXI modules including PXI Express peripherals, CompactPCI peripherals, and hybrid slot compatible PXI peripherals. 18

19 DEMO: Hybrid Slot Add a hybrid-slot-compatible PXI peripheral module to a PXI Express chassis Use the module with no software changes This demonstration introduces a PXI Express system. Additionally, the compatibility, both hardware and software, between PXI and PXI Express is demonstrated. 19

20 Timeline and Organizations PCI Industrial Manufacturers Group (PICMG) January 2003: CompactPCI Express research April 2004: CompactPCI Express spec officially started June 2005: CompactPCI Express (EXP.0) spec passage February 2006: First chassis and controllers released PXI Systems Alliance (PXISA) May 2005: PXI Express spec officially started June 2005: PXI-1 ECN for hybrid-slot-compatible PXI modules August 2005: PXI-5 PXI Express HW spec passage September 2005: PXI-6 PXI Express SW spec passage Spring 2006: First chassis and controllers released PXI Express and CompactPCI Express product rollout throughout 2006/7 In order to successfully integrate PCI Express into CompactPCI and PXI and still maintain backward compatibility, the PICMG ( and the PXISA ( executed coordinated plans to ensure a smooth transition. Since PXI is based on the CompactPCI specification, these efforts to integrate PCI Express first began with CompactPCI Express in early Defining the fundamental mechanical and electrical features of CompactPCI Express systems, the CompactPCI Express specification in turn defines the mechanical and electrical features of PXIe systems. Released June 27, 2005, the CompactPCI Express specification includes the selection of connectors to support PCI Express, definitions of slots and board mechanicals, definitions of slots and board electrical signals, and compliance-testing requirements. In May 2005, work on the PXIe specification began, and in September 2005 the PXIe specification passed. The PXIe specification takes the CompactPCI Express technology and adds specifications for PXI compatibility, timing and synchronization, and system software frameworks. 20