NTP Precision Time Synchronization
|
|
|
- Emmeline Ramsey
- 9 years ago
- Views:
Transcription
1 NTP Precision Time Synchronization David L. Mills University of Delaware alautun, Maya glyph From pogo, Walt Kelly 5-Jul-08 1
2 Precision time performance issues Improved clock filter algorithm reduces network jitter Operating system kernel modifications achieve time resolution of 1 ns and frequency resolution of.001 PPM using NTP and PPS sources. With kernel modifications, residual errors are reducec to less than 2 μs RMS with PPS source and less than 20 μs over a 100-Mb LAN. New optional interleaved on-wire protocol minimizes errors due to output queueing latencies. With this protocol and hardware timestamps in the NIC, residual errors over a LAN can be reduced to the order of PPS signal. Using external oscillator or NIC oscillator as clock source, residual errors can be reduced to the order of IEEE 1588 PTP. Optional precision timing sources using GPS, LORAN-C and cesium clocks. 5-Jul-08 2
3 Part 1 quick fixes Assess errors due to kernel latencies Reduce sawtooth errors due to software frequency discipline Reduce network jitter using the clock filter Minimize latencies in the operating system and network 5-Jul-08 3
4 Errors due to kernel latencies (a) Latency for getimeofday() Call (b) Latency Distribution for (a) These graphs were constructed using a Digital Alpha and OSF/1 V3.2 with precision time kernel modifications (a) Measured latency for gettimeofday() call spikes are due to timer interrupt routine (b) Probability distribution for (a) measured over about ten minutes Note peaks near 1 ms due timer interrupt routine, others may be due to cache reloads, context switches and time slicing Biggest surprise is very long tail to large fractions of a second 5-Jul-08 4
5 Sawtooth errors due to software frequency discipline θ Adjustment Interval σ +S A C t ε S Adjustment Rate R ϕ B Frequency Error ϕ Unix adjtime() slews frequency at net rate R ϕ PPM beginning at A Slew continues to B, depending on the programmed frequency offset S Offset continues to C with frequency offset due to error ϕ 1 1 If ε x, then R ϕ + S and σ + x ϕ R ϕ For ε = 100 μs, ϕ = 200 PPM, S = 200 PPM, this requires R 400 PPM and σ 1 s These are almost completely eliminated using kernel discipline 5-Jul-08 5
6 Cumulative distribution function of network latencies This cumulative distribution function is from the same day as the time offset slide The rightmost curve represents raw offsets received over the network. The left curve represents the offsets after the clock filter algorithm. 5-Jul-08 6
7 CDF in log-log coordinates long term P[Offset < y] Offset (ms) These data are from other sources The interesting observation is that these lines are almost straight, but with different slope. The awesome fact is they keep going. 5-Jul-08 7
8 Latencies in the operating system and network Cryptosum Output Wait Network Input Wait Cryptosum and Protocol Processing Time T 3b Timestamp T 3a Timestamp T 3 Timestamp T 4 Timestamp T 4a Timestamp We want T 3 and T 4 timestamps for accurate network timing If output wait is small, T 3a is good approximation to T 3 T 3a can t be included in message after cryptosum is calculated, but can be sent in next message; if not, use T 3b as best approximation to T 3 T 4a is captured at soft-queue interrupt time, so is a fairly good estimator for T 4. Largest error is usually cryptosum and output wait With software timestamping, T 3 is captured upon return from the sendpacket routine, typically 200 μs after T 3a. With interleaved protocol, T 3 is transmitted in the next packet. See and related briefing. 5-Jul-08 8
9 Measured latencies with software interleaved timestamping The interleaved protcool captures T 3b before the message digest and T 3 after the send-packet routine. The difference varies from 16 μs for a dual-core, 2.8 GHz Pentium 4 running FreeBSD 5.1 to 1100 μs for a Sun Blade 1500 running Solaris 10. On two identical Pentium machines in symmetric mode, the measured output delay T 3b to T 3 is 16 μs and interleaved delay 2x T 3 to T 4a is μs. Four switch hops at 100 Mb accounts for 40 μs, which leaves μs at each end for input delay. The RMS jitter is μs. On two identical UltraSPARC machines running Solaris 10 in symmetric mode, the measured output delay T 3b to T 3 is 160 μs and interleaved delay 2x T 3 to T 4a is 390 μs. Four switch hops accounts for 40 μs, which leaves about 175 μs at each end for input delay. The RMS jitter is μs. A natural conclusion is that most of the jitter is contributed by the network and input delay. 5-Jul-08 9
10 So, how well does it work? We measure the max, mean and standard deviation over one day The mean is an estimator of the offset produced by the clock discipline, which is essentially a lowpass filter. The standard deviation is a estimator for jitter produced by the clock filter. Following are three scenarios with modern machines and Ethernets The best we can do using the precision time kernel and a PPS signal from a GPS receiver. Expect residual errors in the order of 2 μs dominated by hardware and operating system jitter. The best we can do using a workstation synchronized to a primary server over a fast LAN using optimum poll interval of 15 s. Expect residual errors in the order of 20 μs dominated by network jitter. The best we can do using a workstation synchronized to a primary server over a fast LAN using typical poll interval of 64 s. Expect errors in the order of 200 μs dominated by oscillato rwander. Next order of business is the interleaved on-wire protocol and hardware timestamping. The goal is improving network perfomance to PPS level. 5-Jul-08 10
11 Time characteristis with PPS kernel discipline Machine is Pentium II 300 MHz running FreeBSD 6.1 and synchronized to a GPS receiver via a PPS signal and parallel port Precision nanokernel PPS discipline NTP4 is configured at fixed poll interval 4 (16 s) Behavior appears largely determined by hardware/kernel latencies 5-Jul-08 11
12 Time offset CDF with PPS kernel discipline Same configuration as previous slide Note log-log coordinates Offset statistics: max μs, mean μs, stdev μs 5-Jul-08 12
13 Frequency characteristis with PPS kernel discipline Same configuration as previous slide Comparison with the time offset characteristics suggest the dominant error contribution is latency jitter rather than frequency discipline. Compare with later data on a typical machine over a fast LAN 5-Jul-08 13
14 Time characteristis with fast LAN and poll 16 s Machine is UltraSPARC II running Solaris 10 and synchronized to a primary server connected to GPS receiver via a PPS signal NTP4 is configured at fixed poll interval 4 (16 s) Behavior appears largely determined by 100 Mb Ethernet latencies 5-Jul-08 14
15 Time offset CDF with fast LAN and poll 16 s Same configuration as previous slide Note log-log coordinates Offset statistics: max μs mean μs stdev μs About ten times worse than PPS signal 5-Jul-08 15
16 Frequency characteristis with fast LAN and poll 16 s Same configuration as previous slide Comparison with the time offset characteristics suggest the dominant error contribution is latency jitter rather than frequency discipline. Compare with earlier data with a PPS signal 5-Jul-08 16
17 Time characteristis with fast LAN and poll 64 s Machine is Pentium 2.8 GHz running FreeBSD 6.1 and synchronized to a CDMA receiver on a 100 Mb switched Ethernet CDMA receiver claimed accuracy is 10 μs NTP4 is configured at fixed poll interval 6 (64 s) Behavior appears largely determined by oscillator wander 5-Jul-08 17
18 Frequency characteristis with fast LAN and poll 64 s These data are from the same day as the time offset slide The curve approximates the integral of the time offset data This clearly confirms the errors are primarily due to frequency wander Accuracy improves as the poll interval is reduced, but not below 16 s due increased frequency wander 5-Jul-08 18
19 Not so-quick fixes Autokey public key cryptography Avoids errors due to cyrptographic computations See briefing and specification Precision time nanokernel Improves time and frequency resolution Avoids sawtooth error Improved driver interface Includes median filter Adds PPS driver External oscillator/nic oscillator With interleaved protocol, performance equivalent to IEEE 1588 LORAN C receiver and precision clock source 5-Jul-08 19
20 Avoid inline public-key algorithms: the Autokey protocol Source Address Dest Address Key ID Last Session Key MD5 Hash (Session Key) Session Key List RSA Encrypt Server Private Key Next Key ID Server Key Server rolls a random 32-bit seed as the initial key ID Server generates a session key list using repeated MD5 hashes Server encrypts the last key using RSA and its private key to produce the initial server key and provides it and its public key to all clients Server uses the session key list in reverse order, so that clients can verify the hash of each key used matches the previous key Clients can verify that repeated hashes will eventually match the decrypted initial server key 5-Jul-08 20
21 Kernel modifications for nanosecond resolution Nanokernel package of routines compiled with the operating system kernel Represents time in nanoseconds and fraction, frequency in nanoseconds per second and fraction Implements nanosecond system clock variable with either microsecond or nanosecond kernel native time variables Uses native 64-bit arithmetic for 64-bit architectures, double-precision 32-bit macro package for 32-bit architectures Includes two new system calls ntp_gettime() and ntp_adjtime() Includes new system clock read routine with nanosecond interpolation using process cycle counter (PCC) Supports run-time tick specification and mode control Guaranteed monotonic for single and multiple CPU systems 5-Jul-08 21
22 NTP clock discipline with nanokernel assist NTP θ r + θ c Phase Detector V d Clock Filter V s NTP Daemon 1 GHz VFO V c Clock Adjust Loop Filter x y Phase/Freq Prediction Kernel PPS Type II, adaptive-parameter, hybrid phase/frequency-lock loop disciplines variable frequency oscillator (VFO) phase and frequency NTP daemon computes phase error V d = θ r θ o between source and VFO, then grooms samples to produce time update V s Loop filter computes phase x and frequency y corrections and provides new adjustments V c at 1-s intervals VFO frequency adjusted at each hardware tick interrupt 5-Jul-08 22
23 Nanokernel phase/frequency prediction NTP Update V s PLL/FLL Discipline x y PPS Interrupt PPS Discipline x y Switch x y PLL/FLL discipline predicts phase x and frequency y at averaging intervals from 1 s to over one day. PPS discipline predicts x and y at averaging intervals from 4 s to 128 s, depending on nominal Allan intercept. On overflow of the clock second, new values for time θ and frequency φ offset are calculated. Phase adjustment αθ + φ is added to system clock for α < 1 at every tick interrupt, then θ is reduced by (1 α)θ. 5-Jul-08 23
24 NTP phase and frequency discipline Check and Groom x NTP Update V s FLL Freq Average y FLL Switch y PLL Freq Integrate y PLL x is the phase correction initially set at the update value. y FLL is the frequency prediction computed as the average of past update differences. y PLL is the frequency prediction computed as the integral of past update values. The switch controlled by the API selects which of y FLL or y PLL are used. 5-Jul-08 24
25 PPS phase and frequency discipline Second Offset Latch Median Filter Check and Groom x PPS Interrupt Range Gate Frequency Discrim Scaled PCC 1 GHz Latch Check and Groom Frequency Average y Phase and frequency disciplined separately - phase from system clock second offset, frequency from processor cycle counter (PCC) Frequency discriminator rejects noise and invalid signals Median filter rejects sample outlyers and provides error statistic Check and groom rejects popcorn spikes and clamps outlyers Phase offsets exponentially averaged with variable time constant Frequency offsets averaged over variable interval 5-Jul-08 25
26 Nanosecond clock Time of Day Add Interpolation Scale 1 GHz System Clock PCC 433 MHz 1024 Hz Timer Add z Hz Second x z = + y τ x x = x τ Phase x and frequency y are updated by the PLL/FLL or PPS loop. At the second overflow increment z is calculated and x reduced by the time constant. The increment is amortized over the second at each tick interrupt. Time between ticks is interpolated from the PCC scaled to 1 GHz. 5-Jul-08 26
27 Reference clock drivers Peer Filter 1 Reference Driver PPS Driver Filter 2 Filter 3 Selection and Clustering Algorithms Combining Algorithm System Process Loop Filter Clock Adj. Proc. Clock Drivers Peer Processes VFO Reference clock drivers work just like NTP peers. Active drivers produce timecode message in response to poll message. Passive drivers provide timecode registers that can be read by poll routine. PPS driver augments prefer peer for precision time. Offset only within the second; seconds numbering must be provided by reference driver or NTP peer. PPS believed only if prefer peer correct and within 128 ms. 5-Jul-08 27
28 Reference clock driver interface Receive Driver Parse Timecode Driver Timestamp Poll System Clock Timestamp Median Filter Clock Filter PPS (optional) Driver timecode is read either by timecode message interrupt or poll routine. Timecode and associated data are parsed according to specific format. Offset is computed between driver timestamp and system clock timestamp. Offsets accumulate in median filter shift register until processed and sent to clock filter.. Optional PPS signal (PPS driver only) provides offset in second. 5-Jul-08 28
29 Minimize effects of serial port hardware and driver jitter Graph shows raw jitter of millisecond timecode and 9600-bps serial port Additional latencies from 1.5 ms to 8.3 ms on SPARC IPC due to software driver and operating system; rare latency peaks over 20 ms Latencies can be minimized by capturing timestamps close to the hardware Jitter is reduced using median/trimmed-mean filter of 60 samples Using on-second format and filter, residual jitter is less than 50 μs 5-Jul-08 29
30 Precision time and frequency sources KSI/Odetics TPRO IRIG-B SBus interface Provides direct-reading microsecond clock in BCD format Synchronized to GPS receiver using IRIG-B signal Supported both as an NTP driver and as kernel system clock Stabilizes time to 1 μs and frequency to 0.1 PPM Precision oven-stabilized system clock SBus memory-mapped interface Provides direct-reading microsecond clock in Unix timeval format Supported as kernel system clock Stabilizes time via radio or NTP and frequency to.005 PPM PPS discipline Driver or kernel interface via modem control line Stabilizes frequency to.001 PPM relative to external 1-PPS source Stabilizes time within 1 μs with seconds numbered by NTP 5-Jul-08 30
31 Hardware clock discipline 0-999,999 μs Latch Read 0-999,999 μs Latch Read Counter Counter VCXO f f/n Prescaler TCXO f f/n DDS ±1 DAC Latch Latch a I/O Bus b Analog (a) and digital (b) frequency discipline methods Analog method uses voltage-controlled low-frequency oscillator. Digital method uses direct digital synthesis and high-frquency oscillator. Either method could be used in a NIC or bus peripheral 5-Jul-08 31
32 Gadget Box PPS interface Used to interface PPS signals from GPS receiver or cesium oscillator Pulse generator and level converter from rising or falling PPS signal edge Simulates serial port character or stimulates modem control lead Also used to demodulate timecode broadcast by CHU Canada Narrowband filter, 300-baud modem and level converter The NTP software includes an audio driver that does the same thing 5-Jul-08 32
33 LORAN-C timing receiver Inexpensive second-generation bus peripheral for IBM 386-class PC with oven-stabilized external master clock oscillator Includes 100-kHz analog receiver with D/A and A/D converters Functions as precision oscillator with frequency disciplined to selected LORAN-C chain within 200 ns of UTC(LORAN) and stability PC control program (in portable C) simultaneously tracks up to six stations from the same LORAN-C chain Intended to be used with NTP to resolve inherent LORAN-C timing ambiguity 5-Jul-08 33
34 Further information NTP home page Current NTP Version 3 and 4 software and documentation FAQ and links to other sources and interesting places David L. Mills home page Papers, reports and memoranda in PostScript and PDF formats Briefings in HTML, PostScript, PowerPoint and PDF formats Collaboration resources hardware, software and documentation Songs, photo galleries and after-dinner speech scripts Udel FTP server: ftp://ftp.udel.edu/pub/ntp Current NTP Version software, documentation and support Collaboration resources and junkbox Related projects Current research project descriptions and briefings 5-Jul-08 34
Survivable, Real Time Network Services
Survivable, Real Time Network Services Defense Advanced Research Projects Agency Contract F30602-98-1-0225, DARPA Order G409 Quarterly Progress Report 1 January 1999-31 March 1999 David L. Mills Electrical
Network Time Protocol (NTP) General Overview
Network Time Protocol (NTP) General Overview David L. Mills University of Delaware http://www.eecis.udel.edu/~mills mailto:[email protected] alautun, Maya glyph 2-Aug-04 1 Introduction Network Time Protocol
Internet Timekeeping Around the Globe 1,2
Internet Timekeeping Around the Globe 1,2 David L. Mills 3, Ajit Thyagarjan and Brian C. Huffman Electrical and Computer Engineering Department University of Delaware Abstract This paper describes a massive
Precision Time Protocol (PTP/IEEE-1588)
White Paper W H I T E P A P E R "Smarter Timing Solutions" Precision Time Protocol (PTP/IEEE-1588) The Precision Time Protocol, as defined in the IEEE-1588 standard, provides a method to precisely synchronize
HANDBOOK. Measuring System DESIGN EDITORS PETER H. SYDENHAM RICHARD THORN ARTICLE OFFPRINT
HANDBOOK OF Measuring System DESIGN EDITORS PETER H. SYDENHAM RICHARD THORN ARTICLE OFFPRINT 200: Calibrations and Standards in Time Measurement Michael A. Lombardi National Institute of Standards and
3.7. Clock Synch hronisation
Chapter 3.7 Clock-Synchronisation hronisation 3.7. Clock Synch 1 Content Introduction Physical Clocks - How to measure time? - Synchronisation - Cristian s Algorithm - Berkeley Algorithm - NTP / SNTP -
Precision Time Protocol on Linux ~ Introduction to linuxptp
Precision Time Protocol on Linux ~ Introduction to linuxptp Ken ICHIKAWA FUJITSU LIMITED. LinuxCon Japan 2014 Copyright 2014 FUJITSU LIMITED Agenda Background Overview of Precision Time Protocol (PTP)
Timer A (0 and 1) and PWM EE3376
Timer A (0 and 1) and PWM EE3376 General Peripheral Programming Model Each peripheral has a range of addresses in the memory map peripheral has base address (i.e. 0x00A0) each register used in the peripheral
Secure SCADA Communication Protocol Performance Test Results
PNNL-17118 Secure SCADA Communication Protocol Performance Test Results M.D. Hadley K.A. Huston August 2007 Prepared for U.S. Department of Energy Office of Electricity Delivery and Energy Reliability
The Role of Precise Timing in High-Speed, Low-Latency Trading
The Role of Precise Timing in High-Speed, Low-Latency Trading The race to zero nanoseconds Whether measuring network latency or comparing real-time trading data from different computers on the planet,
Evaluating the Accuracy of Maxim Real-Time Clocks (RTCs)
REAL-TIME CLOCKS Application Note 632: Aug 01, 2001 Evaluating the Accuracy of Maxim Real-Time Clocks (RTCs) This app note describes methods for measuring the accuracy of the Maxim Real-Time Clocks (RTCs)
Optimizing VCO PLL Evaluations & PLL Synthesizer Designs
Optimizing VCO PLL Evaluations & PLL Synthesizer Designs Today s mobile communications systems demand higher communication quality, higher data rates, higher operation, and more channels per unit bandwidth.
MicroMag3 3-Axis Magnetic Sensor Module
1008121 R01 April 2005 MicroMag3 3-Axis Magnetic Sensor Module General Description The MicroMag3 is an integrated 3-axis magnetic field sensing module designed to aid in evaluation and prototyping of PNI
A High Resolution Performance Monitoring Software on the Pentium
A High Resolution Performance Monitoring Software on the Pentium Ong Cheng Soon*, Fadhli Wong Mohd Hasan Wong**, Lai Weng Kin* * Software Lab, MIMOS Berhad [email protected], [email protected] ** Dept of Electrical
Wide Area Monitoring, Control, and Protection
Wide Area Monitoring, Control, and Protection Course Map Acronyms Wide Area Monitoring Systems (WAMS) Wide Area Monitoring Control Systems (WAMCS) Wide Area Monitoring Protection and Control Systems (WAMPACS)
Computer Time Synchronization
Michael Lombardi Time and Frequency Division National Institute of Standards and Technology Computer Time Synchronization The personal computer revolution that began in the 1970's created a huge new group
Distributed Synchronization
CIS 505: Software Systems Lecture Note on Physical Clocks Insup Lee Department of Computer and Information Science University of Pennsylvania Distributed Synchronization Communication between processes
DS1104 R&D Controller Board
DS1104 R&D Controller Board Cost-effective system for controller development Highlights Single-board system with real-time hardware and comprehensive I/O Cost-effective PCI hardware for use in PCs Application
Design Issues in a Bare PC Web Server
Design Issues in a Bare PC Web Server Long He, Ramesh K. Karne, Alexander L. Wijesinha, Sandeep Girumala, and Gholam H. Khaksari Department of Computer & Information Sciences, Towson University, 78 York
Time Calibrator. 2013 Fountain Computer Products
Time Calibrator Time Calibrator All rights reserved. No parts of this work may be reproduced in any form or by any means - graphic, electronic, or mechanical, including photocopying, recording, taping,
A PC-BASED TIME INTERVAL COUNTER WITH 200 PS RESOLUTION
35'th Annual Precise Time and Time Interval (PTTI) Systems and Applications Meeting San Diego, December 2-4, 2003 A PC-BASED TIME INTERVAL COUNTER WITH 200 PS RESOLUTION Józef Kalisz and Ryszard Szplet
DAC Digital To Analog Converter
DAC Digital To Analog Converter DAC Digital To Analog Converter Highlights XMC4000 provides two digital to analog converters. Each can output one analog value. Additional multiple analog waves can be generated
Synchronization in. Distributed Systems. Cooperation and Coordination in. Distributed Systems. Kinds of Synchronization.
Cooperation and Coordination in Distributed Systems Communication Mechanisms for the communication between processes Naming for searching communication partners Synchronization in Distributed Systems But...
Enabling Open-Source High Speed Network Monitoring on NetFPGA
Network Operations and Management Symposium (NOMS) 2012 Enabling Open-Source High Speed Network Monitoring on NetFPGA Gianni Antichi, Stefano Giordano Email: @iet.unipi.it Department of Information
CLOCK AND SYNCHRONIZATION IN SYSTEM 6000
By Christian G. Frandsen Introduction This document will discuss the clock, synchronization and interface design of TC System 6000 and deal with several of the factors that must be considered when using
DEVELOPMENT OF DEVICES AND METHODS FOR PHASE AND AC LINEARITY MEASUREMENTS IN DIGITIZERS
DEVELOPMENT OF DEVICES AND METHODS FOR PHASE AND AC LINEARITY MEASUREMENTS IN DIGITIZERS U. Pogliano, B. Trinchera, G.C. Bosco and D. Serazio INRIM Istituto Nazionale di Ricerca Metrologica Torino (Italia)
A Laser Scanner Chip Set for Accurate Perception Systems
A Laser Scanner Chip Set for Accurate Perception Systems 313 A Laser Scanner Chip Set for Accurate Perception Systems S. Kurtti, J.-P. Jansson, J. Kostamovaara, University of Oulu Abstract This paper presents
Tivoli IBM Tivoli Web Response Monitor and IBM Tivoli Web Segment Analyzer
Tivoli IBM Tivoli Web Response Monitor and IBM Tivoli Web Segment Analyzer Version 2.0.0 Notes for Fixpack 1.2.0-TIV-W3_Analyzer-IF0003 Tivoli IBM Tivoli Web Response Monitor and IBM Tivoli Web Segment
Glitch Free Frequency Shifting Simplifies Timing Design in Consumer Applications
Glitch Free Frequency Shifting Simplifies Timing Design in Consumer Applications System designers face significant design challenges in developing solutions to meet increasingly stringent performance and
Technical Bulletin. Enabling Arista Advanced Monitoring. Overview
Technical Bulletin Enabling Arista Advanced Monitoring Overview Highlights: Independent observation networks are costly and can t keep pace with the production network speed increase EOS eapi allows programmatic
The new frontier of the DATA acquisition using 1 and 10 Gb/s Ethernet links. Filippo Costa on behalf of the ALICE DAQ group
The new frontier of the DATA acquisition using 1 and 10 Gb/s Ethernet links Filippo Costa on behalf of the ALICE DAQ group DATE software 2 DATE (ALICE Data Acquisition and Test Environment) ALICE is a
Abstract. Cycle Domain Simulator for Phase-Locked Loops
Abstract Cycle Domain Simulator for Phase-Locked Loops Norman James December 1999 As computers become faster and more complex, clock synthesis becomes critical. Due to the relatively slower bus clocks
Non-Data Aided Carrier Offset Compensation for SDR Implementation
Non-Data Aided Carrier Offset Compensation for SDR Implementation Anders Riis Jensen 1, Niels Terp Kjeldgaard Jørgensen 1 Kim Laugesen 1, Yannick Le Moullec 1,2 1 Department of Electronic Systems, 2 Center
Section 3. Sensor to ADC Design Example
Section 3 Sensor to ADC Design Example 3-1 This section describes the design of a sensor to ADC system. The sensor measures temperature, and the measurement is interfaced into an ADC selected by the systems
TI GPS PPS Timing Application Note
Application Note Version 0.6 January 2012 1 Contents Table of Contents 1 INTRODUCTION... 3 2 1PPS CHARACTERISTICS... 3 3 TEST SETUP... 4 4 PPS TEST RESULTS... 6 Figures Figure 1 - Simplified GPS Receiver
Timing Errors and Jitter
Timing Errors and Jitter Background Mike Story In a sampled (digital) system, samples have to be accurate in level and time. The digital system uses the two bits of information the signal was this big
Contents. Connection Guide. What is Dante?... 2. Connections... 4. Network Set Up... 6. System Examples... 9. Copyright 2015 ROLAND CORPORATION
Contents What is Dante?............................................. 2 Outline.................................................. 2 Fundamental............................................ 3 Required Network
USB 3.0 CDR Model White Paper Revision 0.5
USB 3.0 CDR Model White Paper Revision 0.5 January 15, 2009 INTELLECTUAL PROPERTY DISCLAIMER THIS WHITE PAPER IS PROVIDED TO YOU AS IS WITH NO WARRANTIES WHATSOEVER, INCLUDING ANY WARRANTY OF MERCHANTABILITY,
Time Synchronization & Timekeeping
70072-0111-14 TECHNICAL NOTE 06/2009 Time Synchronization & Timekeeping Time synchronization lets you synchronize the internal clocks of all networked PowerLogic ION meters and devices. Once synchronized,
Computer Time Synchronization
Michael Lombardi Time and Frequency Division NIST email: [email protected] Computer Time Synchronization The personal computer revolution that began in the 1970's created a huge new group of time
APPLICATION NOTE GaGe CompuScope 14200-based Lightning Monitoring System
APPLICATION NOTE GaGe CompuScope 14200-based Lightning Monitoring System Challenge A customer needed to upgrade an older data acquisition unit for a real-time lightning monitoring system. Unlike many lightning
The Model A032-ET of Riga Event Timers
The Model A032-ET of Riga Event Timers V. Bespal ko, E. Boole, V. Vedin 1. Institute of Electronics and Computer Science, Riga, LATVIA. Contact: [email protected] Abstract The Event Timer A032-ET is an advanced
Communicating with devices
Introduction to I/O Where does the data for our CPU and memory come from or go to? Computers communicate with the outside world via I/O devices. Input devices supply computers with data to operate on.
Chapter 3 Operating-System Structures
Contents 1. Introduction 2. Computer-System Structures 3. Operating-System Structures 4. Processes 5. Threads 6. CPU Scheduling 7. Process Synchronization 8. Deadlocks 9. Memory Management 10. Virtual
How To Run A Gps Time Server In A Gpx Device In A Powerbox (Gps) On A Gpm (Gpl) Or Ipa (Gpt) Device
NTP Server/ GPS Network Time Server by EndRun Technologies in Singapore, Malaysia & Indonesia NTP Servers/ Network Time Servers manufactured by EndRun Technologies USA are highperformance, reliable and
QAM Demodulation. Performance Conclusion. o o o o o. (Nyquist shaping, Clock & Carrier Recovery, AGC, Adaptive Equaliser) o o. Wireless Communications
0 QAM Demodulation o o o o o Application area What is QAM? What are QAM Demodulation Functions? General block diagram of QAM demodulator Explanation of the main function (Nyquist shaping, Clock & Carrier
Kepware Technologies Optimizing KEPServerEX V5 Projects
Kepware Technologies Optimizing KEPServerEX V5 Projects September, 2010 Ref. 50.16 Kepware Technologies Table of Contents 1. Overview... 1 2. Factors that Affect Communication Speed... 1 2.1 Defining Bandwidth...
Choosing the correct Time Synchronization Protocol and incorporating the 1756-TIME module into your Application
Choosing the correct Time Synchronization Protocol and incorporating the 1756-TIME module into your Application By: Josh Matson Various Time Synchronization Protocols From the earliest days of networked
The Central Processing Unit:
The Central Processing Unit: What Goes on Inside the Computer Chapter 4 Objectives Identify the components of the central processing unit and how they work together and interact with memory Describe how
Clocks/timers, Time, and GPS
FYS3240 PC-based instrumentation and microcontrollers Clocks/timers, Time, and GPS Spring 2015 Lecture #11 Bekkeng, 22.12.2014 How good is a crystal oscillator (XO)? Interested in the long-term measurement
Gigabit Ethernet Packet Capture. User s Guide
Gigabit Ethernet Packet Capture User s Guide Copyrights Copyright 2008 CACE Technologies, Inc. All rights reserved. This document may not, in whole or part, be: copied; photocopied; reproduced; translated;
Precision Clock Synchronization
Hirschmann. Simply a Good Connection. White Paper Precision Clock Synchronization The Standard IEEE 1588 Precision Clock Synchronization IEEE 1588 White Paper Rev. 1.2 Table of contents Precision Clock
Selecting the Optimum PCI Express Clock Source
Selecting the Optimum PCI Express Clock Source PCI Express () is a serial point-to-point interconnect standard developed by the Component Interconnect Special Interest Group (PCI-SIG). lthough originally
find model parameters, to validate models, and to develop inputs for models. c 1994 Raj Jain 7.1
Monitors Monitor: A tool used to observe the activities on a system. Usage: A system programmer may use a monitor to improve software performance. Find frequently used segments of the software. A systems
PNOZmulti Configurator V8.1.1
General 1000 PNOZmulti 1.1 1100 General 1- ][Allgemein Configurator V8.1.1 This document contains important information, which must be noted. This document also contains details of the changes made in
Department of Electrical and Computer Engineering Ben-Gurion University of the Negev. LAB 1 - Introduction to USRP
Department of Electrical and Computer Engineering Ben-Gurion University of the Negev LAB 1 - Introduction to USRP - 1-1 Introduction In this lab you will use software reconfigurable RF hardware from National
Developing Wireless GPIB Test Systems Using the GPIB-ENET/100
Application Note 184 Developing Wireless GPIB Test Systems Using the GPIB-ENET/100 Introduction The National Instruments GPIB-ENET/100 expands the options for size, distance, environmental conditions,
Lecture 3 Theoretical Foundations of RTOS
CENG 383 Real-Time Systems Lecture 3 Theoretical Foundations of RTOS Asst. Prof. Tolga Ayav, Ph.D. Department of Computer Engineering Task States Executing Ready Suspended (or blocked) Dormant (or sleeping)
Phase coherency of CDMA caller location processing based on TCXO frequency reference with intermittent GPS correction
Phase coherency of CDMA caller location processing based on TCXO frequency reference with intermittent GPS correction Dingchen Lu, Alfredo Lopez, Surendran K. Shanmugam, John Nielsen and Gerard Lachapelle
The Lagopus SDN Software Switch. 3.1 SDN and OpenFlow. 3. Cloud Computing Technology
3. The Lagopus SDN Software Switch Here we explain the capabilities of the new Lagopus software switch in detail, starting with the basics of SDN and OpenFlow. 3.1 SDN and OpenFlow Those engaged in network-related
LoRa FAQs. www.semtech.com 1 of 4 Semtech. Semtech Corporation LoRa FAQ
LoRa FAQs 1.) What is LoRa Modulation? LoRa (Long Range) is a modulation technique that provides significantly longer range than competing technologies. The modulation is based on spread-spectrum techniques
Best Practises for LabVIEW FPGA Design Flow. uk.ni.com ireland.ni.com
Best Practises for LabVIEW FPGA Design Flow 1 Agenda Overall Application Design Flow Host, Real-Time and FPGA LabVIEW FPGA Architecture Development FPGA Design Flow Common FPGA Architectures Testing and
Extended Resolution TOA Measurement in an IFM Receiver
Extended Resolution TOA Measurement in an IFM Receiver Time of arrival (TOA) measurements define precisely when an RF signal is received, necessary in the identification of type and mode of RF and radar
CONTROL MICROSYSTEMS DNP3. User and Reference Manual
DNP3 User and Reference Manual CONTROL MICROSYSTEMS SCADA products... for the distance 48 Steacie Drive Telephone: 613-591-1943 Kanata, Ontario Facsimile: 613-591-1022 K2K 2A9 Technical Support: 888-226-6876
NIST Computer Time Services: Internet Time Service (ITS), Automated Computer Time Service (ACTS), and time.gov Web Sites
NIST Special Publication 250-59 NIST Computer Time Services: Internet Time Service (ITS), Automated Computer Time Service (ACTS), and time.gov Web Sites Judah Levine Michael A. Lombardi Andrew N. Novick
Serial Communications
Serial Communications 1 Serial Communication Introduction Serial communication buses Asynchronous and synchronous communication UART block diagram UART clock requirements Programming the UARTs Operation
Software Stacks for Mixed-critical Applications: Consolidating IEEE 802.1 AVB and Time-triggered Ethernet in Next-generation Automotive Electronics
Software : Consolidating IEEE 802.1 AVB and Time-triggered Ethernet in Next-generation Automotive Electronics Soeren Rumpf Till Steinbach Franz Korf Thomas C. Schmidt [email protected] September
Evaluating 1588v2 Performance Rev 2
Evaluating 1588v2 Performance Rev 2 Application Note IEEE 1588v2 is the preferred protocol for transport frequency and phase synchronization over Ethernet, which is required for 3G and 4G mobile networks.
Time Synchronization of Computer in secure manner while using Teleclock & NTP Services
Time Synchronization of Computer in secure manner while using Teleclock & NTP Services Shilpa 1 and Parveen Sharma 2 1 Research Scholar Shri Krishan Institute of Engineering & Technology, Kurukshetra University,
Atmel Norway 2005. XMEGA Introduction
Atmel Norway 005 XMEGA Introduction XMEGA XMEGA targets Leadership on Peripheral Performance Leadership in Low Power Consumption Extending AVR market reach XMEGA AVR family 44-100 pin packages 16K 51K
Chapter 6: From Digital-to-Analog and Back Again
Chapter 6: From Digital-to-Analog and Back Again Overview Often the information you want to capture in an experiment originates in the laboratory as an analog voltage or a current. Sometimes you want to
Swiss Time Systems. The new multipurpose time server for the LAN and NTP-based Distributed Time System. by MOBATIME DTS 4138.
Proud Partners with MOBATime GPS or DCF 77 MOBA-NMS (Network Management Sy The new multipurpose time server for the LAN and NTP-based Distributed Time System by MOBATIME DTS 4138.timeserver The DTS 4138.timeserver
Computer Systems Structure Input/Output
Computer Systems Structure Input/Output Peripherals Computer Central Processing Unit Main Memory Computer Systems Interconnection Communication lines Input Output Ward 1 Ward 2 Examples of I/O Devices
Below is a diagram explaining the data packet and the timing related to the mouse clock while receiving a byte from the PS-2 mouse:
PS-2 Mouse: The Protocol: For out mini project we designed a serial port transmitter receiver, which uses the Baud rate protocol. The PS-2 port is similar to the serial port (performs the function of transmitting
Real-time Process Network Sonar Beamformer
Real-time Process Network Sonar Gregory E. Allen Applied Research Laboratories [email protected] Brian L. Evans Dept. Electrical and Computer Engineering [email protected] The University of Texas
How To Monitor And Test An Ethernet Network On A Computer Or Network Card
3. MONITORING AND TESTING THE ETHERNET NETWORK 3.1 Introduction The following parameters are covered by the Ethernet performance metrics: Latency (delay) the amount of time required for a frame to travel
AVR131: Using the AVR s High-speed PWM. Introduction. Features. AVR 8-bit Microcontrollers APPLICATION NOTE
AVR 8-bit Microcontrollers AVR131: Using the AVR s High-speed PWM APPLICATION NOTE Introduction This application note is an introduction to the use of the high-speed Pulse Width Modulator (PWM) available
Delivering NIST Time to Financial Markets Via Common-View GPS Measurements
Delivering NIST Time to Financial Markets Via Common-View GPS Measurements Michael Lombardi NIST Time and Frequency Division [email protected] 55 th CGSIC Meeting Timing Subcommittee Tampa, Florida September
Hello, and welcome to this presentation of the STM32L4 reset and clock controller.
Hello, and welcome to this presentation of the STM32L4 reset and clock controller. 1 The STM32L4 reset and clock controller manages system and peripheral clocks. STM32L4 devices embed three internal oscillators,
Interfacing Analog to Digital Data Converters
Converters In most of the cases, the PIO 8255 is used for interfacing the analog to digital converters with microprocessor. We have already studied 8255 interfacing with 8086 as an I/O port, in previous
Simple SDR Receiver. Looking for some hardware to learn about SDR? This project may be just what you need to explore this hot topic!
Michael Hightower, KF6SJ 13620 White Rock Station Rd, Poway, CA 92064; [email protected] Simple SDR Receiver Looking for some hardware to learn about SDR? This project may be just what you need to explore
What You Will Learn About. Computers Are Your Future. Chapter 8. Networks: Communicating and Sharing Resources. Network Fundamentals
What You Will Learn About Computers Are Your Future Chapter 8 Networks: Communicating and Sharing Resources Basic networking concepts Advantages and disadvantages of networks Peer-to-peer and client/server
Performance Evaluation of Linux Bridge
Performance Evaluation of Linux Bridge James T. Yu School of Computer Science, Telecommunications, and Information System (CTI) DePaul University ABSTRACT This paper studies a unique network feature, Ethernet
Computer-System Architecture
Chapter 2: Computer-System Structures Computer System Operation I/O Structure Storage Structure Storage Hierarchy Hardware Protection General System Architecture 2.1 Computer-System Architecture 2.2 Computer-System
Description: Multiparameter System (4 or 8 channels)
Model MPA4, 8 ch acquisition system with 6 ns time tagging The MPA4 is a Multiparameter Data Acquisition System Description: Multiparameter System (4 or 8 channels) ADC Settings and Presets Dialog The
GPS NTP TIME SERVER Rack Version V2
GPS NTP TIME SERVER Rack Version V2 Description: Server is dedicated to synchronize network devices local time/date to Universal Time (UTC) Devices synchronizing own local time through the NTP V3 protocol.
HD Radio FM Transmission System Specifications Rev. F August 24, 2011
HD Radio FM Transmission System Specifications Rev. F August 24, 2011 SY_SSS_1026s TRADEMARKS HD Radio and the HD, HD Radio, and Arc logos are proprietary trademarks of ibiquity Digital Corporation. ibiquity,
Design and Implementation of One-way IP Performance Measurement Tool
Design and Implementation of One-way IP Performance Measurement Tool Jaehoon Jeong 1, Seungyun Lee 1, Yongjin Kim 1, and Yanghee Choi 2 1 Protocol Engineering Center, ETRI, 161 Gajong-Dong, Yusong-Gu,
AN NTP STRATUM-ONE SERVER FARM FED BY IEEE-1588
AN NTP STRATUM-ONE SERVER FARM FED BY IEEE-1588 Richard E. Schmidt and Blair Fonville Time Service Department, U.S. Naval Observatory 3450 Massachusetts Ave. NW, Washington, D.C. 20392, USA [email protected],
DEPARTMENT OF COMPUTER SCIENCE & ENGINEERING Question Bank Subject Name: EC6504 - Microprocessor & Microcontroller Year/Sem : II/IV
DEPARTMENT OF COMPUTER SCIENCE & ENGINEERING Question Bank Subject Name: EC6504 - Microprocessor & Microcontroller Year/Sem : II/IV UNIT I THE 8086 MICROPROCESSOR 1. What is the purpose of segment registers
White Paper. Real-time Capabilities for Linux SGI REACT Real-Time for Linux
White Paper Real-time Capabilities for Linux SGI REACT Real-Time for Linux Abstract This white paper describes the real-time capabilities provided by SGI REACT Real-Time for Linux. software. REACT enables
SYSTEM ecos Embedded Configurable Operating System
BELONGS TO THE CYGNUS SOLUTIONS founded about 1989 initiative connected with an idea of free software ( commercial support for the free software ). Recently merged with RedHat. CYGNUS was also the original
8-bit Microcontroller. Application Note. AVR134: Real-Time Clock (RTC) using the Asynchronous Timer. Features. Theory of Operation.
AVR134: Real-Time Clock (RTC) using the Asynchronous Timer Features Real-Time Clock with Very Low Power Consumption (4µA @ 3.3V) Very Low Cost Solution Adjustable Prescaler to Adjust Precision Counts Time,
The Bus (PCI and PCI-Express)
4 Jan, 2008 The Bus (PCI and PCI-Express) The CPU, memory, disks, and all the other devices in a computer have to be able to communicate and exchange data. The technology that connects them is called the
A Transport Protocol for Multimedia Wireless Sensor Networks
A Transport Protocol for Multimedia Wireless Sensor Networks Duarte Meneses, António Grilo, Paulo Rogério Pereira 1 NGI'2011: A Transport Protocol for Multimedia Wireless Sensor Networks Introduction Wireless
Using Network Time Protocol (NTP): Introduction and Recommended Practices
Using Network Time Protocol (NTP): Introduction and Recommended Practices International SEMATECH Manufacturing Initiative SEMATECH and the SEMATECH logo are registered service marks of SEMATECH, Inc. International
AVR32788: AVR 32 How to use the SSC in I2S mode. 32-bit Microcontrollers. Application Note. Features. 1 Introduction
AVR32788: AVR 32 How to use the SSC in I2S mode Features I²S protocol overview I²S on the AVR32 I²S sample rate configurations Example of use with AT32UC3A on EVK1105 board 32-bit Microcontrollers Application
Application of Android OS as Real-time Control Platform**
AUTOMATYKA/ AUTOMATICS 2013 Vol. 17 No. 2 http://dx.doi.org/10.7494/automat.2013.17.2.197 Krzysztof Ko³ek* Application of Android OS as Real-time Control Platform** 1. Introduction An android operating
