SAMA5D2. Scope. Reference Documents. Atmel SMART ARM-based MPU ERRATA

Transcription

1 SAMA5D2 Atmel SMART ARM-based MPU ERRATA Scope This document contains the known errata found on the following Atmel SMART ARM -based SAMA5D2 devices, and planned to be fixed in the next silicon version: ATSAMA5D22A-CN-ES ATSAMA5D27A-CN-ES ATSAMA5D24A-CU-ES ATSAMA5D28A-CN-ES Reference Documents Type Title Atmel Lit. No. Datasheet SAMA5D2 Series Datasheet 11267

2 Table of Contents 1. Errata ROM Code: SDMMC ROM Code: SPI ROM Code: QSPI ROM Code: RSA ROM Code: AES Customer Key diversification according to the Chip Unique ID ROM Code: Console Terminal on UARTs ROM Code: Main External Clock Frequency Support for SAM-BA Monitor ROM Code: Watchdog after SAM-BA Monitor Connection ROM Code: Console Terminal UART Baudrate ROM Code: JTAG Access Lock Unique Serial Number Fuse Masking Fuse Writing HSIC Startup ADC SleepWalking ADC Last Channel Low-speed Trigger ADC Trigger Events ACC Output SDMMC Software 'Reset For all' Command SDMMC Status Flag INTCLKS PMC GCLK Fields PMC SleepWalking CLASSD Peripheral FLEXCOM SMBUS TWIHS Clear Command MPDDRC tfaw Audio PLL SSC TD Output I2SC First Sent Data Quad I/O Serial Peripheral Interface (QSPI) Master/Processor Clock Prescaler Revision History

3 1. Errata 1.1 ROM Code: SDMMC ROM code v1.0 does not support emmc boot partition 1.2 ROM Code: SPI ROM code v1.0 SPI boot clock frequency is limited to 6 MHz 1.3 ROM Code: QSPI ROM code v1.0 does not support QSPI boot 1.4 ROM Code: RSA ROM code v1.0 does not support the RSA signature 1.5 ROM Code: AES Customer Key diversification according to the Chip Unique ID ROM code v1.0 does not support the Pairing mode 1.6 ROM Code: Console Terminal on UARTs ROM code v1.0 does not display the Secure Boot Mode string when running the secure boot sequence 3

4 1.7 ROM Code: Main External Clock Frequency Support for SAM-BA Monitor ROM code v1.0 supports ONLY a 12 MHz external clock frequency to allow USB connection to be used for SAM-BA Monitor 1.8 ROM Code: Watchdog after SAM-BA Monitor Connection Watchdog reset occurs when re-enabling the watchdog When no bootable program is found in an external memory, the Watchdog is disabled just before the ROM Code runs SAM-BA Monitor. The ROM code sets the Watchdog Timer Mode register (WDT_MR) to the value 0x and then clears the counter value. If a program loaded and executed using the SAM-BA Monitor Go command re-enables the watchdog, a watchdog reset is immediately executed whatever the value of the watchdog counter. To avoid any unexpected watchdog reset when re-enabling the watchdog, the following sequence has to be performed: 1. Write 0x in the WDT_MR register. 2. Wait for three slow clock cycles. 3. Write the final value in the WDT_MR register. 1.9 ROM Code: Console Terminal UART Baudrate UART baudrate is Baud instead of Baud 1.10 ROM Code: JTAG Access Lock When no bootable program is found on any external Flash memory, the JTAG access remains locked if the chip is not connected to a host computer using a USB connection To re-enable the JTAG access, send any character using the UART console terminal Unique Serial Number The serial number stored in the SFR registers (SFR_SN0 and SFR_SN1) is not correct The serial number (SFR_SN0, SFR_SN1) has only 16 bits set. This serial number cannot be used as a 64-bit unique ID. 4

5 1.12 Fuse Masking The Partial Fuse Masking function does not work The fuse masking function described in the Secure Fuse Controller section of the datasheet does not work. If the ROM code is used in Secure mode, the overall fuses are masked by the ROM code even if some of them are not used Fuse Writing The first two bits of each 32-bit block of the fuse matrix cannot be written The first two bits of each 32-bit block of the fuse matrix cannot be written, so that any word (32 bits) written needs to set to 0 the first two bits of each word (32 bits) of the fuse matrix HSIC Startup At HSIC startup, the strobe default state is wrong The strobe line should be at logic state 0 when HSIC is powered ON, and disabled. Currently, powering up the product sets the strobe line at logic state 1 before the HSIC is enabled. In this case, a connected device tries to connect before the HSIC is enabled. Connect the device after the SAMA5D2 has been started ADC SleepWalking ADC SleepWalking is not functional 1.16 ADC Last Channel Low-speed Trigger The last channel can be triggered at low speed but cannot be programmed by the OUT1 field of the RTC. Only the 1-Hz sampling period is available 1.17 ADC Trigger Events ADC trigger events RTCOUT0 and RTCOUT1 are not functional RTCOUT0 issue leads to ADC Sleepwalking not functional. RTCOUT1 issue makes the last channel specific measurement trigger work at 1 Hz only. 5

6 1.18 ACC Output ACC output connection issue The Analog Comparator (ACC) output is not connected to the PWM event line SDMMC Software 'Reset For all' Command Software 'Reset For all' command is not guaranteed The software 'Reset For all' command is not guaranteed, and some registers of the host controller may not properly reset. The setting of the different registers must be checked before reinitializing the SD card SDMMC Status Flag INTCLKS Status flag INTCLKS may not work correctly When the SDMMC internal clock is disabled (SDMMC_CCR. INTCLKEN= 0) and re-enabled after a few cycles (SDMMC_CCR. INTCLKEN= 1), the status flag INTCLKS may get stuck at 0. A delay loop of 6 cycles minimum of the slowest clock (HCLOCK or BASECLK) must be inserted between SDMMC_CCR. INTCLKEN= 0 and SDMMC_CCR. INTCLKEN= PMC GCLK Fields GCLK fields are re-programmed unexpectedly When configuring a peripheral featuring no GCLK, the GCLK fields (GCKEN, GCKCSS, GCKDIV) of FLEXCOM0 are reconfigured. No other parameter is modified. When accessing a peripheral featuring no GCLK, fill the GCLK fields with the GCLK configuration of FLEXCOM PMC SleepWalking PMC SleepWalking is not functional In Ultra-Low Power mode (ULP1) using simultaneously partial wake-up (SleepWalking) and full wake-up (PIOBU used as wake-up pins or internal events RTC, etc.) may not resume from ULP1.. 6

7 1.23 CLASSD Peripheral Unexpected offset and noise level in Differential Output mode When the CLASSD peripheral is set to Differential Output mode (PWMTYP = 1), a significant output offset and an increased level of noise are observed on the audio outputs. The offset is systematic and is equal to 1/16 of the digital full scale. To avoid the offset, add the opposite offset on the input signal of the CLASSD peripheral FLEXCOM SMBUS FLEXCOM SMBUS alert signalling is not functional The TWI function embedded in the FLEXCOM does not support SMBUS alert signal management. If this signal is mandatory in the application, the user can use one of the standalone TWIs (TWIHS0, TWIHS1) supporting the SMBUS alert signaling TWIHS Clear Command The TWIHS Clear command does not work Bus reset using the CLEAR bit of the TWIHS control register does not work correctly during a bus busy state. Reconfigure the SCL line in GPIO output and generate by software 9 clock pulses to unlock the I2C device. Once done, the SCL line can be reconfigured as a peripheral line MPDDRC t FAW t FAW timing violation DDR2/LPDDR2 memory devices with 8 banks have an additional requirement for t FAW : no more than four Activate commands must be issued in any given t FAW period. Increase the value of t RRD to 3 to avoid the issue Audio PLL Audio PLL output frequency range The frequency range of the AUDIOCORECLK signal (AUDIOPLL output) provided in the SAMA5D2 Series datasheet ( PLL AUDIO Characteristics table, f CORE parameter) does not comply with the applicable specification. The AUDIOCORECLK signal can be operated from 720 MHz to 790 MHz if the following restricted operating conditions are met: Junction temperature (T j ) range: 0 C to +40 C VDDCORE/VDDPLL supply range: 1.20V to 1.32V Bits <29:28> in register PMC_AUDIO_PLL0 are set to (01) 2 7

8 1.28 SSC TD Output Unexpected delay on TD output When SSC is configured with the following conditions: RCMR.START = Start on falling edge/start on Rising edge/start on any edge, RFMR.FSOS = (input), TCMR.START = Receive Start, an unexpected delay of 2 or 3 system clock cycles is added to the TD output I2SC First Sent Data I2SC first sent data corrupted Right after I2SC reset, the first data sent by I2SC controller on the I2SDO line is corrupted. The following data are not affected Quad I/O Serial Peripheral Interface (QSPI) QSPI hangs with long DLYCS QSPI hangs if a command is written to any QSPI register during the DLYCS delay. There is no status bit to flag the end of the delay. The field DLYCS defines a minimum period for which Chip Select is de-asserted, required by some memories. This delay is generally < 60 ns and comprises internal execution time, arbitration and latencies. Thus, DLYCS must be configured to be slightly higher than the value specified for the slave device. The software must wait for this same period of time plus an additional delay before a command can be written to the QSPI Master/Processor Clock Prescaler Change of the field PMC_MCKR.PRES is not allowed if Master/Processor Clock Prescaler frequency is too high PMC_MCKR.PRES cannot be changed if the clock applied to the Master/Processor Clock Prescaler (see Master Clock Controller, in section Power Management Controller (PMC) of the datasheet) is greater than 312 MHz (VDDCORE[1.1, 1.32]) and 394 MHz (VDDCORE[1.2, 1.32]). 1. Set PMC_MCKR.CSS to MAIN_CLK. 2. Set PMC_MCKR.PRES to the required value. 3. Change PMC_MCKR.CSS to the new clock source (PLLA_CLK, UPLLCK). 8

9 2. Revision History In the table that follows, the most recent version of the document appears first. Table 2-1. SAMA5D2 Errata Revision History Doc. Rev. Date Changes Updated: - Section 1.7 ROM Code: Main External Clock Frequency Support for SAM-BA Monitor - Section 1.8 ROM Code: Watchdog after SAM-BA Monitor Connection 44056D 07-Jan-16 Added: - Section 1.27 Audio PLL - Section 1.28 SSC TD Output - Section 1.29 I2SC First Sent Data - Section 1.30 Quad I/O Serial Peripheral Interface (QSPI) - Section 1.31 Master/Processor Clock Prescaler Section 1.21 PMC GCLK Fields : replaced GCK with GCLK 44056C 13-Nov-15 Added: - Section 1.17 ADC Trigger Events, - Section 1.18 ACC Output - Section 1.20 SDMMC Status Flag INTCLKS - Section 1.22 PMC SleepWalking - Section 1.24 FLEXCOM SMBUS - Section 1.25 TWIHS Clear Command - Section 1.26 MPDDRC tfaw 44056B 06-Oct-15 Added Section 1.23 CLASSD Peripheral A 07-Sep-15 First issue 9

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