AN11008 Flash based non-volatile storage
|
|
|
- Esther Brenda Sanders
- 9 years ago
- Views:
Transcription
1 Rev. 1 5 January 2011 Application note Document information Info Content Keywords Flash, EEPROM, Non-Volatile Storage Abstract This application note describes the implementation and use of a library that allows on-chip flash memory to be used for non-volatile storage, in a similar manner to EEPROM.
2 Revision history Rev Date Description Initial version. Contact information For more information, please visit: For sales office addresses, please send an to: [email protected] All information provided in this document is subject to legal disclaimers. NXP B.V All rights reserved. Application note Rev. 1 5 January of 12
3 1. Introduction The NXP LPC1100, LPC1300, LPC1700 and LPC2000 family of ARM7 and ARM Cortex microcontrollers provide on-chip flash memory for storage of firmware. A frequent requirement for embedded systems is the storage of variables whose values need to persist through resets of the system. For microcontrollers without on-chip EEPROM there are two basic options. One is to attach an external EEPROM device, perhaps using I 2 C or SPI. The second is to use the on-chip flash memory for variable storage. Attaching an external device requires additional integration work as well as increasing hardware production costs and board space. Using flash memory is problematic as flash memory is not arranged in an optimal way for storage of small pieces of changing data. There are three key issues with using flash memory for storage of variables: Erasing memory is on a per-sector basis Flash memory lifespan Reprogramming locations This application note describes a simple solution to the problem of using flash memory for variable storage, which takes into account erasing flash memory in a way that avoids data loss and minimizes the effect of flash memory lifespan. 2. Storing variables in flash memory When a flash memory location is erased its value becomes 0xFF. Each bit can then be programmed to logic 0 but it cannot be returned to logic 1 without erasing the entire sector. Subject to some limitations this allows multiple writes to a single flash sector to add data to it, without needing to erase the entire sector each time. Each location in flash has a finite lifespan, rated in terms of the number of programming and erase cycles. For the Microcontrollers covered by this application note it is a minimum of 10,000 programming and erase cycles. To continually erase a sector and program the same location each time a variable changed would result in continual use of the same location until the point of failure, while leaving thousands of other locations in the same sector unused. The solution presented in this application note is to make use of all the locations in a single sector until it is full, then reorganize the memory usage so the process can start again. 2.1 Basic mechanism Initially flash sector A is empty (i.e., erased). When a variable needs to be stored a variable record is programmed into sector A. Later when the variable needs to be updated a new record is programmed into sector A and the old record is ignored. Eventually sector A will become full, mostly with old records that are no longer used. On the next variable write when there isn't space in sector A, a second sector, sector B is employed. All the current records in sector A are copied to sector B and sector A is then erased. When a variable needs to be updated, the update goes into sector B, which is the sector currently in use. Once sector B has been filled the current records are copied to sector A and the process repeats. All information provided in this document is subject to legal disclaimers. NXP B.V All rights reserved. Application note Rev. 1 5 January of 12
4 By swapping between two sectors of the same size it can be ensured that current variable values are always stored somewhere in flash memory while erasing takes place. This helps to ensure that if a reset or power failure occurs; the risk of data loss is minimized. 019aab322 Fig 1. Basic mechanism 2.2 Variable records The following table describes the structure of a variable record. Table 1. Variable record structure Field Size in Bytes Description Flags 1 0xFF = no entry, 0xAA = valid data ID 2 A unique identifier for the variable Data N The data stored in native-endianess, maximum of 12 bytes Padding 12 N Always set to 0x00 Checksum 1 A 2's compliment checksum of the ID, data and padding Each record is always a multiple of 16 bytes due to a system called Error Correction Code (ECC) which can be found on some NXP microcontrollers. ECC allows one write per 16 consecutive bytes of flash memory. If needed the record size could be increased, which would allow larger variables to be used at the expense of the number of variables that can be stored, however it must always be a multiple of 16 bytes. It is also possible to store more complex data types, such as structures, in a variable record. All information provided in this document is subject to legal disclaimers. NXP B.V All rights reserved. Application note Rev. 1 5 January of 12
5 The flags field indicates the status of the record. Erased memory has the effect of setting the flags to 0xFF which indicates no entry. This field takes advantage of the fact that it is possible to continually reprogram a location in flash memory without erasing, providing that each successive write only changes bits from logic 1 to logic 0. Therefore the lifecycle of a record is: no entry to valid data. Because multiple variables are supported, it must be possible to identify the variable that a record contains. Therefore a unique identifier is used. For example if a variable called Counter is used, the ID might be defined using the C preprocessor: 1 #define COUNTERID 1 The same identifier must be used for a specific variable throughout the operation of the firmware. The checksum is calculated by adding together the ID, data and padding using an eight byte variable, then subtracting from 0x Sector organization The start of both sectors used contains a single 48 byte sector record: Table 2. Sector record Field Size in Bytes Description Flags 1 1 0xFF = sector empty, 0xAA = sector not empty Padding 15 Reserved. Always set to 0x00 Flags 2 1 0xFF = sector empty or initializing, 0xAA = sector valid or invalid Padding 15 Reserved. Always set to 0x00 Flags 3 1 0xFF = sector empty, initializing or valid, 0xAA = sector invalid Padding 15 Reserved. Always set to 0x00 The three flags fields indicate the status of the sector. An erased sector will have the effect of setting all the flags to 0xFF, which indicates the sector is empty. These fields take advantage of the fact that it is possible to continually reprogram a location in flash memory without erasing, providing that each successive write only changes bits from logic 1 to logic 0. The lifecycle of a sector is: empty to initializing to valid to invalid. The flags are spaced 16 bytes apart. This is due to the ECC functionality previously mentioned, that is featured on some microcontrollers. By spacing the flags apart, any update to the flags results in a single write per 16 consecutive bytes. The initializing state for a sector indicates that the sector is in the process of being filled with current variable records from the old sector. Once the copying has finished the sector will be marked as valid. When the sector has been filled and the current variable records have been copied to the new sector, it will be marked as invalid. In the following diagram the flags for a sector have been grouped into 24-bit values with Flags 1 occupying the most significant byte, and Flags 3 the least significant byte. All information provided in this document is subject to legal disclaimers. NXP B.V All rights reserved. Application note Rev. 1 5 January of 12
6 019aab323 Fig 2. Sector flags 2.4 Data access To find the current value of a variable it is necessary to search through the current flash sector to find the last written valid record for the variable. If the value of the variable has changed then there will be several old records for the variable, which will need to be skipped. In the worst case the sector will be almost full and the variable record will be located at the end of the sector. To speed up variable access a RAM-based lookup table is used. Every time a variable record is written an offset into the flash sector is stored in a table along with the variable's ID. To read the value of a variable the lookup table is consulted and then a direct access to the variable record is made. Similarly the next free location in the current sector is also stored in RAM, increasing the speed at which new variable records can be written. Each entry in the RAM-based lookup table occupies eight bytes. As supplied the library supports a maximum of 100 variables (see #define MAX_VARIABLES), resulting in a All information provided in this document is subject to legal disclaimers. NXP B.V All rights reserved. Application note Rev. 1 5 January of 12
7 lookup table size of 800 bytes. If RAM usage is critical the RAM-based lookup table could be easily removed at the expense of slower non-volatile variable access. 2.5 Recovery after reset The most important aspect of storing variables in flash memory is the ability to retain values even if the microcontroller is reset or power is interrupted. Even if power is interrupted while variables are being copied from one sector to another the system must be able to recover without data loss. There is protection for this on two levels variables level and sector level Variable protection When the value for a new variable is stored in flash, the variable record has a flags field and a checksum field that ensure only complete and correctly written variable records are used. When reading the current value of a variable the flags must be set to 0xAA and the checksum must be correct. After writing the variable record flash memory is read back to compare the contents and make sure the write was successful. If the write failed for some reason then the application layer is informed. If the microcontroller is reset during the write of a variable record then after the next reset when the RAM-based lookup table is reconstructed, partially written or invalid records will be ignored. This will have the effect of using the last successfully written value for the variable Sector protection During the switch between sectors the microcontroller could be interrupted at any point. After the following reset the microcontroller needs to continue where it left off switching sectors. To achieve this, a decision table is used. The flags of both sectors are examined to determine the current state of the system and what to do next. This takes place automatically during initialization. Note that not all states are possible during normal operation, however there has to be an action for every combination of sector flags. In Table 3, the flags for a sector have been grouped into 24-bit values with Flags 1 occupying the most significant byte, and Flags 3 the least significant byte. Table 3. Sector decision table Sector A Flags Sector B Flags Action Invalid X (don't care) Erase sector A X (don't care) Invalid Erase sector B 0xFFFFFF 0xFFFFFF Mark sector A as valid (flags = 0xAAAAFF) 0xFFFFFF 0xAAFFFF Mark sector B as valid (flags = 0xAAAAFF) 0xFFFFFF 0xAAAAFF No action 0xFFFFFF 0xAAAAAA Treat sector B as full and swap to sector A 0xAAFFFF 0xFFFFFF Mark sector A as valid (flags = 0xAAAAFF) 0xAAFFFF 0xAAFFFF Erase sector B. Mark sector A as valid (flags = 0xAAAAFF) All information provided in this document is subject to legal disclaimers. NXP B.V All rights reserved. Application note Rev. 1 5 January of 12
8 Sector A Flags Sector B Flags Action 0xAAFFFF 0xAAAAFF Erase sector A. Treat sector B as full and swap to sector A 0xAAFFFF 0xAAAAAA Mark sector A as valid (flags = 0xAAAAFF). Erase sector B 0xAAAAFF 0xFFFFFF No action 0xAAAAFF 0xAAFFFF Erase sector B. Treat sector A as full and swap to sector B 0xAAAAFF 0xAAAAFF Erase sector B 0xAAAAFF 0xAAAAAA Erase sector B 0xAAAAAA 0xFFFFFF Treat sector A as full and swap to sector B 0xAAAAAA 0xAAFFFF Mark sector B as valid (flags = 0xAAAAFF). Erase sector A 0xAAAAAA 0xAAAAFF Erase sector A 0xAAAAAA 0xAAAAAA Erase sectors A and B. Mark sector A as valid (flags = 0xAAAAFF) Code Read Protection All ARM-based microcontrollers from NXP feature Code Read Protection (CRP), which is a method of securing the device by programming special values into a predefined memory location. The flash-based system described in this application note can function when the CRP is disabled or when it is set to CRP level one. However it will not function if the CRP is set to level two or three. 3. Application Programmer Interface This section describes the interface to the library implementing the system of storing variables in flash memory. 3.1 Functions NVOL_Init Initializes the non-volatile library. This function must be called before any other functions. Returns TRUE for success and FALSE for an error. An error can occur if the flash memory cannot be placed into a known state NVOL_SetVariable Stores a value for a variable in flash memory. Passed is an ID unique to that variable along with a pointer to the variable and the size of the variable in bytes. This generic prototype allows for variables of any size and type to be stored. Returns TRUE for success and FALSE for an error NVOL_GetVariable Gets the value of a variable previously stored in flash memory. Passed is an ID unique to that variable along with a location for the value to be stored and the size of the variable. This generic prototype allows for variables of any size and type to be read. Returns TRUE for success and FALSE for an error. All information provided in this document is subject to legal disclaimers. NXP B.V All rights reserved. Application note Rev. 1 5 January of 12
9 4. Limitations 3.2 Configuration Configuration options are set using the #define statements in flash_nvol.c Sector descriptions The sector start addresses, numbers and sizes are set using SECTOR1_STARTADDR, SECTOR2_STARTADDR, SECTOR1_NUM, SECTOR2_NUM and SECTOR_SIZE. The sector number must match the numbering scheme given in the flash memory section of the NXP User Manual for the device CPU clock The frequency of the CPU clock in khz is set using CPU_CLK. This is needed by the IAP routines for timing Interrupts Different compilers use different non-standard ways of enabling and disabling interrupts. The macros ENABLEIRQ and DISABLEIRQ must be set to the appropriate statements or function calls for the compiler you are using IAP access point The value of IAP_LOCATION must be set to the memory location for IAP routines. This address can be found in the NXP User Manual of the device Number of variables and size The maximum size of a variable in bytes is set using MAX_VARIABLE_SIZE. This must always be a multiple of 16 minus four (e.g., 12, 28, 44). A larger size results in less efficient usage of flash memory. The maximum number of variables is set using MAX_VARIABLES. This has to be small enough to ensure that all variables can fit into a single flash sector. Note that 48 bytes are always allocated at the start of each sector for sector management. Also four bytes are needed per variable record. The smaller this number is, the less RAM is needed for the lookup table. There are two key limitations with the system. Firstly the flash lifespan limits the number of times that a variable can be written. Secondly there will be a delay in writing variables to flash memory. 4.1 Flash lifespan The flash memory in the microcontrollers covered by this application note is rated at a minimum of 10,000 program and erase cycles. If there is a single 12-byte variable and the flash sectors are 4096 bytes in size, then the variable can be written ( ) / 12 = 340 times before the sector is full. At that point the variable will move to the other sector where it can be written an additional 340 times. The result is that the variable can be written 680 times for a single erase in each sector. The lifespan is therefore a minimum of 10,000 x 680 = 6.8 million variable writes. Now consider the worst case for sectors 4096 bytes in size. It would be 340 variables of 12-bytes in size. Every write of a value would cause the flash sectors to be swapped, All information provided in this document is subject to legal disclaimers. NXP B.V All rights reserved. Application note Rev. 1 5 January of 12
10 resulting in one erase cycle of a specific sector every two variable writes. The lifespan would therefore be a minimum of 20,000 variable writes. Note that the library only writes a variable if the value has changed. Consecutive writes with the same value will have no effect. 4.2 Write delays Each time a new value for a variable is written it has to be programmed into flash memory. The speed of this operation is limited by the flash programming and erase speed. The worst case write time for a single variable when the current sector is not full is approximately 1.05ms. If the sector is full then the write will cause a swap of the two sectors used in the system. The worst case time for the entire operation will be approximately 105ms ms per variable ms for the current variable. For example if there are 20 variables then the approximate worst case time will be (1.05 x 20) = ms. A possible optimization that could be implemented is to add a function that allows the application layer to determine how close the current sector is to being full and then manually perform a swap of the sectors. This would avoid unexpectedly long write delays at undesirable moments by ensuring that the sector swapping always takes place during idle periods. 4.3 IAP RAM usage Calls to erase and program the flash memory using IAP require RAM. The location and amount of RAM used is defined in the NXP User Manual for the device, but is typically 32 bytes at the top of the RAM space and a maximum of 128 bytes on the user stack. All information provided in this document is subject to legal disclaimers. NXP B.V All rights reserved. Application note Rev. 1 5 January of 12
11 5. Legal information 5.1 Definitions Draft The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. 5.2 Disclaimers Limited warranty and liability Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer s own risk. Applications Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer s applications and products planned, as well as for the planned application and use of customer s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer s applications or products, or the application or use by customer s third party customer(s). Customer is responsible for doing all necessary testing for the customer s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer s third party customer(s). NXP does not accept any liability in this respect. Export control This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. Evaluation products This product is provided on an as is and with all faults basis for evaluation purposes only. NXP Semiconductors, its affiliates and their suppliers expressly disclaim all warranties, whether express, implied or statutory, including but not limited to the implied warranties of noninfringement, merchantability and fitness for a particular purpose. The entire risk as to the quality, or arising out of the use or performance, of this product remains with customer. In no event shall NXP Semiconductors, its affiliates or their suppliers be liable to customer for any special, indirect, consequential, punitive or incidental damages (including without limitation damages for loss of business, business interruption, loss of use, loss of data or information, and the like) arising out the use of or inability to use the product, whether or not based on tort (including negligence), strict liability, breach of contract, breach of warranty or any other theory, even if advised of the possibility of such damages. Notwithstanding any damages that customer might incur for any reason whatsoever (including without limitation, all damages referenced above and all direct or general damages), the entire liability of NXP Semiconductors, its affiliates and their suppliers and customer s exclusive remedy for all of the foregoing shall be limited to actual damages incurred by customer based on reasonable reliance up to the greater of the amount actually paid by customer for the product or five dollars (US$5.00). The foregoing limitations, exclusions and disclaimers shall apply to the maximum extent permitted by applicable law, even if any remedy fails of its essential purpose. 5.3 Trademarks Notice: All referenced brands, product names, service names and trademarks are property of their respective owners. All information provided in this document is subject to legal disclaimers. NXP B.V All rights reserved. Application note Rev. 1 5 January of 12
12 6. Contents 1. Introduction Storing variables in flash memory Basic mechanism Variable records Sector organization Data access Recovery after reset Variable protection Sector protection Code Read Protection Application Programmer Interface Functions NVOL_Init NVOL_SetVariable NVOL_GetVariable Configuration Sector descriptions CPU clock Interrupts IAP access point Number of variables and size Limitations Flash lifespan Write delays IAP RAM usage Legal information Definitions Disclaimers Trademarks Contents...12 Please be aware that important notices concerning this document and the product(s) described herein, have been included in the section 'Legal information'. NXP B.V All rights reserved. For more information, please visit: For sales office addresses, please send an to: Date of release: 5 January 2011 Document identifier:
AN11239. Boot mode jumper settings for LPC1800 and LPC4300. Document information
Rev. 1 1 July 2012 Application note Document information Info Keywords Abstract Content Hitex Rev A4, NGX Xplorer, Keil, element14, LPC1830, LPC1850, LPC4330, LPC4350, MCB1800, MCB4300 This application
AN11241. AES encryption and decryption software on LPC microcontrollers. Document information
AES encryption and decryption software on LPC microcontrollers Rev. 1 25 July 2012 Application note Document information Info Content Keywords AES, encryption, decryption, FIPS-197, Cortex-M0, Cortex-M3
Using the RS232 serial evaluation boards on a USB port
Document information Info Content Keywords Serial evaluation Board, PN512,PN532, MFRC663, MFRC522, MFRC523, MFRC52x, MFRD522, MFRD523, MFRD52x MIFARE Contactless Smart Card Reader Reference Design, MIFARE
AN10866 LPC1700 secondary USB bootloader
Rev. 2 21 September 2010 Application note Document information Info Content Keywords LPC1700, Secondary USB Bootloader, ISP, IAP Abstract This application note describes how to add a custom secondary USB
UM10764. Vertical Alignment (VA) displays and NXP LCD drivers
Rev. 1 11 November 2013 User manual Document information Info Keywords Abstract Content Vertical Alignment, Twisted Nematic, LCD, PCA85232U, PCA85233UG, PCA8576FUG, PCF21219DUGR, PCA85262ATT, PCA85276ATT
AN1991. Audio decibel level detector with meter driver
Rev. 2.1 20 March 2015 Application note Document information Info Keywords Abstract Content SA604A, LM358, RSSI, cellular radio The SA604A can provide a logarithmic response proportional to the input signal
ES_LPC4357/53/37/33. Errata sheet LPC4357/53/37/33. Document information
Rev. 1.1 8 August 2012 Errata sheet Document information Info Keywords Abstract Content LPC4357FET256; LPC4357FET180; LPC4357FBD208; LPC4353FET256; LPC4353FET180; LPC4353FBD208; LPC4337FET256; LPC4337FET180;
AN10950. LPC24XX external memory bus example. Document information
Rev. 1.1 9 November 2012 Application note Document information Info Content Keywords LPC24XX, EMC, memory, SDRAM, SRAM, flash Abstract This application note will detail an example design illustrating how
AN11357. BGU8009 Matching Options for 850 MHz / 2400 MHz Jammer Immunity. Document information. Keywords
BGU89 Matching Options for 85 MHz / 24 MHz Jammer Immunity Rev. 1 27 May 213 Application Note Document information Info Content Keywords LNA, GNSS, GPS, BGU89, WLAN, GSM-85, GSM-9 Abstract This document
AN11160. Designing RC snubbers
AN60 Rev. 25 April 202 Application note Document information Info Keywords Abstract Content RC snubber, commutation, reverse recovery, leakage inductance, parasitic capacitance, RLC circuit and damping,
AN11007. Single stage 5-6 GHz WLAN LNA with BFU730F. document information
Single stage 5-6 GHz WLAN LNA with BFU730F Rev. 2 20 November 2012 Application note document information Info Content Keywords BFU730F, LNA, 802.11a & 802.11n MIMO WLAN Abstract The document provides circuit,
Mounting instructions for SOT78 (TO-220AB); SOT186A (TO-220F)
Mounting instructions for SOT78 (TO-220AB); SOT186A (TO-220F) Rev. 1 29 May 2012 Application note Document information Info Keywords Abstract Content SOT78; SOT186A; TO-220AB; TO-220F This application
PN7120 Windows IoT Porting Guidelines. Rev. 1.0 13 October 2015 349610
Rev. 1.0 13 October 2015 Application note Document information Info Content Keywords Windows, Internet of Things, NFC, NXP, NCI Abstract This notes describes how to add support for PN7120 to a Windows
Planar PIN diode in a SOD323 very small plastic SMD package.
Rev. 8 12 May 2015 Product data sheet 1. Product profile 1.1 General description Planar PIN diode in a SOD323 very small plastic SMD package. 1.2 Features and benefits High voltage, current controlled
Schottky barrier quadruple diode
Rev. 3 8 October 2012 Product data sheet 1. Product profile 1.1 General description with an integrated guard ring for stress protection. Two electrically isolated dual Schottky barrier diodes series, encapsulated
HEF4011B. 1. General description. 2. Features and benefits. 3. Ordering information. 4. Functional diagram. Quad 2-input NAND gate
Rev. 6 10 December 2015 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The is a quad 2-input NAND gate. The outputs are fully buffered for the highest noise
HEF4021B. 1. General description. 2. Features and benefits. 3. Ordering information. 8-bit static shift register
Rev. 10 21 March 2016 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The is an (parallel-to-serial converter) with a synchronous serial data input (DS), a clock
AN10850. LPC1700 timer triggered memory to GPIO data transfer. Document information. LPC1700, GPIO, DMA, Timer0, Sleep Mode
LPC1700 timer triggered memory to GPIO data transfer Rev. 01 16 July 2009 Application note Document information Info Keywords Abstract Content LPC1700, GPIO, DMA, Timer0, Sleep Mode This application note
AN10860_1. Contact information. NXP Semiconductors. LPC313x NAND flash data and bad block management
Rev. 01 11 August 2009 Application note Document information Info Keywords Abstract Content LPC3130 LPC3131 LPC313x LPC313X LPC3153 LPC3154 LPC3141 LPC3142 LPC31XX LPC31xx Linux kernel Apex boot loader
1-of-4 decoder/demultiplexer
Rev. 6 1 April 2016 Product data sheet 1. General description 2. Features and benefits 3. Applications The contains two 1-of-4 decoders/demultiplexers. Each has two address inputs (na0 and na1, an active
10 ma LED driver in SOT457
SOT457 in SOT457 Rev. 1 20 February 2014 Product data sheet 1. Product profile 1.1 General description LED driver consisting of resistor-equipped PNP transistor with two diodes on one chip in an SOT457
Quad 2-input NAND Schmitt trigger
Rev. 9 15 December 2015 Product data sheet 1. General description 2. Features and benefits 3. Applications The is a quad two-input NAND gate. Each input has a Schmitt trigger circuit. The gate switches
NPN wideband transistor in a SOT89 plastic package.
SOT89 Rev. 05 21 March 2013 Product data sheet 1. Product profile 1.1 General description in a SOT89 plastic package. 1.2 Features and benefits High gain Gold metallization ensures excellent reliability
Low forward voltage High breakdown voltage Guard-ring protected Hermetically sealed glass SMD package
Rev. 6 10 September 2010 Product data sheet 1. Product profile 1.1 General description Planar with an integrated guard ring for stress protection, encapsulated in a small hermetically sealed glass SOD80C
Passivated, sensitive gate triacs in a SOT54 plastic package. General purpose switching and phase control
TO-92 Rev. 9 9 November 2 Product data sheet. Product profile. General description Passivated, sensitive gate triacs in a SOT54 plastic package.2 Features and benefits Designed to be interfaced directly
3-to-8 line decoder, demultiplexer with address latches
Rev. 7 29 January 2016 Product data sheet 1. General description The is a high-speed Si-gate CMOS device and is pin compatible with low-power Schottky TTL (LSTTL). The is specified in compliance with JEDEC
BAT54 series SOT23 Schottky barrier diodes Rev. 5 5 October 2012 Product data sheet 1. Product profile 1.1 General description
SOT2 Rev. 5 5 October 2012 Product data sheet 1. Product profile 1.1 General description Planar with an integrated guard ring for stress protection, encapsulated in a small SOT2 (TO-26AB) Surface-Mounted
14-stage ripple-carry binary counter/divider and oscillator
Rev. 8 25 March 2016 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The is a with three oscillator terminals (RS, REXT and CEXT), ten buffered outputs (Q3 to
HEF4013B. 1. General description. 2. Features and benefits. 3. Applications. 4. Ordering information. Dual D-type flip-flop
Rev. 9 10 December 2015 Product data sheet 1. General description 2. Features and benefits 3. Applications The is a dual D-type flip-flop that features independent set-direct input (SD), clear-direct input
High-speed switching diodes. Type number Package Configuration Package NXP JEITA JEDEC
Rev. 8 18 November 2010 Product data sheet 1. Product profile 1.1 General description, encapsulated in small Surface-Mounted Device (SMD) plastic packages. Table 1. Product overview Type number Package
The 74LVC1G11 provides a single 3-input AND gate.
Rev. 8 17 September 2015 Product data sheet 1. General description The provides a single 3-input AND gate. The input can be driven from either 3.3 V or 5 V devices. This feature allows the use of this
The sensor can be operated at any frequency between DC and 1 MHz.
Rev. 6 18 November 2010 Product data sheet 1. Product profile 1.1 General description The is a sensitive magnetic field sensor, employing the magneto-resistive effect of thin film permalloy. The sensor
74HC377; 74HCT377. 1. General description. 2. Features and benefits. 3. Ordering information
Rev. 4 24 February 2016 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The is an octal positive-edge triggered D-type flip-flop. The device features clock (CP)
AN11122. Water and condensation safe touch sensing with the NXP capacitive touch sensors. Document information
with the NXP capacitive touch sensors Rev. 3 14 March 2014 Application note Document information Info Keywords Abstract Content PCF8883, PCA8885, PCF8885, PCA8886 This application note explains the unique
BAS16 series. 1. Product profile. High-speed switching diodes. 1.1 General description. 1.2 Features and benefits. 1.
Rev. 6 4 September 04 Product data sheet. Product profile. General description, encapsulated in small Surface-Mounted Device (SMD) plastic packages. Table. Product overview Type number Package Configuration
74HC175; 74HCT175. Quad D-type flip-flop with reset; positive-edge trigger
Rev. 5 29 January 2016 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The is a quad positive-edge triggered D-type flip-flop with individual data inputs (Dn)
SiGe:C Low Noise High Linearity Amplifier
Rev. 2 21 February 2012 Product data sheet 1. Product profile 1.1 General description The is a low noise high linearity amplifier for wireless infrastructure applications. The LNA has a high input and
AN10849. LPC1700 RTC hardware auto calibration. Document information. RTC, Hardware Auto Calibration, LPC1700, Graphic LCD
Rev. 01 1 July 2009 Application note Document information Info Keywords Abstract Content RTC, Hardware Auto Calibration, LPC1700, Graphic LCD Using the LPC1700 RTC s auto calibration feature Revision history
DISCRETE SEMICONDUCTORS DATA SHEET. dbook, halfpage M3D088. BB201 Low-voltage variable capacitance double diode. Product specification 2001 Oct 12
DISCRETE SEMICONDUCTORS DATA SHEET dbook, halfpage M3D088 Low-voltage variable capacitance double 2001 Oct 12 Low-voltage variable capacitance double FEATURES Excellent linearity C1: 95 pf; C7.5: 27.6
AN11243. Failure signature of electrical overstress on power MOSFETs. Document information
Rev. 01 29 October 2012 Application note Document information Info Keywords Abstract Content Power MOSFETs, Electrical Overstress (EOS), Unclamped Inductive Switching (UIS) When Power MOSFETs fail, there
Triple single-pole double-throw analog switch
Rev. 12 25 March 2016 Product data sheet 1. General description 2. Features and benefits 3. Applications 4. Ordering information The is a triple single-pole double-throw (SPDT) analog switch, suitable
IP4220CZ6. 1. Product profile. Dual USB 2.0 integrated ESD protection. 1.1 General description. 1.2 Features and benefits. 1.
SOT457 Rev. 5 8 July 2011 Product data sheet 1. Product profile 1.1 General description The is designed to protect I/O lines sensitive to capacitive load, such as USB 2.0, ethernet, Digital Video Interface
74HC02; 74HCT02. 1. General description. 2. Features and benefits. Ordering information. Quad 2-input NOR gate
Rev. 5 26 November 2015 Product data sheet 1. General description 2. Features and benefits The is a quad 2-input NOR gate. Inputs include clamp diodes. This enables the use of current limiting resistors
AN11261. Using RC Thermal Models. Document information
Rev. 2 19 May 2014 Application note Document information Info Keywords Abstract Content RC thermal, SPICE, Models, Z th, R th, MOSFET, Power Analysis of the thermal performance of power semiconductors
45 V, 100 ma NPN general-purpose transistors
Rev. 9 2 September 214 Product data sheet 1. Product profile 1.1 General description NPN general-purpose transistors in Surface-Mounted Device (SMD) plastic packages. Table 1. Product overview Type number
DISCRETE SEMICONDUCTORS DATA SHEET M3D848. CGD923 870 MHz, 20 db gain power doubler amplifier. Product specification 2002 Oct 08
DISCRETE SEMICONDUCTORS DATA SHEET M3D848 2002 Oct 08 FEATURES High output capability Excellent linearity Extremely low noise Excellent return loss properties Rugged construction Gold metallization ensures
8-channel analog multiplexer/demultiplexer
Rev. 12 25 March 2016 Product data sheet 1. General description The is an with three address inputs (S1 to S3), an active LOW enable input (E), eight independent inputs/outputs (Y0 to Y7) and a common
Low-power configurable multiple function gate
Rev. 7 10 September 2014 Product data sheet 1. General description The provides configurable multiple functions. The output state is determined by eight patterns of 3-bit input. The user can choose the
AN10724. TDA8026ET - 5 slots smart card interface. Document information
Rev. 1.0 27 September 2011 Application note Document information Info Content Keywords TDA8026, 5 slots, Smart Card Interface, Banking, EMV, Point-Of-Sale, ISO 7816-3 Abstract This application note describes
8-bit binary counter with output register; 3-state
Rev. 3 24 February 2016 Product data sheet 1. General description The is an 8-bit binary counter with a storage register and 3-state outputs. The storage register has parallel (Q0 to Q7) outputs. The binary
74HC4040; 74HCT4040. 12-stage binary ripple counter
Rev. 5 3 February 2016 Product data sheet 1. General description 2. Features and benefits 3. Applications 4. Ordering information The is a with a clock input (CP), an overriding asynchronous master reset
74HC107; 74HCT107. Dual JK flip-flop with reset; negative-edge trigger
Rev. 5 30 November 2015 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The is a dual negative edge triggered JK flip-flop featuring individual J and K inputs,
AVR106: C Functions for Reading and Writing to Flash Memory. Introduction. Features. AVR 8-bit Microcontrollers APPLICATION NOTE
AVR 8-bit Microcontrollers AVR106: C Functions for Reading and Writing to Flash Memory APPLICATION NOTE Introduction The Atmel AVR devices have a feature called Self programming Program memory. This feature
Ultrafast, epitaxial rectifier diode in a SOD59 (TO-220AC) plastic package
TO-220AC 27 May 2015 Product data sheet 1. General description Ultrafast, epitaxial rectifier diode in a SOD59 (TO-220AC) plastic package 2. Features and benefits Fast switching Low thermal resistance
74HC238; 74HCT238. 3-to-8 line decoder/demultiplexer
Rev. 4 27 January 2016 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The decodes three binary weighted address inputs (A0, A1 and A2) to eight mutually exclusive
74HC2G02; 74HCT2G02. 1. General description. 2. Features and benefits. 3. Ordering information. Dual 2-input NOR gate
Rev. 5 27 September 2013 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The is a dual 2-input NOR gate. Inputs include clamp diodes. This enables the use of
AVR151: Setup and Use of the SPI. Introduction. Features. Atmel AVR 8-bit Microcontroller APPLICATION NOTE
Atmel AVR 8-bit Microcontroller AVR151: Setup and Use of the SPI APPLICATION NOTE Introduction This application note describes how to set up and use the on-chip Serial Peripheral Interface (SPI) of the
74HCU04. 1. General description. 2. Features and benefits. 3. Ordering information. Hex unbuffered inverter
Rev. 7 8 December 2015 Product data sheet 1. General description The is a hex unbuffered inverter. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to
DATA SHEET. BF245A; BF245B; BF245C N-channel silicon field-effect transistors DISCRETE SEMICONDUCTORS
DISCRETE SEMICONDUCTORS DATA SHEET N-channel silicon field-effect transistors Supersedes data of April 995 996 Jul BF5A; BF5B; BF5C FEATURES Interchangeability of drain and source connections Frequencies
LIN-bus ESD protection diode
Rev. 3 31 May 2011 Product data sheet 1. Product profile 1.1 General description in a very small SOD323 (SC-76) Surface-Mounted Device (SMD) plastic package designed to protect one automotive Local Interconnect
74HC393; 74HCT393. Dual 4-bit binary ripple counter
Rev. 6 3 December 2015 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The 74HC393; 7474HCT393 is a dual 4-stage binary ripple counter. Each counter features
74HC154; 74HCT154. 4-to-16 line decoder/demultiplexer
Rev. 7 29 February 2016 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The is a. It decodes four binary weighted address inputs (A0 to A3) to sixteen mutually
APPLICATION NOTE. AT07175: SAM-BA Bootloader for SAM D21. Atmel SAM D21. Introduction. Features
APPLICATION NOTE AT07175: SAM-BA Bootloader for SAM D21 Atmel SAM D21 Introduction Atmel SAM Boot Assistant (Atmel SAM-BA ) allows In-System Programming (ISP) from USB or UART host without any external
How To Write To An Eeprom Memory On A Flash Memory On An Iphone Or Ipro Memory On Microsoft Flash Memory (Eeprom) On A Microsoft Microsoft Powerbook (Ai) 2.2.2
Application note EEPROM emulation in STM32F10x microcontrollers Introduction Many applications require EEPROM (electrically erasable programmable read-only memory) for non-volatile data storage. For low-cost
AN10811 Programming SPI flash on EA3131 boards Rev. 01 1 May 2009 Application note Document information Info Content Keywords Abstract
Rev. 01 1 May 2009 Application note Document information Info Keywords Abstract Content LPC3130, LPC3131, SPI flash Example for programming SPI flash on EA3131 boards. Revision history Rev Date Description
74HC574; 74HCT574. Octal D-type flip-flop; positive edge-trigger; 3-state
Rev. 7 4 March 2016 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The is an 8-bit positive-edge triggered D-type flip-flop with 3-state outputs. The device
How To Add A Usb Secondary Ipo Bootloader To An Lpc23Xx Flash Device To A Flash Device
Rev. 01 16 October 2008 Application note Document information Info Keywords Abstract Content LPC23xx, Secondary ISP Bootloader, Bootloader, USB This application note describes how to add custom USB secondary
74HC165; 74HCT165. 8-bit parallel-in/serial out shift register
Rev. 4 28 December 2015 Product data sheet 1. General description 2. Features and benefits 3. Applications 4. Ordering information The is an 8-bit serial or parallel-in/serial-out shift register. The device
DISCRETE SEMICONDUCTORS DATA SHEET. BT151 series C Thyristors
DISCRETE SEMICONDUCTORS DATA SHEET Product specification April 24 Product specification GENERAL DESCRIPTION QUICK REFERENCE DATA Passivated thyristors in a plastic SYMBOL PARAMETER MAX. MAX. MAX. UNIT
The 74LVC1G04 provides one inverting buffer.
Rev. 12 6 ugust 2012 Product data sheet 1. General description The provides one inverting buffer. Input can be driven from either 3.3 V or 5 V devices. These features allow the use of these devices in
74HC138; 74HCT138. 3-to-8 line decoder/demultiplexer; inverting
Rev. 6 28 December 2015 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The decodes three binary weighted address inputs (A0, A1 and A2) to eight mutually exclusive
Hex buffer with open-drain outputs
Rev. 5 27 October 20 Product data sheet. General description The provides six non-inverting buffers. The outputs are open-drain and can be connected to other open-drain outputs to implement active-low
8-bit synchronous binary down counter
Rev. 5 21 April 2016 Product data sheet 1. General description The is an 8-bit synchronous down counter. It has control inputs for enabling or disabling the clock (CP), for clearing the counter to its
Femtofarad bidirectional ESD protection diode
Rev. 3 24 October 2011 Product data sheet 1. Product profile 1.1 General description Femtofarad bidirectional ElectroStatic Discharge (ESD) protection diode in a leadless ultra small SOD882 Surface-Mounted
74HC74; 74HCT74. 1. General description. 2. Features and benefits. 3. Ordering information
Rev. 5 3 December 2015 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The 74HC74 and 74HCT74 are dual positive edge triggered D-type flip-flop. They have individual
1. GRANT OF LICENSE. Formdocs LLC grants you the following rights provided that you comply with all terms and conditions of this EULA:
END-USER LICENSE AGREEMENT FOR FORMDOCS SOFTWARE IMPORTANT-READ CAREFULLY: This End-User License Agreement ("EULA") is a legal agreement between you (either an individual or a single entity) and Formdocs
AGREEMENT BETWEEN USER AND Caduceon Environmental Laboratories Customer Portal
Terms of Use AGREEMENT BETWEEN USER AND Caduceon Environmental Laboratories Customer Portal The Caduceon Environmental Laboratories Customer Portal Web Site is comprised of various Web pages operated by
HEF4013B. 1. General description. 2. Features and benefits. 3. Applications. 4. Ordering information. Dual D-type flip-flop
Rev. 8 21 November 2011 Product data sheet 1. General description 2. Features and benefits 3. pplications The is a dual -type flip-flop that features independent set-direct input (S), clear-direct input
If you do not wish to agree to these terms, please click DO NOT ACCEPT and obtain a refund of the purchase price as follows:
IMPORTANT: READ THIS AGREEMENT CAREFULLY. THIS IS A LEGAL AGREEMENT BETWEEN AVG TECHNOLOGIES CY, Ltd. ( AVG TECHNOLOGIES ) AND YOU (ACTING AS AN INDIVIDUAL OR, IF APPLICABLE, ON BEHALF OF THE INDIVIDUAL
Partners in Care Welch Allyn Connex Software Development Kit License Agreement
This Software Development Kit End User ( Agreement ) is between Welch Allyn, Inc. ( Welch Allyn ) and the Customer identified in the purchase order ( Customer or You ), and it governs the Software Development
Buffer with open-drain output. The 74LVC1G07 provides the non-inverting buffer.
Rev. 11 29 June 2012 Product data sheet 1. General description The provides the non-inverting buffer. The output of this device is an open drain and can be connected to other open-drain outputs to implement
APPLICATION NOTE. Atmel AVR134: Real Time Clock (RTC) Using the Asynchronous Timer. Atmel AVR 8-bit Microcontroller. Introduction.
APPLICATION NOTE Atmel AVR134: Real Time Clock (RTC) Using the Asynchronous Timer Introduction Atmel AVR 8-bit Microcontroller This application note describes how to implement a real time counter (RTC)
Self Help Guides. Setup Exchange Email with Outlook
Self Help Guides Setup Exchange Email with Outlook Setting up Exchange Email Connection This document is to be used as a guide to setting up an Exchange Email connection with Outlook; 1. Microsoft Outlook
General purpose low power phase control General purpose low power switching Solid-state relay. Symbol Parameter Conditions Min Typ Max Unit V DRM
TO-92 May 25 Product data sheet. General description Planar passivated very sensitive gate four quadrant triac in a SOT54 plastic package intended to be interfaced directly to microcontrollers, logic integrated
AN3969 Application note
Application note EEPROM emulation in STM32F40x/STM32F41x microcontrollers Introduction EEPROMs (Electrically Erasable Programmable Read-Only Memory) are often used in industrial applications to store updateable
BLL6G1214L-250. 1. Product profile. LDMOS L-band radar power transistor. 1.1 General description. 1.2 Features and benefits. 1.
BLL6G1214L-25 Rev. 1 16 February 212 Preliminary data sheet 1. Product profile 1.1 General description 25 W LDMOS power transistor intended for L-band radar applications in the 1.2 GHz to 1.4 GHz range.
BlackBerry Mobile Voice System - BlackBerry MVS Client
BlackBerry Mobile Voice System - BlackBerry MVS Client BlackBerry Device Software 5.0 User Guide Version: 5.2 SWD-1249531-0316085151-001 Contents Basics... 2 About the BlackBerry MVS Client... 2... 3 basics...
AN10441. Level shifting techniques in I 2 C-bus design. Document information
Rev. 01 18 June 2007 Application note Document information Info Keywords Abstract Content I2C-bus, level shifting Logic level shifting may be required when interfacing legacy devices with newer devices
BlackBerry Business Cloud Services. Version: 6.1.7. Release Notes
BlackBerry Business Cloud Services Version: 6.1.7 Release Notes Published: 2015-04-02 SWD-20150402141754388 Contents 1 Related resources...4 2 What's new in BlackBerry Business Cloud Services 6.1.7...
CereVoice Cloud Text To Speech Web Service Terms and Conditions Of Usage Agreement
This ("Agreement") is a legal agreement between you (either as an individual or as single legal entity, referred to in this Agreement as "SERVICE USER") and CereProc Ltd ("CereProc") for the use of the
BZT52H series. Single Zener diodes in a SOD123F package
Rev. 3 7 December 2010 Product data sheet 1. Product profile 1.1 General description General-purpose Zener diodes in a SOD123F small and flat lead Surface-Mounted Device (SMD) plastic package. 1.2 Features
Website Hosting Agreement
Website Hosting Agreement 6 oak grove avenue This Hosting Contract governs your purchase and use, in any manner, of all Web site hosting services, including the Shared Hosting Services, (collectively,
74HC595; 74HCT595. 1. General description. 2. Features and benefits. 3. Applications
8-bit serial-in, serial or parallel-out shift register with output latches; 3-state Rev. 8 25 February 2016 Product data sheet 1. General description The is an 8-bit serial-in/serial or parallel-out shift
USER GUIDE EDBG. Description
USER GUIDE EDBG Description The Atmel Embedded Debugger (EDBG) is an onboard debugger for integration into development kits with Atmel MCUs. In addition to programming and debugging support through Atmel
END-USER LICENSE AGREEMENT FOR DIGIMETRICS AURORA SOFTWARE
END-USER LICENSE AGREEMENT FOR DIGIMETRICS AURORA SOFTWARE IMPORTANT READ CAREFULLY: This End-User License Agreement ("EULA") is a legal agreement between you (either an individual or a single entity)
NPN wideband silicon germanium RF transistor
Rev. 1 29 April 211 Product data sheet 1. Product profile 1.1 General description NPN silicon germanium microwave transistor for high speed, low noise applications in a plastic, 4-pin dual-emitter SOT343F
74HC4067; 74HCT4067. 16-channel analog multiplexer/demultiplexer
Rev. 6 22 May 2015 Product data sheet 1. General description The is a single-pole 16-throw analog switch (SP16T) suitable for use in analog or digital 16:1 multiplexer/demultiplexer applications. The switch
MIFARE ISO/IEC 14443 PICC
Rev. 3.0 26 June 2009 130830 Application note PUBLIC Document information Info Keywords Abstract Content Activate Card, MIFARE, Select Card This Application te shows the elementary communication for selecting
Low-power D-type flip-flop; positive-edge trigger; 3-state
Rev. 8 29 November 2012 Product data sheet 1. General description The provides the single D-type flip-flop with 3-state output. The flip-flop will store the state of data input (D) that meet the set-up
