Assessment of Long-term Reliability in Lead-free Assemblies
|
|
|
- Jared Wilkinson
- 9 years ago
- Views:
Transcription
1 Assessment of Long-term Reliability in Lead-free Assemblies Sanka Ganesan, Ji Wu, and Michael Pecht CALCE Electronic Products & Systems Center University of Maryland College Park, MD 20742, USA Ricky Lee and Jeffery Lo Hong Kong University of Science and Technology Yun Fu, Yonghong Li, and Ming Xu Aero Combined Environment Laboratory China Aero-Polytechnology Establishment, Beijing , P.R.China Abstract Abundant data exist on the short-term reliability (i.e. less than 5 years) of lead-free solder joints under single loading conditions. Data on combined loading conditions and long-term reliability is scarce. The lead-free electronics will be deployed in many products that serve markets where long-term (greater than 5 years) is a critical requirement. In many applications, electronics will be subjected to long-term exposure to temperature extremes (high and low), humidity, atmospheric contaminants, and combined thermo-mechanical loading (temperature cycling and vibrations). To assess long-term reliability, an experimental plan includes assessing the interactions among the applications conditions. The interacting influences include the growth of intermetallics at the solder joints due to high temperature exposure, electro-chemical degradation of electronics assemblies due to the exposure to humidity and atmospheric contaminants, formation of tin pest due to extended exposure to low temperature and the effects of combined thermo-mechanical loading conditions on the electronics assemblies. The test vehicle designs incorporate commercial variations in PCB pad finishes, component lead finishes. Three PCBs designs were developed to assess reliability of surface mount assemblies and single sided through-hole assemblies. The PCB materials include FR4, polyimide for SMT assemblies and paper-phenolic type (CEM-1) for through-hole assemblies. 1 Introduction The electronics industry is migrating to lead-free electronics, both to comply with government legislations and to increase market share through product differentiation. Considering that lead-based electronics have been in use for over 40 years, the adoption of leadfree technology represents a dramatic change. The manufacturing of lead-free electronic products involves assembling lead-free components to lead-free printed circuit boards using lead-free solder alloys. Key issues that are being addressed by academia and industry include leadfree solder alloy selection, characterization of lead-free solder alloy properties and behavior under various stress loading conditions, lead-free manufacturing, logistics and intellectual property issues, and lead-free assembly reliability assessment. 2 What We Know? By definition, lead-free soldering assembly involves the use of only lead-free materials. This applies both to printed circuit boards (PCB) soldering materials, namely solder paste or wave solder for surface-mount or throughhole assembly respectively, and finishes used on component terminals and PCB mounting pads. Ganesan and Pecht [1] provide a summary of lead-free solder alloy compositions. At present, tin-rich alloys with some combinations of silver, copper, bismuth, and antimony are the leading lead-free solder candidate materials. Among those, tin-silver-copper (SAC) eutectic alloy, which has a melting point of approximately 217 C, appears to be one of the most promising compositions, based on both current industry trends, and recommendations by CALCE EPSC, the International Tin Research Institute (ITRI), National Electronics Manufacturing Initiative (NEMI), and Japan Electronics and Information Technology Industries Association (JEITA). There are over 300 lead-free patents for the ternary SAC alloy. Patents depend on such factors as solder alloy composition, solder joint or intermetallic compound. Patent and intellectual property issues on lead-free alloys have been discussed in studies conducted at CALCE [2-4]. PCB pad finishes can affect the reliability of solder joint since they may change the final composition of the solder joints due to the dissolution of species from the board finishes and the reaction between the solder alloy and the board finishes. Previous studies showed that Sn- 3.8Ag-0.7Cu alloy should not be soldered onto a PCB pad with hot air solder leveling (HASL) finish. This combination resulted in a weak interface after high temperature aging [14, 15]. Solectron study showed that HASL finish creates a low temperature phase in reaction with Sn-3.5Ag solder in wave soldering which in turn resulted in fillet lifting [1]. PCB pad finish selection also depends on the manufacturability: solderability and ability to create good solder joints after multiple reflows (may be required in complex systems). Based on these considerations, PCB pads with Sn or Ag metallization may offer a robust solution especially in no-clean flux assembly processes. On components, the source of lead (Pb) is usually the Sn-Pb alloy at the terminals. For the peripheral components, Sn-Pb coating is used as lead finish, while for the array /05/$ IEEE 140
2 components, tin-lead-silver (SnPbAg) alloy balls are in use as component terminals. To realize the transition of peripheral components to lead-free, alternative coatings, such as pure tin (Sn), tin-bismuth (Sn-Bi), tin-copper (Sn- Cu) are being developed and implemented. There are also commercially available preplated lead frame components with nickel-palladium-gold (NiPdAu) finish. From the point view of plating manufacturability, tin plating (matte finish) appears to be the leading candidate for lead finishing, followed by Sn-Cu, Sn-Bi, and Ni/Pd/Au. A few Japanese companies are implementing Sn-Bi plating as lead finish material. However, there are possible concerns in the long-term reliability of these components in various application environments. Fine-pitch peripheral lead-free components have reliability concerns such as tin whiskering for pure tin plating, and creep corrosion for nickel-palladium-gold preplated lead frames. For array packaging, tin-silver-copper appears to be the leading metallurgy for component terminals. Solder reliability is a concern in the transition to leadfree electronics. There has been long-term, successful use of tin-lead solders in terms of electronics manufacturing and solder processing. By contrast, lead-free soldering assembly prompts many unanswered questions. The prominent reliability concerns with the use of lead-free solders are solder joint durability, intermetallic growth, electro chemical migration, tin pest and tin whiskers. 2.1 Solder Joint Reliability Over 90% of the previous studies on lead-free solders were undertaken using SnAgCu alloy. Although a variety of electronic packages have been considered, most of them were surface-mount area array devices such as Ball Grid Arrays (BGA), Chip-Scale (CSP), Flip-Chip (FP) Packages, Quad Flat Packages (QFPs). Consequently, there is insufficient number of studies on long-term lead-free solder joint reliability for through-hole components assembled by lead-free wave soldering; especially single sided boards. The thermo-mechanical durability of lead-free solder joints in cyclic temperature conditions has been studied for temperature cycle extremes of 0 and +100 C, -40 and +125 C, or -55 and +125 C, with -40ºC to 125ºC temperature cycle being the most widely employed. The number of cycles to failure under the above testing conditions was typically found to be several thousand cycles. Another aspect is the stress conditions experienced by the solder joints during its operating life. The solder joints in packages like QFPs and PBGAs are subjected to lower stress conditions due to compliance of the solder joints and low thermal mismatch stresses compared to packages like leadless ceramic chip carriers (large thermal mismatch stresses) with non-compliant solder joints. Previous CALCE studies concluded that non-compliant lead-free solder joints as in leadless ceramic chip carriers under performed Sn-Pb joints [5-13]. On the other hand, for plastic QFPs and PBGAs, the reverse is true (lead-free solder joints outperform the Sn-Pb solder joints), which is consistent with the thermo-mechanical durability results reported from several independent studies across the industry and academia. The time to failure under vibration loading conditions was found to be significantly less than under temperature cycling. However, combined loading conditions may be more representative of actual application environments than single loading tests. There are no data on the long-term reliability of lead-free electronics under combined loading conditions such as temperature cycling and vibration conditions. 2.2 Intermetallic compounds The formation of intermetallic compounds (IMC) at solder-pad interface is essential for creating a reliable joint. However, excessive growth of IMC will result in a brittle interface which can lead to solder failures during the operating life of the product. IMCs form due to two factors: wetting reaction of solder alloy with the pad metal on the board during the soldering process; solid state ageing during the storage and operating life of the product. During the wetting reaction, the tin present in the solder chemically reacts with the pad metal to form the IMC. The extent of the IMC formation depends upon the type of pad finish metallurgies like copper (OSP), nickel (ENIG), immersion silver or immersion tin. The copper-tin IMCs form in the case of pad finish that contains copper, immersion tin and immersion silver. In the case of immersion silver, silver-tin IMCs can also form. Tincopper-nickel IMCs form in the case of pads containing nickel. In solid state ageing, the IMCs form due to the diffusion of reacting species through the initially formed IMCs. Intermetallics growth in lead-free solder joints due to high-temperature ageing has been reported. The studies conducted at CALCE EPSC and elsewhere [1, 14-16] showed that intermetallics compounds grow during ageing at high temperature exposure due to solid state diffusion of reacting species. The growth follows the classical square root of time dependence. For example, after 1000 hours of exposure at 150ºC, the SAC solder on copper pad exhibits an intermetallics thickness of about 7 microns. CALCE EPSC study also showed that IMC growth does not follow the square root of time dependence in the case of immersion silver due to the dissolution of silver in the bulk solder [14]. However, the combined effects of intermetallics growth plus vibration have not been investigated. 2.3 Tin whiskering Tin whiskering is one of the key reliability issues associated with lead-free electronics components. Whiskers are elongated single crystals of pure tin that have been reported to grow to more than 10 mm (250 mils) in length (though they are more typically 1 mm or less) and from 0.3 to 10µm in diameter (typically 1-3 µm). Whiskers grow spontaneously without an applied electric field or moisture (unlike dendrites) and independent of atmospheric pressure (they grow in vacuum as well). Whiskers may be straight, kinked, hooked, or forked and some are reported to be hollow. Their outer surfaces are usually striated. Whiskers can grow in non-filament type which is sometimes called lumps or flowers. Whisker growth may begin soon after plating or initiate after years. The unpredictable nature of whisker incubation and subsequent growth is of particular concern to systems requiring long term, reliable operation [1] /05/$ IEEE 141
3 2.4 Tin pest Another issue associated with the use of lead-free tinrich alloys is the formation of tin pest. The allotropic transformation of white (β) tin, which has a body-centered tetragonal structure, to brittle gray (α) tin, which is a diamond cubic crystal, is known as tin pest. This transformation occurs at 13.2 C. Above this temperature, white tin is the stable form. Since the spontaneous formation of α-tin is rare in conventional Sn-Pb solder alloy, and tin pest has generally been ignored. This may not hold in the case of some lead-free solders since the microstructure of lead-free solders typically contains pure tin grains with tin-copper and tin-silver intermetallic compounds dispersed along the grain boundaries. The allotropic transformation from white tin to gray tin is accompanied by a 26% increase in volume. The volumetric strain in a solder joint can potentially have a detrimental effect on its lifetime. More over, the gray tin is also brittle and weak which in turn can result in joint failures, especially in vibration loading conditions. Kariya studied pest formation of pure tin specimen (cast ingots) by aging it at a constant temperature of -18 C for up to two years [18]. 40% of the specimen surface was transformed into grey tin (tin pest) after ageing for 1.5 years, and this percentage increased to approximately 70% after exposure for 1.8 years. The test results indicate that an incubation period is necessary for tin pest formation. No tin pest was observed on the Sn-37Pb specimen. Kariya s studies also provided the time that different alloy additions retard tin pest transformation [19, 20]. He found that the small additions of soluble alloying elements like bismuth and antimony can retard the formation of tin pest. During the life cycle of electronics, tin-rich lead-free solder joints can be subjected to temperature cycling (typically between 55 C to 125 C) and/or prolonged exposure to temperatures below the transformation temperature, thereby subjecting the joints to allotropic transformation. If the ambient temperature of the solder joints is lower than the transformation temperature, the nucleation of the tin pest will be promoted. The nucleation of tin pest will be enhanced at lower ambient temperatures because the undercooling (difference between the service temperature and the transformation temperature) increases. The impact of this phenomenon in solder joints has not been studied. Thus there is a need to understand and quantify the impact of tin pest on the reliability of lead-free solder joints subjected to extended periods of low temperature exposure in field applications. 2.5 Electro-chemical migration The combined effects of moisture, temperature and electrical bias on electro-chemical migration between leadfree solder joints on PCB assemblies have not been considered. The electro-chemical migration is a concern because the boards are subjected to higher lead-free reflow temperature, which may potentially cause higher degradation and higher migration of ions from the interior of the boards to the surface compared to the boards subjected to the standard eutectic tin-lead reflow process. This effect may cause corrosion of PCB metallization. Moreover long-term exposure to electrical bias and humidity may cause migration of species (e.g., Ag) between the lead-free solder joints. This issue may be exacerbated in the situation of fine pitch components assembled with lead-free materials and process. These issues need investigation to ensure long-term reliability requirements. 3 What We Need to Know? All the changes to the bill of materials for electronics assembly in the context of lead-free migration are being driven by high volume consumer, computer, and portable communication industry where the reliability requirements are not very stringent and the product life cycle is less than 5 years. However, the impact of these material changes on long-term or over 20 years of reliability is not understood. Lead-free electronics will be deployed in many products that serve markets where long-term (greater than 5 years) is a critical requirement. In many applications, electronics will be subjected to long-term exposure to temperature extremes (high and low), humidity, atmospheric contaminants, and combined thermomechanical loading (temperature cycling + vibrations). Thus, long-term reliability studies should comprehend the interactions among these applications conditions and the long test times. Thus the objectives of this long-term reliability assessment of lead-free soldered assemblies are to assess and compare the lead-free technology against the lead-based for long-term (10 to 30 years) reliability requirements, and provide recommendations to reduce reliability risks to achieve long-term reliability goal of 10 to 30 years of operating life for lead-free products. The key results expected from this long-term reliability studies include: (1) extent of the growth of intermetallics in the solder joints as a function of commercially available PCB pad finishes and component finishes, (2) assessment of any yet-unknown risks, such as tin pest of high tin solders joints after long-term exposure to low temperature, (3) impact of PCB degradation due to high temperature lead-free soldering in causing corrosion failures and or degradation in insulation resistance between solder interconnects, (4) vibration fatigue life and failure modes of lead-free solder joints with thicker intermetallics, and possibly with tin pest, (5) Failure mechanisms, mode in solder joint failures in the combined temperature cycling + vibration tests, (6) Long-term life of lead-free assembly in comparison with the lead-based. 4 Experimental Approach The effort focuses on utilizing current knowledge, tools and resources to achieve the long-term reliability goal for electronics products. The approach will be as follows: Conduct experiments in accelerated environments to assess the long-term reliability of commercially available lead-free technologies. Perform failure analysis and interpret results. Experiments are designed with the objective of determining the long-term (over 20 years) reliability of lead-free electronics assembly manufactured using production qualified process. The study involves subjecting the test samples to short-term vibrations after long-term storage at high temperature (125ºC) and low temperature (- 55ºC), long-term exposure to high temperature (135ºC), /05/$ IEEE 142
4 high humidity (85%RH) with electrical bias, long-term temperature cycling (~10000 cycles) with temperature excursions between -40ºC to 125ºC, and the combined loading conditions of temperature cycling with random vibrations. The effect of long exposure to high temperature is expected to enhance the growth of intermetallics in the solder joints. Because intermetallic compounds are brittle in nature, they are expected to degrade the solder joint life under vibration stress conditions. Thus this interaction between the intermetallics growth and vibration stress environment will be studied in the proposed experiments. On the other hand, the low temperature exposure is expected to enhance the tin pest formation (due to allotropic transformation in tin) in tin rich lead-free solder joints. The effect of this phenomenon on the solder joint life under vibration stress conditions is unknown at this point of time. The proposed experiments are expected to shed some light on this phenomenon. Long-term exposure of electronics to high temperature high humidity plus electrical bias will enhance the electrochemical processes, which ultimately can lead to corrosion of metallization, reduction in insulation resistance between the solder joints. This mechanism can be aggravated in lead-free assembly because of the higher PCB assembly temperature possibly causing a more degradation (material degradation, contamination migration) compared to lead-based assembly Variations in bill of materials for electronics products Most OEMs build electronics products consisting of several types of commercially available components which include SMT components in QFPs, BGAs, SOICs, leadless carriers, passives, and through-hole technology components. Thus the experiment includes the SMT and through-hole components. The basis for the selection of the components is to create variations in the compliance of the solder joints (example: QFPs vs. leadless ceramic chip carrier) and thermal mismatch stresses (example: plastic BGAs vs. ceramic carrier) on the solder joints. Next consideration involves creating variations in the lead finish of the components. The lead finish variations for QFPs include electroplated matte Sn, Sn-Cu and Sn-Bi. As for BGAs, SnAgCu solder balls are used. With respect to PCB assembly, again industry has converged to the SnAgCu (SAC) paste for reflow soldering of SMT components and SAC or Sn0.7Cu for wave soldering of through-hole components. Thus these materials will be fixed in the experimental builds based on the current process conditions. Thus, test boards will consist of two types: SMT and single sided through-hole technology. Moreover, all the assemblies will be built using production qualified process in order to represent the actual production conditions of the PCB assembly. On the PCB pad finish issue, the objective is to create variations representing the actual manufacturing conditions. Thus, the experimental builds include PCB pad finishes with immersion Ag, immersion Sn, electroless NiP/Au (ENIG) and organic solderability preservative (OSP). The experimental builds also include the PCB assemblies with the current lead-based materials and processes to serve as control. 4.2 Test vehicles SMT and through-hole boards were designed for this study. The SMT test boards are made of two materials: FR4 (the glass transition temperature is ~130ºC) and polyimide (glass transition temperature is ~250ºC). These boards have a daisy chain pattern to enable resistance monitoring of the solder joints of each component. The size of the board is 8 by 7. The board typically has 1 ounce thick copper (~35 microns) pads/traces. The board is mounted with the selected packages with the dummy silicon die. The packages have wire bonds connecting the adjacent leads (not to the die) in order to enable resistance monitoring of the solder joints when assembled on to the test board. In random vibrations test, the vibration stress level will depend upon the position on the board. This aspect needs to be considered in the component placement for PCB layout. The symmetrical layout of the vibration test board is shown in Figure 1. Figure 2 is the SMT board design for temperature cycling tests. These boards incorporate a cutout feature around each component (except resistors) to facilitate component removal during temperature cycling tests to enable failure analysis on each failed component. These PCBs also incorporate a structure to study the electrochemical migration in solder joints. This structure consists of pads with the center to-center spacing of 0.5 mm (20 mils). This spacing represents the current fine pitch pad spacing practiced in the industry. During PCB assembly, the solder paste will be reflowed on these pads to create solder islands. During HAST testing (130ºC/85%RH), the electrical bias will be applied between them to simulate the accelerated electrochemical migration effect between two adjacent solder joints. Figure 3 shows the layout for the single sided throughhole technology test board. This board is made of CEM-1 material and has a size of 8 X 5.5. This board will be used for both vibration and temperature cycling tests. The rationale for the inclusion of this design is to create a representation for electronics assemblies deployed in the systems such as washers and dryers /05/$ IEEE 143
5 Figure 1: SMT test board for vibration stress test Electro-chemical migration test structure Cut-out feature Figure 2: SMT test board for temperature cycling tests with electrochemical degradation test structure for long-term storage tests. Cut-out features are provided to enable easy component removal during the temperature cycling test /05/$ IEEE 144
6 Figure 3: Single sided, through-hole board for vibration and temperature cycling tests 4.3 Testing conditions The fundamental premise in the proposed assessment of long-term reliability of lead-free electronics is to investigate and quantify the interactions between the physical phenomena like intermetallics growth and tin pest and the expected field stress conditions (vibrations, temperature cycling) on the solder joint degradation. The experimental matrix is shown in Table 1. Table 1: Experimental matrix Pre-treatment Accelerated stressing Solder and PCB pad finish Sn-Pb SAC SAC SAC SAC HASL Immersion Ag Immersion Sn ENIG OSP High temp. storage (125ºC/100 hours) Vibration test High temp. storage (125ºC/350 hours) Vibration test Low temp. storage (-55ºC/500 hours) Vibration test Low temp. storage (-55ºC/1000 hours) Vibration test None (Control) Vibration test Not applicable HAST (130ºC / 85%RH / 672 hours) + Bias (for corrosion test structure) None Temp. cycling (-40ºC to 125ºC) None Temp. cycling + vibration The growth of intermetallics at the solder joints can be enhanced by subjecting the electronics assemblies to high temperature storage. The time and temperature conditions for this test are determined based on the acceleration factor that relates the extent of growth in the test to the field conditions. Based on a previous analysis (based on the activation energy for IMC growth of 1.05 ev) [16], it is expected that the test conditions of (125ºC/350 hours) will simulate the growth of intermetallics that will be observed in the field after exposure to 55ºC in 28 years. In the proposed experiments, the growth kinetics of intermetallics /05/$ IEEE 145
7 and their structural morphology will be studied for all the combinations of lead finish-sac-pcb pad finish. The lead-free alloy that will be studied in this proposal is tin rich Sn3Ag0.5Cu alloy. The microstructure of this alloy in the solder joint consists of tin grain matrix with interdispersed Sn-Ag, Sn-Cu intermetallic compounds. Tin pest may occur at low temperatures. To accelerate this phenomenon of tin pest and investigate its impact on long term reliability, the PCB assemblies will be subjected to low temperature (-55ºC) storage of 1000 hours. At this point, we do not know the acceleration factor for this test. Vibration test involves subjecting the test assemblies to resonant frequency of vibration in the vibration chamber. The appropriate power spectral density level for long-term vibration tests will be determined through simulation and step stress experiments. Sensors will be mounted and monitored on the PCB assemblies to measure vibration stress. The resistance of each daisy chain will be monitored continuously using the in-house built test equipment during vibration tests. This equipment will monitor the resistance of each chain in parallel with detection window of ~70 ns. The resistance threshold (a programmable quantity in the system) will be set to 100 ohms. A resistance spike exceeding the threshold will be counted as a failure event when the increased resistance persists for at least 1µs. There is a counter which stores these failure events with the time stamp. This parallel and continuous measurement method is expected to ensure that no failure event (including intermittents) is missed within each vibration period (can range from 2.5 ms to 12.5 ms). A daisy chain in vibration test will be considered as failure when there are consecutive 15 failure events. Time to failure for the daisy chain will correspond to the time at which the failure event occurred. The temperature cycling tests will be conducted in air convection chambers. The temperature of each board will be independently monitored using thermocouples installed at the center of the boards. The temperature profile that will be used in this study is: temperature excursion between -40ºC to 125ºC with 15 minutes dwell time at both high and low temperature extremes and a ramp time of 15 minutes (~10ºC per minute ramp rate) between extremes. The resistance of the daisy chains in temperature cycling will be monitored using commercially available Agilent data loggers. The data logger switching (polling) frequency will be set to 82 chains per minute. All the tests will continue till failure. Failure is defined as one or more resistance excursions greater than 300 ohms occurring in each cycle for 10 consecutive temperature cycles. To define cycles-to-failure, we go back to the first of the ten final thermal cycles that registered the consecutive failure readings. HAST test (135ºC/85%RH with bias for 672 hrs) will also be conducted to investigate any electrochemical migration and corrosion phenomena. This study will use the corrosion test structure that is incorporated on the temperature cycling test board. This structure will enable application of electrical bias and to quantify the electrochemical degradation phenomenon. The experimental builds include the Sn-Pb assemblies as controls to assess and compare the long-term reliability of electronics assemblies in temperature cycling and the combined temperature cycling with random vibrations. 4.4 Analysis methods As assembled PCB samples will be examined under optical microscopy to assess and compare the quality of the solder joints. Specifically, analysis will look for difference in the wetting characteristics, appearance of the joints (dull vs. shiny), fillet shape, any evidence of bridging, solder balling, and any evidence of fillet lifting in through-hole components. Cross-sectioning and microscopy (Optical, SEM/EDX) will be performed on each type of component/pad finish combinations after exposure (up to 1000 hrs.) to high temperature storage test to determine the extent of intermetallic compounds growth, their chemical constituents (EDX), morphology (SEM, TEM) and stochiometry (XPS). Similar analysis will be performed for samples after exposure to low temperature to investigate for the evidence of tin pest in the tin rich solder joints. Because tin pest is associated with crystal structure change and which is more likely to initiate from the surface of the solder joints, ion scattering spectroscopy (ISS) techniques will be used to determine the tin pest phenomenon. Microscopic analysis will also be performed on the solder joints after the temperature/humidity/electrical bias tests to assess the electrochemical degradation. Optical/SEM analysis of the solder joints after vibration, temperature cycling and combined vibration + temperature cycling tests will be performed to determine the failure mode and morphology. The plan also includes characterizing the morphology of the solder joint microstructures, intermetallics, tin pest in solder joints and tin whiskers in lead and PCB plating finish metallurgies under long-term aging (high temperature exposure, low temperature exposure, temperature cycling) using several characterization methods including TEM (transmission electron microscopy), XPS (X-ray photoelectron spectroscopy: to determine the stochiometry of intermetallics compounds) and ISS (ion scattering spectroscopy: to determine the surface crystallographic structures, film thickness, and possibly surface stresses). 5 Printed Circuit Board Assembly The printed circuit board assemblies for this study were assembled in Jabil s San Jose facility. Jabil Circuits Inc. is one of the leading edge electronics manufacturing service (EMS) providers in the world. Jabil offers manufacturing services to world leading electronics companies that include consumer, telecommunication, computing, instrumentation, medical, and automotive industries. Jabil has design, manufacturing and repair centers in every major region of the world. Jabil's manufacturing operations comply with ISO Quality Management System Standards, ISO Environmental Standard, and ISO Health and Safety Standard. The Jabil s San Jose facility supports high and lowmix PCB and backplane assembly for volumes that range from just a few units for prototypes, to modest quantities for pre-production, to hundreds of thousands in volume /05/$ IEEE 146
8 production. The facility s capabilities extend from single sided through-hole to double sided, high density surface mount assemblies with chip scale packages, mixed technology assemblies, lead-free assembly, flip chip, chip on board, and fine pitch high pin count press fit connectors. The SMT process flow is shown in Figure 4. Figure 5 shows the process flow for through-hole assemblies. The assembly involved two surface mount designs (vibration and temperature cycling) and one single sided through-hole design. The surface mount designs, fabricated using two PCB materials FR4 and polyimide were of 2- metal layer construction. The components were mounted on top side of the surface mount boards only. The single sided through-hole design boards were fabricated using CEM-1 material and were assembled using Jabil s selective soldering technology. The total number of assemblies included 306 surface mount designs (vibration design=169, temperature cycling design = 137) and 70 through-hole design. The build sequence started with PbSn assembly for the SMT vibration and temperature cycle designs. This was followed by Pb-free assembly of SMT vibration design boards and temperature cycling design boards. Single sided throughhole boards were assembled last due to scheduling constraints. 5.1 SMT assembly process A no clean-type 3-Kester R905 paste (Sn3Ag0.5Cu) was used for the Pb-free assemblies. For control Sn-Pb assemblies, no-clean-type 3-Kester 256 paste (Sn37Pb) was used. The stencil was sourced from Beam On Technology (a preferred supplier of Jabil-San Jose assembly facility). A laser-cut stencil with 5 mils nominal thickness was used for printing. The quality compliance certificate from the stencil supplier is shown below. A 10-zone Vitronics-Soltec XPM2 convection reflow oven was used for reflow. The reflow gas was nitrogen. The temperature was monitored for PBGAs and resistors. PBGAs were selected due to their sensitivity to popcorning. The PBGA saw a peak temperature of 246ºC. The peak temperature of all the PBGAs was same. The resistors saw a peak temperature of 250ºC. The time duration for the PBGAs in the oven above the melting point of the solder (217ºC) was 78 seconds. The time duration between 150ºC to 217ºC was 73 seconds. The Pb-free reflow temperature profile used for the assembly is shown in Figure 6. For the control Pb-63Sn assemblies, the thermal profile (Figure 7) was used. In this assembly the PBGAs saw the peak temperatures between 213ºC to 215ºC. In this process, resistors saw a higher peak temperature of 219ºC. The time duration above the melting point (183ºC) for this process ranged from seconds. The time duration between 150ºC to 183ºC ranged from 88 to 100 seconds. By comparing two processes, there is a difference of 31ºC in peak temperatures experienced by PBGAs. All the assemblies were subjected to two reflow profiles in order to simulate actual top and bottom assembly process. Figure 8 shows the assembled board after reflow. Bill of Materials Quantity verification Incoming inspection of PCBs (sample basis) PCB serialization Shipping media transfer (for CLCCs) Stencil print paste Component placement (resistors) Component placement (PBGAs, LQFPs, CLCCs) Reflow Automatic X-ray and optical inspection Defects assessment No defectives Flying probe (resistance measurements) Rework Defectives Shipping Figure 4: Process flow for the SMT boards assembly /05/$ IEEE 147
9 Bill of Materials Quantity verification Incoming inspection of PCBs (sample basis) Hand-placement of components (48 PDIPs) Selective soldering technology (Versaflow) Automatic optical inspection Defects assessment Defectives Rework No defectives Flying probe (resistance measurements) Shipping Figure 5: Process flow for single sided through-hole boards assembly Figure 6: Lead-free reflow profile /05/$ IEEE 148
10 Figure 7: Sn-Pb reflow profile 5.2 Inspection A HP 5Dx X-ray tomography system was used to inspect the quality of solder joints in the assemblies. The X-ray images of the solder joints of all the component types are shown in Figures Figure 9 shows the x-ray image of good PBGA solder joints from the assembled boards The 5Dx system was also used to capture the images of all the defective lead-free PBGA solder joints (see Figure 144). Defects in solder joints of the SMT vibration assemblies (FR4 with immersion tin, immersion silver, ENIG, and OSP finishes, polyimide boards with ENIG finish) in non-baked Amkor s 256 Pb-free PBGAs after the lead-free reflow. The solder joint defects were categorized in to three major types: open and or insufficient solder, shorts (bridging) and the combination of shorts with insufficient solder. All the defects occurred under the die Figure 8: Test board after the reflow area of the PBGA. The PBGAs were rated as MSL 3 parts and were out of the moisture proof bags for a maximum of 2 hours before assembly. The defects were hypothesized to be due to the combined effects of popcorn phenomenon occurring in PBGA packages during Pb-free reflow and PBGA-PCB warpage during higher temperature Pb-free reflow. With this hypothesis, it was decided to bake all the PBGAs before lead-free assembly of the rest of the boards in order to eliminate popcorning as one of the potential causes. After baking the PBGAs at 125ºC for 24 hours before reflow, the rest of the SMT lead-free assemblies did not exhibit the defects based on the X-ray inspection results. It can be concluded that the single factor which had the most influence in preventing defects was the baking of Pb-free PBGAs. Further analysis of the failed PBGAs confirmed that moisture induced interfacial delamination and popcorning was the root-cause of the observed solder /05/$ IEEE 149
11 joints defects after lead-free reflow. All the affected assemblies were reworked with assembly house rework process. Figure 9: X-ray image of 256 PBGA solder joints Figure 10: X-ray image of 100 ld LQFP solder joints Figure 11: X-ray image of 44 ld CLCC solder joints /05/$ IEEE 150
12 Figure 12: X-ray image of 2512 SMT resistor Figure 13: X-ray image of 1210 SMT resistor /05/$ IEEE 151
13 Over-sized solder joint Insufficient solder joint Bridged solder joint Figure 14: X-ray image of the first article on lead-free FR4 vibration board 5.3 Single sided through-hole assemblies The assembly steps for single sided through-hole assembly involved hand- placement of s and wave soldering. The wave soldering for this study was accomplished with Jabil s selective soldering technology where in individual solder joints are created with the high precision solder nozzle in ERSA Versaflow equipment (see Figure 15). The selective soldering technology is the preferred method in high mix, low volume assembly facilities. The ERSA VERSAFLOW consists of 3 independently programmable and operating modules: a micro-drop fluxer mounted on an XY-table, a fix-mounted pre-heating module and a solder module positioned on an XYZ-table. To reduce the formation of oxides in the solder bath and to improve the quality of the solder joints, the solder bath is inerted with nitrogen. The temperature profile used for the through-hole assemblies is shown in Figure 16. The Sn3Ag0.5Cu solder alloy (Kester 905) was used for Pbfree assemblies and the standard eutectic Pb63Sn solder alloy (Kester 256) was used for control SnPb assemblies. A no-clean, Lonco65 flux was used during soldering. Figures 17 and 18 show the top side and bottom side of an assembled through-hole board respectively. Figure 15: ERSA Versaflow equipment used for single sided through-hole assemblies /05/$ IEEE 152
14 Figure 16: Temperature profile for single sided through-hole lead-free assemblies Figure 17: Top side of an assembled through-hole board Figure 18: Bottom side of an assembled through-hole board /05/$ IEEE 153
15 6 Summary Abundant data exist on the short-term reliability (i.e. less than 5 years) of lead-free solder joints under single loading conditions. Data on combined loading conditions and long-term reliability is non-existent. The lead-free electronics will be deployed in many products that serve markets where long-term (greater than 5 years) is a critical requirement. In many applications, electronics will be subjected to long-term exposure to temperature extremes (high and low), humidity, atmospheric contaminants, and combined thermo-mechanical loading (temperature cycling + vibrations). Thus, this long-term reliability studies comprehend the interactions among these applications conditions. These interacting influences include unacceptable growth of intermetallics at the solder joints due to high temperature exposure, electro-chemical degradation of electronics assemblies due to the exposure to humidity and atmospheric contaminants, formation of tin pest due to extended exposure to low temperature and the effects of combined thermo-mechanical loading conditions on the electronics assemblies. 7 Acknowledgements CALCE Electronic Products and Systems Center has initiated the long-term lead-free reliability program and is collaborating with Aero combined Environment Laboratory of China Aero-Polytechnology Establishment, Hong Kong University of Science and Technology, Poland Technologic University, and many companies engaged in telecommunication, industrial, aerospace, and oil exploration businesses. 8 References [1] Ganesan, S. and Pecht, M., Lead-free Electronics, 2004 Edition, Edited by, CALCE EPSC Press, University of Maryland, College Park, Maryland [2] Casey, P., S. Ganesan and M. Pecht, Challenges in Adopting Pb-free Interconnects for Green Electronics, Proceedings of the IPC/JEDEC Second International Conference on Lead-free Electronic Components and Assemblies, pp , Taipei, Taiwan, [3] P. Casey and M. Pecht, Assessing Lead-free Intellectual Property, Circuit World, Vol. 30, No. 2, pp , [4] P. Casey and M. Pecht, The Technical, Social and Legal Outlook for Lead-Free Solders, IEEE International Symposium on Electronic Material and Packaging, pp , Kaohsiung, Taiwan, December, 2002 [5] Zhang, Q., A. Dasgupta and P. Haswell, 2003, Viscoplastic Constitutive Properties and Energy- Partitioning Model of Lead-free Sn3.9Ag0.6Cu Solder Alloy, ECTC 2003, New Orleans, Louisiana, USA, 2003 [6] Zhang, Q., A. Dasgupta, P. Haswell and M. Osterman, 2003a, Isothermal Mechanical Fatigue of Lead-free Solders: Damage Propagation and Time to Failure, 34th International SAMPE Technical Conference, Baltimore, MD, 2003 [7] Zhang, Q., Dasgupta, A., and Haswell, P. Creep and High-Temperature Isothermal Fatigue of Pb- Free Solders, Proceedings of IPACK 03: International Electronic Packaging Technical Conference and Exhibition, July 6-11, 2003, Maui, Hawaii, USA, 2003 [8] Zhang, Q., Haswell, P. and Dasgupta, A. Isothermal Mechanical Creep and Fatigue of Pbfree Solders, International Brazing &Soldering Conference, San Diego, CA, February 16-19, 2003 [9] Zhang, Q., Haswell, P., and Dasgupta, A. Cyclic Mechanical Durability of Sn-3.9Ag-0.6Cu and Sn-3.5Ag Lead-Free Solder Alloys, Proceedings ASME IMECE 2002, New Orleans, LA, 2002 [10] Zhang, Q., Haswell, P., Dasgupta, A., and Osterman, M. Isothermal Mechanical Fatigue of Pb-free Solders: Damage Propagation Rate & Time to Failure, 34th International SAMPE Technical Conference, Baltimore, MD, November 4-7, 2002 [11] Haswell, P. and Dasgupta, A., Viscoplastic Constitutive Properties of Lead-free Sn-3.9Ag- 0.6Cu Alloy, MRS Proceedings, San Francisco, CA, 2001 [12] Haswell, P., Durability Assessment and Microstructural Observations of Selected Solder Alloys, Ph.D. Dissertation, University of Maryland, College Park, MD, 2001 [13] Haswell,P. and Dasgupta, A. Microthermomechanical Analysis of Lead-Free Sn3.9Ag0.6Cu Alloys, Part I: Viscoplastic Constitutive Properties, and Part II: Cyclic Durability Properties, Paper N2.1, MRS Proceedings, Vol. 682E, MRS Spring Symposium on Microelectronics and Microsystems Packaging, Editors: Boudreaux, Dauskardt, Last, and McCluskey, Chicago, 2001 [14] Zheng, Y., Hillman, C., and McCluskey, P. Effect of PWB Plating on the Microstructure and Reliability of SnAgCu Solder Joints, presented on AESF SUR/FIN 2002 June 24-27, Chicago, IL, 2002 [15] Zheng, Y., Hillman, C., and McCluskey, P. Intermetallic Growth on PWBs Soldered with Sn3.8Ag0.7Cu, presented on Proceedings of the 52nd Electronic Components & Technology Conference, pp , San Diego, 2002 [16] Lee, T.Y. et al. Morphology, Kinetics, and Thermodynamics of Solid-State Aging of Eutectic Sn-Pb and Pb-free Solders (Sn-3.5Ag, Sn-3.8Ag- 0.7Cu and Sn-0.7Cu) on Cu, Journal of Materials Research, Vol.17, No.2, February 2002, pp [17] Hilty, R. D. Lead Free Components in Automotive Applications, IPC/JEDEC Fourth International Conference on Lead Free Electronic /05/$ IEEE 154
16 Components And Assemblies, Frankfurt, Germany, October 21-22, 2003 [18] Kariya, Y., Gagg, C., Plumbridge, W.J., Tin pest in lead-free solders, Soldering & Surface Mount Technology, vol.13, no.1, p , 2001 [19] Kariya, Y., T. Morihata, E. Hazawa and M. Otsuka, Assessment of Low-Cycle Fatigue Life of Sn-3.5mass%Ag-X (X=Bi or Cu) Alloy by Strain Range Partitioning Approach, Journal of Electronic Materials, Vol. 30, No. 9, pp , 2001 [20] Kariya, Y., Williams, N., Gagg, C., and Plumbridge, W., Tin Pest in Sn-0.5 wt% Cu Lead-Free Solder, Journal of Materials, June 2001, pp.39-41, /05/$ IEEE 155
Effect of PWB Plating on the Microstructure and Reliability of SnAgCu Solder Joints
Effect of PWB Plating on the Microstructure and Reliability of SnAgCu Solder Joints Y. Zheng, C. Hillman, P. McCluskey CALCE Electronic Products and Systems Center A. James Clark School of Engineering
, Yong-Min Kwon 1 ) , Ho-Young Son 1 ) , Jeong-Tak Moon 2 ) Byung-Wook Jeong 2 ) , Kyung-In Kang 2 )
Effect of Sb Addition in Sn-Ag-Cu Solder Balls on the Drop Test Reliability of BGA Packages with Electroless Nickel Immersion Gold (ENIG) Surface Finish Yong-Sung Park 1 ), Yong-Min Kwon 1 ), Ho-Young
Lead Free Wave Soldering
China - Korea - Singapore- Malaysia - USA - Netherlands - Germany WAVE SELECTIVE REFLOW SOLDERING SOLDERING SOLDERING Lead Free Wave Soldering Ursula Marquez October 18, 23 Wave Soldering Roadmap Parameter
Lead Free Reliability Testing
Lead Free Reliability Testing Reliability Implications of Lead-Free Reliability, of what? Solder Joints Laminate Solder Joint Reliability Components SAC vs. SAC main alternative alloy Comparison is desired,
Overview of Risk Assessment, Mitigation, and Management Research for Pb-free Electronics
Overview of Risk Assessment, Mitigation, and Management Research for Pb-free Electronics Formed 1987 Electronic Products and Systems Center College Park, MD 20742 (301) 405-5323 http://www.calce.umd.edu
Technical Note Recommended Soldering Parameters
Technical Note Recommended Soldering Parameters Introduction Introduction The semiconductor industry is moving toward the elimination of Pb from packages in accordance with new international regulations.
Analysis of BGA Solder Joint Reliability for Selected Solder Alloy and Surface Finish Configurations
Analysis of BGA Solder Joint Reliability for Selected Solder Alloy and Surface Finish Configurations Hugh Roberts / Atotech USA Inc Sven Lamprecht and Christian Sebald / Atotech Deutschland GmbH Mark Bachman,
Solutions without Boundaries. PCB Surface Finishes. Todd Henninger, C.I.D. Sr. Field Applications Engineer Midwest Region
Solutions without Boundaries PCB Surface Finishes Todd Henninger, C.I.D. Sr. Field Applications Engineer Midwest Region 1 Notice Notification of Proprietary Information: This document contains proprietary
Customer Service Note Lead Frame Package User Guidelines
Customer Service Note Lead Frame Package User Guidelines CSN30: Lead Frame Package User Guidelines Introduction Introduction When size constraints allow, the larger-pitched lead-frame-based package design
How do you create a RoHS Compliancy-Lead-free Roadmap?
How do you create a RoHS Compliancy-Lead-free Roadmap? When a company begins the transition to lead-free it impacts the whole organization. The cost of transition will vary and depends on the number of
Lead-free Defects in Reflow Soldering
Lead-free Defects in Reflow Soldering Author: Peter Biocca, Senior Development Engineer, Kester, Des Plaines, Illinois. Telephone 972.390.1197; email [email protected] February 15 th, 2005 Lead-free Defects
Molded. By July. A chip scale. and Omega. Guidelines. layer on the silicon chip. of mold. aluminum or. Bottom view. Rev. 1.
Application Note PAC-006 By J. Lu, Y. Ding, S. Liu, J. Gong, C. Yue July 2012 Molded Chip Scale Package Assembly Guidelines Introduction to Molded Chip Scale Package A chip scale package (CSP) has direct
Introduction to the Plastic Ball Grid Array (PBGA)
Introduction to the Plastic Ball Grid Array (PBGA) Q1, 2008 Terry Burnette Dec. 15, 2005 Presentation Outline PBGA Introduction and Package Description PC Board Design for PBGA PBGA Assembly PBGA Solder
Ball Grid Array (BGA) Technology
Chapter E: BGA Ball Grid Array (BGA) Technology The information presented in this chapter has been collected from a number of sources describing BGA activities, both nationally at IVF and reported elsewhere
Flip Chip Package Qualification of RF-IC Packages
Flip Chip Package Qualification of RF-IC Packages Mumtaz Y. Bora Peregrine Semiconductor San Diego, Ca. 92121 [email protected] Abstract Quad Flat Pack No Leads (QFNs) are thermally enhanced plastic packages
Taking the Pain Out of Pb-free Reflow
Taking the Pain Out of Pb-free Reflow Paul N. Houston & Brian J. Lewis Siemens Dematic Electronics Assembly Systems (770) 797-3362 Presented at APEX 2003, Anaheim CA Daniel F. Baldwin Engent, Inc. Norcross,
Lead-free Wave Soldering Some Insight on How to Develop a Process that Works
Lead-free Wave Soldering Some Insight on How to Develop a Process that Works Author: Peter Biocca, Senior Market Development Engineer, Kester, Des Plaines, Illinois. Telephone: 972.390.1197; email [email protected]
First Published in the ECWC 10 Conference at IPC Printed Circuits Expo, Apex and Designer Summit 2005, Anaheim, Calif., Feb.
First Published in the ECWC 10 Conference at IPC Printed Circuits Expo, Apex and Designer Summit 2005, Anaheim, Calif., Feb. 22-24, 2005 Test and Inspection as part of the lead-free manufacturing process
17 IMPLEMENTATION OF LEAD-FREE SOLDERING TECHNOLOGY. Eva Kotrčová České Vysoké Učení Technické Fakulta Elektrotechnická Katedra Elektrotechnologie
17 IMPLEMENTATION OF LEAD-FREE SOLDERING TECHNOLOGY Eva Kotrčová České Vysoké Učení Technické Fakulta Elektrotechnická Katedra Elektrotechnologie 1. Introduction Lead is the toxic heavy metal which is
Choosing a Low-Cost Alternative to SAC Alloys for PCB Assembly
Choosing a Low-Cost Alternative to SAC Alloys for PCB Assembly Our thanks to Indium Corporation for allowing us to reprint the following article. By Brook Sandy and Ronald C. Lasky, PhD, PE., Indium Corporation
PRODUCT PROFILE. ELECTROLOY in partnership with FCT Asia Pte Limited. in manufacturing. Nihon Superior Lead Free Solder Bar.
PRODUCT PROFILE ELECTROLOY in partnership with FCT Asia Pte Limited in manufacturing Nihon Superior Lead Free Solder Bar SN100C Product Name Product Code LEAD FREE BAR LEAD FREE BAR ( TOP UP ALLOY ) SN100C
RoHS-Compliant Through-Hole VI Chip Soldering Recommendations
APPLICATION NOTE AN:017 RoHS-Compliant Through-Hole VI Chip Soldering Recommendations Ankur Patel Associate Product Line Engineer Contents Page Introduction 1 Wave Soldering 1 Hand Soldering 4 Pin/Lead
SURFACE FINISHING FOR PRINTED CIRCUIT BOARDS
SURFACE FINISHING FOR PRINTED CIRCUIT BOARDS In a world of ever-increasing electronic component complexity and pin count requirements for component packaging, focus is once again on the age-old question
MuAnalysis. Printed Circuit Board Reliability and Integrity Characterization Using MAJIC. M. Simard-Normandin MuAnalysis Inc. Ottawa, ON, Canada
Printed Circuit Board Reliability and Integrity Characterization Using MAJIC M. Simard-Normandin Inc. Ottawa, ON, Canada Abstract The recent need to develop lead-free electrical and electronic products
Characterization and Kinetics of the Interfacial Reactions in Solder Joints of Tin-Based Solder Alloys on Copper Substrates
Characterization and Kinetics of the Interfacial Reactions in Solder Joints of Tin-Based Solder Alloys on Copper Substrates J. C. Madeni*, S. Liu* and T. A. Siewert** *Center for Welding, Joining and Coatings
Pure Tin - The Finish of Choice for Connectors
Pure Tin - The Finish of Choice for Connectors Pete Elmgren and Dan Dixon Molex Lisle, IL Robert Hilty, Ph.D. Tyco Electronics Harrisburg, PA Thomas Moyer and Sudarshan Lal, Ph.D. FCI Etters, PA Axel Nitsche
Specification for Electroless Nickel/ Electroless Palladium/ Immersion Gold (ENEPIG) Plating for Printed Circuit Boards
Specification for Electroless Nickel/ Electroless Palladium/ Immersion Gold (ENEPIG) Plating for Printed Circuit Boards Developed by the Plating Processes Subcommittee (4-14) of the Fabrication Processes
Electronic Board Assembly
Electronic Board Assembly ERNI Systems Technology Systems Solutions - a one stop shop - www.erni.com Contents ERNI Systems Technology Soldering Technologies SMT soldering THR soldering THT soldering -
Wurth Electronics Midcom Policy Statement on RoHS Compliance And Lead-Free Products
Wurth Electronics Midcom Policy Statement on RoHS Compliance And Lead-Free Products General Environmental Policy Wurth Electronics Midcom is committed to the manufacture of environmentally-friendly products
Selective Soldering Defects and How to Prevent Them
Selective Soldering Defects and How to Prevent Them Gerjan Diepstraten Vitronics Soltec BV Introduction Two major issues affecting the soldering process today are the conversion to lead-free soldering
REVISION HISTORY APPROVERS
REVISION HISTORY Revision Description of Change Writer/Reviser Effective Date 1.0 As Issued. Renumbered from PEC-MAT-2-003-00. Lenora Bennett January 23, 2012 2.0 Updated Table 1 Nickel barrier specifications
Lead-Free Rework Optimization Project
Lead-Free Rework Optimization Project Project Co-Chairs: Jasbir Bath, Flextronics International Craig Hamilton, Celestica IPC APEX 2008 Background Reliability tests in the previous inemi lead-free assembly
BGA - Ball Grid Array Inspection Workshop. Bob Willis leadfreesoldering.com
BGA - Ball Grid Array Inspection Workshop Bob Willis leadfreesoldering.com Mixed Technology Assembly Processes Adhesive Dispensing Component Placement Adhesive Curing Turn Boar Over Conventional Insertion
Materials Chemistry and Physics 85 (2004) 63 67. Meng-Kuang Huang, Pei-Lin Wu, Chiapyng Lee
Materials Chemistry and Physics 85 (2004) 63 67 Effects of different printed circuit board surface finishes on the formation and growth of intermetallics at thermomechanically fatigued small outline J
Mounting of Meritec SMT Products Using Lead-Free Solder
Mounting of Meritec SMT Products Using Lead-Free Solder 10/10/08 rev B Mounting of Meritec SMT Products Using Lead-Free Solder Contents Page 2 Scope Page 3 Test Samples/Preparation Page 3 Facilities/Equipment
Rework stations: Meeting the challenges of lead-free solders
Rework stations: Meeting the challenges of lead-free solders Market forces, particularly legislation against the use of lead in electronics, have driven electronics manufacturers towards lead-free solders
PRINTED CIRCUIT BOARD SURFACE FINISHES - ADVANTAGES AND DISADVANTAGES
PRINTED CIRCUIT BOARD SURFACE FINISHES - ADVANTAGES AND DISADVANTAGES By Al Wright, PCB Field Applications Engineer Epec Engineered Technologies Anyone involved within the printed circuit board (PCB) industry
Review of the Impact of Intermetallic Layers on the Brittleness of Tin-Lead and Lead-Free Solder Joints
Review of the Impact of Intermetallic Layers on the Brittleness of Tin-Lead and Lead-Free Solder Joints Per-Erik Tegehall, Ph.D. 6-03-15 Preface This review has been funded by Vinnova (Swedish Governmental
Assembly of LPCC Packages AN-0001
Assembly of LPCC Packages AN-0001 Surface Mount Assembly and Handling of ANADIGICS LPCC Packages 1.0 Overview ANADIGICS power amplifiers are typically packaged in a Leadless Plastic Chip Carrier (LPCC)
Lead-Free Soldering and Environmental Compliance: An Overview
CHAPTER 1 Lead-Free Soldering and Environmental Compliance: An Overview Dongkai Shangguan, Flextronics International Introduction Solder interconnects perform three major functions: electrical, mechanical,
Evaluation of Soft Soldering on Aluminium Nitride (AlN) ESTEC Contract No. 19220/05/NL/PA. CTB Hybrids WG ESTEC-22nd May 2007
Evaluation of Soft Soldering on Aluminium Nitride (AlN) ESTEC Contract No. 19220/05/NL/PA CTB Hybrids WG ESTEC-22nd May 2007 Evaluation of Soft Soldering on AlN Schedule Project presentation Feasibility
Application Note AN-0994 Maximizing the Effectiveness of your SMD Assemblies
Application Note AN-0994 Maximizing the Effectiveness of your SMD Assemblies Table of Contents Page Method...2 Thermal characteristics of SMDs...2 Adhesives...4 Solder pastes...4 Reflow profiles...4 Rework...6
How to Build a Printed Circuit Board. Advanced Circuits Inc 2004
How to Build a Printed Circuit Board 1 This presentation is a work in progress. As methods and processes change it will be updated accordingly. It is intended only as an introduction to the production
Compliant Terminal Technology Summary Test Report
Engineering Report ER04100 October 5th, 2004 Revision A Copyright Autosplice Inc., September 2004 Table of Contents Summary Overview 3 Compliant Terminal Specifications 3 Test Plan 4 Test Conditions 4
Solder Reflow Guide for Surface Mount Devices
June 2015 Introduction Technical Note TN1076 This technical note provides general guidelines for a solder reflow and rework process for Lattice surface mount products. The data used in this document is
White Paper. Modification of Existing NEBS Requirements for Pb-Free Electronics. By Craig Hillman, PhD
White Paper Modification of Existing NEBS Requirements for Pb-Free Electronics By Craig Hillman, PhD Executive Summary Thorough review of the relevant NEBS requirements identified several areas of concerns
DETECTION OF DEFECT ON FBGA SOLDER BALLS USING X-RAY TECHNOLOGY
DETECTION OF DEFECT ON FBGA SOLDER BALLS USING X-RAY TECHNOLOGY Pavel Řihák Doctoral Degree Programme (2), FEEC BUT E-mail: [email protected] Supervised by: Ivan Szendiuch E-mail: [email protected]
PCB inspection is more important today than ever before!
PCB inspection is more important today than ever before! Industry experts continue to stress the need to inspect hidden solder joints! Figure 1. The BGA package has not been placed into the paste deposit.
Self Qualification Results
(ATO) Divisional Philips Semiconductors Philips Internal Report No.: RNR- 8 3-03/RdH/RdH- 2 0 3 6 QTS Report Database No.: 030692 Self Qualification Results NiPdAu lead- free solution of SO14/16/20 Products
Thermal Management Solutions for Printed Circuit Boards used in Digital and RF Power Electronics and LED assemblies
Thermal Management Solutions for Printed Circuit Boards used in Digital and RF Power Electronics and LED assemblies Sandy Kumar, Ph.D. Director of Technology American Standard Circuits, Inc 3615 Wolf Road
Lead-free Hand-soldering Ending the Nightmares
Lead-free Hand-soldering Ending the Nightmares Most issues during the transition seem to be with Hand-soldering As companies transition over to lead-free assembly a certain amount of hand-soldering will
What is surface mount?
A way of attaching electronic components to a printed circuit board The solder joint forms the mechanical and electrical connection What is surface mount? Bonding of the solder joint is to the surface
Designing with High-Density BGA Packages for Altera Devices
2014.12.15 Designing with High-Density BGA Packages for Altera Devices AN-114 Subscribe As programmable logic devices (PLDs) increase in density and I/O pins, the demand for small packages and diverse
Sn-Cu Intermetallic Grain Morphology Related to Sn Layer Thickness
Journal of ELECTRONIC MATERIALS, Vol. 36, No. 11, 2007 DOI: 10.1007/s11664-007-0270-x Ó 2007 TMS Special Issue Paper -Cu Intermetallic Grain Morphology Related to Layer Thickness MIN-HSIEN LU 1 and KER-CHANG
1.Introduction. Introduction. Most of slides come from Semiconductor Manufacturing Technology by Michael Quirk and Julian Serda.
.Introduction If the automobile had followed the same development cycle as the computer, a Rolls- Royce would today cost $00, get one million miles to the gallon and explode once a year Most of slides
Advanced Technologies and Equipment for 3D-Packaging
Advanced Technologies and Equipment for 3D-Packaging Thomas Oppert Semicon Russia 15 th May 2014 Outline Short Company Introduction Electroless Plating on Wafer Level Ultra-SB 2 - Wafer Level Solder Balling
AND8464/D. Board Level Application Note for 0402, 0502 and 0603 DSN2 Packages APPLICATION NOTE
Board Level Application Note for 0402, 0502 and 0603 DSN2 Packages Prepared by: Denise Thienpont, Steve St. Germain ON Semiconductor APPLICATION NOTE Introduction ON Semiconductor has introduced an expanded
Good Boards = Results
Section 2: Printed Circuit Board Fabrication & Solderability Good Boards = Results Board fabrication is one aspect of the electronics production industry that SMT assembly engineers often know little about.
Interfacial Reaction between Sn Ag Co Solder and Metals
Materials Transactions, Vol. 46, No. 11 (25) pp. 2394 to 2399 Special Issue on Lead-Free ing in Electronics III #25 The Japan Institute of Metals Interfacial Reaction between Sn Ag Co and Metals Hiroshi
Q&A. Contract Manufacturing Q&A. Q&A for those involved in Contract Manufacturing using Nelco Electronic Materials
Q&A Q&A for those involved in Contract Manufacturing using Nelco Electronic Materials 1. Do Nelco laminates have any discoloration effects or staining issues after multiple high temperature exposures?
GUIDELINES FOR PRINTED CIRCUIT BOARD ASSEMBLY (PCBA) OF UTAC GROUP S GRID ARRAY PACKAGE (GQFN) AND ITS BOARD LEVEL RELIABILITY
GUIDELINES FOR PRINTED CIRCUIT BOARD ASSEMBLY (PCBA) OF UTAC GROUP S GRID ARRAY PACKAGE (GQFN) AND ITS BOARD LEVEL RELIABILITY Kyaw Ko Lwin*, Daniel Ting Lee Teh, Carolyn Epino Tubillo, Jun Dimaano, Ang
Lead-Free Product Transition: Impact on Printed Circuit Board Design and Material Selection
Presented in the ECWC 10 Conference at IPC Printed Circuits Expo, SMEMA Council AP EX and Designers Summit 05 Lead-Free Product Transition: Impact on Printed Circuit Board Design and Material Selection
Interface Reaction and Mechanical Properties of Lead-free Sn Zn Alloy/Cu Joints
Materials Transactions, Vol. 43, No. 8 (2002) pp. 1797 to 1801 Special Issue on Lead-Free Electronics Packaging c 2002 The Japan Institute of Metals Interface Reaction and Mechanical Properties of Lead-free
CONSIDERATIONS FOR SELECTING A PRINTED CIRCUIT BOARD SURFACE FINISH
CONSIDERATIONS FOR SELECTING A PRINTED CIRCUIT BOARD SURFACE FINISH Randy Schueller, Ph.D. DfR Solutions Minneapolis, MN, USA [email protected] ABSTRACT The selection of the surface finish to
Bob Willis leadfreesoldering.com
Assembly of Flexible Circuits with Lead-Free Solder Alloy Bob Willis leadfreesoldering.com Introduction to Lead-Free Assembly Video Clips Component www.bobwillis.co.uk/lead/videos/components.rm Printed
PCB Assembly Guidelines for Intersil Wafer Level Chip Scale Package Devices
Assembly Guidelines for Intersil Wafer Level Chip Scale Package Devices Introduction There is an industry-wide trend towards using the smallest package possible for a given pin count. This is driven primarily
Influence of Solder Reaction Across Solder Joints
Influence of Solder Reaction Across Solder Joints Kejun Zeng FC BGA Packaging Development Semiconductor Packaging Development Texas Instruments, Inc. 6 th TRC Oct. 27-28, 2003 Austin, TX 1 Outline Introduction
Correlation of Material properties to the Reliability performance of High Density BGA Package solder joints:
Correlation of Material properties to the Reliability performance of High Density BGA Package solder joints: By.S. devan For IPC Reliability Summit February 23, 2007 Legal Information THIS DOCUMENT AND
Thermal Fatigue Assessment of Lead-Free Solder Joints
Thermal Fatigue Assessment of Lead-Free Solder Joints Qiang YU and Masaki SHIRATORI Department of Mechanical Engineering and Materials Science Yokohama National University Tokiwadai 79-5, Hodogaya-ku,
Edition 2012-032 Published by Infineon Technologies AG 81726 Munich, Germany 2013 Infineon Technologies AG All Rights Reserved.
Recommendations for Printed Circuit Board Assembly of Infineon Laminate Packages Additional Information DS1 2012-03 Edition 2012-032 Published by Infineon Technologies AG 81726 Munich, Germany 2013 Infineon
Component Candidacy of Second Side Reflow with Lead-Free Solder
Materials Transactions, Vol. 47, No. 6 (006) pp. 577 to 583 #006 The Japan Institute of Metals Component Candidacy of Second Side Reflow with Lead-Free Solder Yueli Liu ; *, David A. Geiger and Dongkai
Edition 2012-05 Published by Infineon Technologies AG 81726 Munich, Germany 2012 Infineon Technologies AG All Rights Reserved.
Recommendations for Printed Circuit Board Assembly of Infineon QFN Packages Additional Information DS7, 2012-05 Edition 2012-05 Published by Infineon Technologies AG 81726 Munich, Germany 2012 Infineon
Soldering of SMD Film Capacitors in Practical Lead Free Processes
Soldering of SMD Film Capacitors in Practical Lead Free Processes Matti Niskala Product Manager, SMD products Evox Rifa Group Oyj, a Kemet Company Lars Sonckin kaari 16, 02600 Espoo, Finland Tel: + 358
Reliability of Eutectic Sn-Pb Solder Bumps and Flip Chip Assemblies
Reliability of Eutectic Sn-Pb Solder Bumps and Flip Chip Assemblies Xingjia Huang 1, Christine Kallmayer 2, Rolf Aschenbrenner 2, S.-W. Ricky Lee 1 1 Department of Mechanical Engineering Hong Kong University
Auditing Contract Manufacturing Processes
Auditing Contract Manufacturing Processes Greg Caswell and Cheryl Tulkoff Introduction DfR has investigated multiple situations where an OEM is experiencing quality issues. In some cases, the problem occurs
Preface xiii Introduction xv 1 Planning for surface mount design General electronic products 3 Dedicated service electronic products 3 High-reliability electronic products 4 Defining the environmental
CIRCUITS AND SYSTEMS- Assembly and Printed Circuit Board (PCB) Package Mohammad S. Sharawi ASSEMBLY AND PRINTED CIRCUIT BOARD (PCB) PACKAGE
ASSEMBLY AND PRINTED CIRCUIT BOARD (PCB) PACKAGE Mohammad S. Sharawi Electrical Engineering Department, King Fahd University of Petroleum and Minerals Dhahran, 31261 Saudi Arabia Keywords: Printed Circuit
How to avoid Layout and Assembly got chas with advanced packages
How to avoid Layout and Assembly got chas with advanced packages Parts and pitch get smaller. Pin counts get larger. Design cycles get shorter. BGA, MicroBGA, QFN, DQFN, CSP packages are taking the design
The Study, Measurement, and Prevention of Tarnish on Immersion Silver Board Finishes
The Study, Measurement, and Prevention of Tarnish on Immersion Silver Board Finishes Lenora Toscano and Donald Cullen MacDermid, Inc. Waterbury, CT USA ABSTRACT With increased environmental legislation
Lead-free soldering of telecommunication network infrastructure products
Lead-free soldering of telecommunication network infrastructure products Bo Eriksson and Richard Trankell, Ericsson AB Abstract Ericsson has successfully transferred to lead-free solder for its high volume
Accelerated Thermal Cycling and Failure Mechanisms For BGA and CSP Assemblies
Accelerated Thermal Cycling and Failure Mechanisms For BGA and CSP Assemblies Reza Ghaffarian, Ph.D. Jet Propulsion Laboratory California Institute of Technology Pasadena, California 818-354-2059 [email protected]
Wetting Behavior of Pb-free Solder on Immersion Tin Surface Finishes in Different Reflow Atmospheres
Wetting Behavior of Pb-free Solder on Immersion Tin Surface Finishes in Different Reflow Atmospheres Sven Lamprecht 1, Dr. Kenneth Lee 2, Bill Kao 3, Günter Heinz 1 1 Atotech Deutschland GmbH, Berlin,
Printed Circuits. Danilo Manstretta. microlab.unipv.it/ [email protected]. AA 2012/2013 Lezioni di Tecnologie e Materiali per l Elettronica
Lezioni di Tecnologie e Materiali per l Elettronica Printed Circuits Danilo Manstretta microlab.unipv.it/ [email protected] Printed Circuits Printed Circuits Materials Technological steps Production
REACTIONS IN THE SN CORNER OF THE CU-SN-ZN ALLOY SYSTEM
REACTIONS IN THE SN CORNER OF THE CU-SN-ZN ALLOY SYSTEM D.D. Perovic, L Snugovsky and J.W. Rutter Department of Materials Science and Engineering University of Toronto Toronto, ON, Canada [email protected]
Application Note. Soldering Methods and Procedures for 1st and 2nd Generation Power Modules. Overview. Analysis of a Good Solder Joint
Soldering Methods and Procedures for 1st and 2nd Generation Power Modules Overview This document is intended to provide guidance in utilizing soldering practices to make high quality connections of Vicor
Choosing a Stencil. By William E. Coleman, Ph.D. and Michael R. Burgess
Choosing a Stencil Is a stencil a commodity or a precision tool? A commodity is something that can be purchased from many suppliers, with the expectation that the performance will be the same. A precision
Lead-Free Universal Solders for Optical and MEMS Packaging
Lead-Free Universal Solders for Optical and MEMS Packaging Sungho Jin Univ. of California, San Diego, La Jolla CA 92093 OUTLINE -- Introduction -- Universal Solder Fabrication -- Microstructure -- Direct
RoHS / Lead-Free Initiative. Microsemi Analog Mixed Signal Group
RoHS / Lead-Free Initiative Microsemi Analog Mixed Signal Group Table of Contents RoHS / Pb-Free Initiative............................................... 3 RoHS / Pb-Free Transition Strategy......................................
LEAD FREE HALOGENFREE. Würth Elektronik PCB Design Conference 2007. Lothar Weitzel 2007 Seite 1
LEAD FREE HALOGENFREE Würth Elektronik PCB Design Conference 2007 Lothar Weitzel 2007 Seite 1 Content Solder surfaces/overview Lead free soldering process requirements/material parameters Different base
SOLDER CHARGE SMT: THE DESIGN AND VALIDATION OF NEW SOLDER ATTACH TECHNOLOGIES
SOLDER CHARGE SMT: THE DESIGN AND VALIDATION OF NEW SOLDER ATTACH TECHNOLOGIES Jim Hines 1, Kirk Peloza 2, Adam Stanczak 3, David Geiger 4 1 Molex Lisle, IL, USA 2 Molex Lisle, IL, USA 3 Molex Lisle, IL,
Flex Circuit Design and Manufacture.
Flex Circuit Design and Manufacture. Hawarden Industrial Park, Manor Lane, Deeside, Flintshire, CH5 3QZ Tel 01244 520510 Fax 01244 520721 [email protected] www.merlincircuit.co.uk Flex Circuit
Reliability Stress Test Descriptions
1. Solder Reflow Preconditioning (PRECON): The preconditioning stress sequence is performed for the purpose of evaluating the capability of semiconductor devices to withstand the stresses imposed by a
Electroless Nickel / Immersion Gold Process Technology for Improved Ductility of Flex and Rigid-Flex Applications
M44.44kk-growth Electroless Nickel / Immersion Gold Process Technology for Improved Ductility of Flex and Rigid-Flex Applications By: Kuldip Johal and Hugh Roberts - Atotech USA Inc. Sven Lamprecht and
Lapping and Polishing Basics
Lapping and Polishing Basics Applications Laboratory Report 54 Lapping and Polishing 1.0: Introduction Lapping and polishing is a process by which material is precisely removed from a workpiece (or specimen)
ALPHA OL-107F-A ZERO-HALOGEN, LOW VOIDS, FINE FEATURE, EXCELLENT PIN TEST PERFORMANCE, NO-CLEAN, LEAD-FREE SOLDER PASTE
T E C H N I C A L B U L L E T I N ALPHA OL-107F-A ZERO-HALOGEN, LOW VOIDS, FINE FEATURE, EXCELLENT PIN TEST PERFORMANCE, NO-CLEAN, LEAD-FREE SOLDER PASTE DESCRIPTION ALPHA OL-107F-A is a lead-free, Zero-halogen
Fraunhofer ISIT, Itzehoe 14. Juni 2005. Fraunhofer Institut Siliziumtechnologie (ISIT)
Research and Development centre for Microelectronics and Microsystems Applied Research, Development and Production for Industry ISIT applies an ISO 9001:2000 certified quality management system. Certificate
Failure Analysis (FA) Introduction
Failure Analysis (FA) Introduction (III - Reliability ) Tung-Bao Lu 1 of 23 Reliability Stress Stress Reliability Geberal Condition Temperature Humidity Electrical Others Precondition Baking/L3/Reflowing
NEPP TRO Lead-Free Soldering for Space Applications Lead-Free Solder Body of Knowledge
NEPP TRO Lead-Free Soldering for Space Applications Lead-Free Solder Body of Knowledge Kurt Kessel ITB, Inc. Kennedy Space Center, Florida [email protected] May 2005 Under the sponsorship of Mark
