Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, ColdFire+, C- Ware, the Energy Efficient Solutions logo, Kinetis,

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1 March 2013 Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, ColdFire+, C- Ware, the Energy Efficient Solutions logo, Kinetis, mobilegt, PEG, PowerQUICC, Processor Expert, QorIQ, Qorivva, StarCore, Symphony and VortiQa are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. Airfast, BeeKit, BeeStack, CoreNet, Flexis, Layerscape, MagniV, MXC, Platform in a Package, QorIQ Qonverge, QUICC Engine, Ready Play, SafeAssure, the SafeAssure logo, SMAROS, Tower, TurboLink, Vybrid and Xtrinsic are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners Freescale Semiconductor, Inc.

2 This session will provide an overview of the Enterprise WLAN market trends and discuss CPU processing requirements for ac Access Points, how to select the right processor based on performance (workload, utilization and throughput), power and cost. Single user monthly data consumption forecast (source: Alcatel Lucent) 2

3 Market Overview QorIQ P1 based Reference design solutions CPU Requirements Roadmap Performance Scalability Performance and processing requirements of n/11ac Workload, Utilization, Throughput Freescale solutions for n and 80.11ac Atheros CUS223 based dual-band solution Broadcom BCM based dual-band solution Freescale WLAN Access Controller Solution Freescale NAS update 3

4 Unit shipments (%) 100% 80% 60% 40% 20% Access Points by Technology: a/b/g vs n vs ac a/b/g adoption is going down, and will be replaced by 11n/11ac soon. The first next-generation ac products will appear in 2Q ac will start nibbling away at n s share, and could well account for over 40% of APs by % CY10 CY11 CY12 CY13 CY14 CY15 CY16 Source: Infonetics.11a/b/g.11n.11ac 4

5 K unit By the end of 2010, China mobile already set up 120,000 WLAN access point, while China telecom has 100,000 one, China Unicom has 30,000 one. In 2010, three Operator plan to put into 30 billion RMB for WLAN access equipment in next 3 years. Both China telecom and China Mobile announced to set up 1million WLAN Access points before end of Each WLAN controller will set up average ten to hundred WLAN Access Points. We estimate 3x3 AP will take 30% of whole AP market by end of

6 Security Accel XOR TDM 32KB I- Cache e500 Core 3x GE MAC 32KB D- Cache 256KB L2 Coherency Module System System Bus Bus DMA 32KB I- Cache e500 Core 32KB D- Cache On-Chip Network PCI Express x4 SerDes PCI Express DDR2/DDR3, SDRAM Controller Enhanced Local Bus Perf Mon, DUART, MPIC 2x I2C, Timers USB2.0 SD/MMC SPI 32b 16b Dual e500 Power Architecture core MHz 256KB Frontside L2 cache w/ecc, HW cache coherent 36 bit physical addressing, DP-FPU System Unit 32-bit DDR2/DDR3 with ECC to 800MHz datarate Integrated SEC 3.3 Security Engine Open-PIC Interrupt Controller, Perf Mon, 2x I2C, Timers, 16 GPIO s, DUART 16-bit Enhanced Local Bus supports booting from NAND Flash Two USB 2.0Controllers Host/Device support SPI controller supporting booting from SPI serial Flash SD/MMC card controller supporting booting from Flash cards TDM interface Three 10/100/1000 Ethernet Controllers (etsec) w/ Jumbo Frame support, SGMII interface Enhanced features: Parser/Filer, QOS, IP- Checksum Offload, Lossless Flow Control IEEE1588v2 Support Two PCI Express 1.0a Controllers operating at 2.5GHz Power Management Process & Package 45nm SOI, XX +/- XX, 0C to 125C Tj with -40C to 125C Tj option 689-pin TePBGAII, 31x31mm, 1.0mm pitch 6

7 2x GE MAC SATA Security Accel XOR Advanced Power Management LCD (DIU) I 2 S IEEE e500 Core 32kB I-Cache 32kB D-Cache Coherency Module System System Bus Bus x2 SERDES 256KB L2 2x DMA Dual x1 PCIe Single x2 PCIe Dual SATA P1022 dual core e500 Core 32kB I-Cache 32kB D-Cache On-Chip Network PCI Express PCI Express x4 SERDES Single x4 PEX Dual x2 PEX Single x2 + dual x1 DDR2/DDR3, SDRAM Controller Enhanced Local Bus Perf Mon, DUART, MPIC 2x I2C, Timers SPI 2x USB2.0 SD/MMC PCI Express Scalable performance for Media Application Processing Up to 1.0GHz operation High Speed DDR2 and DDR3 (800MHz) HW math and secure networking acceleration Integrated system peripherals Dual USB 2.0 SD/MMC SATA Gigabit Ethernet LCD Low cost PCB layout Open Standard High Speed Serial Interconnect 3 PCI Express Controller 6 lanes High Speed SPI, SGMII, I2S Green Operation Low power fanless dynamic operation = <4W typical at dual core 800MHz Advanced Power Management Split power planes for power-down deep-sleep operation for EnergyStar support Programmable wake-on-packet <300mW deep Process & Package 45nm, 1.0V+/-50mV, 0C-105C Tj TePBGAII 7

8 TDM (3) VeTSEC/ VortiQa External Tamper Detect Security Accel XOR Security Monitor Internal BootROM JTAG e500 Core 32kB I-Cache 32kB D-Cache System Bus Bus 1x DMA 256KB L2 CCSR Access Controller On-Chip Network SATAx2 x6 SERDES Trust DDR etsec PCIe x2 DDR3/LP SDRAM Controller (IFC) Flash Cont. Perf Mon, DUART, MPIC 2x I2C, Timers SPI USB2.0 w/phy ecan3.0 x2 SD/MMC e500 v2, MHz 256 KB Frontside L2 cache w/ecc, HW cache coherent 36 bit physical addressing System Unit 16-/32-bit DDR3, 800 MHz data rate w/ecc Integrated SEC 4.x Lite Security Engine with Secure Boot Flash Controller supporting NOR, SLC and MLC based NAND devices One USB 2.0Controllers Host/Device support with Integrated PHY SD/MMC card controller supporting booting from Flash cards VortiQa based data path acceleration with (3) 10/100/1000 Ethernet Controllers w/ Jumbo Frame support, SGMII interface, IEEE1588v2 Support Two PCI Express 1.0a Controllers operating up to 2.5Gbps Two SATA Controller, 3.0 Gb/S Two ecan3.0 Controllers 4x UARTs, 2x I2Cs Process & Package 45nm SOI 425-pin TEPBGA I (19mmx19mm, 0.8mm pitch) <3W power consumption P1010 Yes x32 3x P1014 No x16 2x 8

9 Device reference manual Primary User Handbook of the device Detailed description on Reset and Boot-up Define the Soc from register level Device hardware specification Detailed define SoC Electronical Characteristics Device design checklist Detailed define Proper Pin arrangements DDR3 Layout Guide Application Note Provide specific guideline on how to properly route DDR3 traces. P1020WLAN and P1022DS design source files Schematic, Layout, and Gerber are provided in source files. 9

10 Processor Options P1010, P1014 P1015, P1024 P1011, P x USB x GbE PoE Module P1020WLAN(Enterprise Access Point) General Features: P1020 (800MHz Core, 667/800DDR3) Memory subsystem: 256MB to 512MB DDR3 SDRAM Up to 64MB NOR FLASH Up to 256MB of NAND Flash Support Atheros AR93xx for n Support a/b/g/n dual band dual cards 3 x 3 MIMO solution Proven Opensource OpenWRT application program Arada Advance Wireless Enterprise AP Software (evaluation copy) Support system configuration & management using GUI; Reset & Factory default 2x MiniPCI-e, 2x10/100/1000 Base-T, USB Type A connector Power over Ethernet support FCC/CE Class A certified Mini-ITX form factor PCB Ordering Information: P1020WLAN - Support Atheros XB114 MiniPCIe card Schedule: Prototype May, 2010, Production Q4,

11 RS232 Serial USB PHY SERDES Clocking POR Cfg. Power Ckt PoE JTAG COP DDR DDR3 SD/MMC esdhc elbc NAND NOR USB TypeA USB TypeA USB/ULPI QorIQ P1020 x1 x1 Mini PCIe Mini PCIe RJ45 DUART GE GE PHY PHY RJ45 RJ45 EEPROM I2C 11

12 SDK Detailed Features on Individual Platforms U-Boot v Boot from NAND Flash (without ECC) (X8bit, small page NAND Flash) - Boot from NOR Flash (X16bit flash) - Boot from espi Flash - DDR3 supported - NAND Flash Read/Write operation(without ECC) - NOR Flash Read/ Write operation. - Support TFTP protocol for download over Ethernet - Support kernel booting from Network - Support CPU/board-specific configuration - Support PCIe host driver initialization in U-boot - Support USB (UI) - Support espi controller - Reset mechanism - esata and isata interfaces enabled. Support loading kernel and file system from SATA harddisk by default - 36bit Physical addressing SDK summary: Tool Chain Version: - Gcc-4.5.1, eglibc-2.11, binutils , CodeSourcery release supporting the e500v2 cores. U-Boot Version: v Freescale patches Kernel Version: Hardware Platforms: Processors: P1014E CPU Rev 1.0 (PVR = 0x , SVR = 0x80f90110) P1020E CPU Rev 1.1 (PVR = 0x , SVR =0x80EC0011) P1021E CPU Rev 1.1 (PVR = 0x , SVR = 0x80ec0111) P1012E CPU Rev 1.1 (PVR = 0x , SVR = 0x80ed0111) P1024E CPU Rev 1.1 (PVR = 0x , SVR =0x80ec0211) 12

13 Feature O/S, BSP Wireless Wi-Fi Comment Linux 2.6.xx or later with redundant boot process from FLASH b/g/n compatible Wireless Modules Broadcom BCM43460, ac, and BCM n Atheros Support: AR93xx Wireless Security System Configuration & Management Protocols UPnP DHCP DNS QoS PSK, WEP, WPA2, authentication with Radius MAC address filtering Web browser based, TFTP: FTP & Telnet, System configuration restore in FLASH memory (Firmware update) TR-069 based remote configuration & management * IPv4 and IPv6, RIP v1/v2, TCP/IP, UDP, PPTP, PPPOE, DMZ, VLAN, Bridging, NAT/PAT, IGMP, VPN, Firewall, ACL, IDS Open Source SDK with configuration interface and integration DHCP Client, DHCP Relay Agent, DHCP Server DNS Relay, Dynamic DNS Based on IP/DSCP/Port/Protocol with WRR *Software features will be phased so not all listed features will be available in the Initial prototype release. 13

14 OpenWRT utility is provided as patches to standard SDK 14

15 PHY Control & Data Plane Traffic CPU Data Plane Data Plane PHY Acceleratio n H/W Control plane CPU Data Plane PHY Soft ASF Control plane Default Network ing a. Forwarding by CPU b. Hardware based Data Path Acceleration CPU c. Software based Data Path Acceleration What is ASF? - Module that accelerates the data throughput for the networking devices Most network packet processing protocols can be classified to follow two paths Fast path (Data Path) requires quick and efficient switching/routing Slow path(control Path) requires complex processing and has more inherent latency Customized to platform: Optimized implementation for Data Path processing Leverages HW functionality: Hashing, checksum calculation, cryptography, classification, scheduling to provide higher throughput 15

16 Application Data Path Control Path Layer 2 bridging IPv4 forwarding NAPT FDB lookup, VLAN add/delete, Learning Dest-cache lookup, L2 modify 5-tuple lookup, IP/Port/L2 modify Aging, STP route-table lookup, ARP Connection setup/destroy, policy, ALG Firewall Access control list, pin-holes Stateful packet inspection, ALG IPSec QoS 5-tuple lookup, encap/decap + crypto Enforcement sched, police, congestion, shaper SA setup, security policy Policy, provisioning 16

17 MIMO 3x3 means 3x Rx/Tx PHY Each PHY has 150 Mbps physical bandwidth Totally 3x PHYs can provide 450Mbps physical bandwidth It is not possible to achieve physical line rate. Usually 60% of line rate is considered as good performance. Thus, actual data rate is ~60% of 450Mbps = 270Mbps. This is the single-band or single radio card performance. For dual-band performance, it is 2x times the single-band performance which is 540Mbps. In reality, dual-band operation brings up harmonic interferences which makes 1+1 < 2x performance 17

18 Streams MIMO 3x3 means 3x Rx/Tx PHY n n ac ac 20MHz 40MHz 80MHz 160MHz 1 75Mbps 150Mbps 433Mbps 867Mbps 2 150Mbps 300Mbps 867Mbps 1.7Gbps 3 225Mbps 450Mbps 1.3Gbps 2.6Gbps Each PHY has 433 Mbps physical bandwidth Totally 3x PHYs can provide 1300Mbps physical bandwidth In wireless communication, it is quite impossible to achieve physical line rate. Usually 60% converting rate calls a good solution. Thus, actual data rate is ~60% of 1300Mbps = 780Mbps. This is so called the single-band or single radio card performance. Multi-user MIMO not supported yet in current 11ac spec. 18

19 IxChariott Host DUT DUT: Device under test, P1020WLAN Host: Win XP based IxChariot 5.4 Benchmark Host PC1: Win 7 32-bit 2.4G end-point Wi-Fi Client PC2: Win 7 32-bit 5G end-point Wi-Fi Client Conductive Mode: DUT and End-points are connected in conductive mode cable through a properly configured Attenuator. Over-the-air Mode: DUT and End-points are linked over the antennas in a shielding room. Open-air Mode: DUT and End-points are linked over the antennas in a office environment where interferences exists 19

20 Increased Bandwidth PCIe Gen.2 Increased SoC Performance Next Generation WLAN EAP solutions Mandatory POE support Increased SoC Performance 20-30% above P1020 Mandatory PoE support Must support.af spec Support for PCIe Gen.2 within the POE TDP envelope SoC still needs to be able to fit within the sub-3.5w TDP Drives requirement for 28nm technology node 20

21 Best Processors Turnkey Software Key Platform Right Partners Freescale QorIQ Processors VortiQa Software Security Applications Optimized Reference Design ODM Integration Partners Freescale Reference Design QorIQ P1 Family Processors Sample of ODM Partners Accton Senao USI Wistron / Neweb 2 x USB x GbE PoE Module 21

22 DUT: Device under test, P1010RDB or P1020WLAN, IP: PC1-0: IxChariot Benchmark Host, IP: PC1-1: Iperf Benchmark Host, IP: PC3: 5G end-point Wi-Fi Client, IP: Uplink test: Streams from WLAN Client to DUT Downlink test: Streams from DUT to WLAN Client 22

23 PCIe PCIe PCIe PCIe SATA 2.0 SATA 2.0 TDM/HDLC TDM/HDLC Security Fuse Processor Security Monitor 16b IFC Power Management SD/MMC+ 2x DUART 2x I2C SPI, GPIO 2x USB 2.0 w/phy DIU Power Architecture 256 KB e5500 Backside L2 Cache 32 KB 32 KB PAMU Security 5.x (XoR, CRC) Pattern Match Engine 2.0 D-Cache Queue Mgr. Buffer Mgr. PAMU I-Cache Parse, Classify, Distribute 1G 1G 1G 1G 8 Port Switch 1G 1G 1G 1G 1G 1G 1G 1G Device 28HPM Process 780-pin C4 FC package 23x23mm, 0.8mm pitch Power targets Enable Convection cooled system design with reasonable sized heatsink Cygnus Coherency Fabric PAMU 2xDMA 8-Lane 5GHz SERDES 256KB Platform Cache QUICC Engine 32/64-bit DDR3L/4 DDR2/3 Memory Controller PAMU Perf Monitor Datapath Acceleration SEC- crypto acceleration PME- Reg-ex Pattern Matcher Peripheral Access Mgmt Unit Real Time Debug Watchpoint Cross Trigger CoreNet Trace Processor 4x e5500, 64b, up to 1.4GHz Each with 256KB backside L2 cache 256KB Shared Platform Cache w/ecc Supports up to 64GB addressability (36 bit physical addressing) Memory SubSystem 32/64b DDR3L/4 Controller up to 1333MHz Cygnus Switch Fabric High Speed Serial IO 4x PCIe Gen2 Controllers 2x SATA 2.0, 3Gb/s 2x USB 2.0 with PHY Network IO FMan packet Parse/Classify/Distribute Lossless Flow Control, IEEE x 10/100/1000 Ethernet Controllers 8-Port Gigabit Ethernet Switch QUICC Engine HDLC, 2x TDM Green Energy Operation Fanless operation quad-core 1.2GHz Packet lossless deepsleep Programmable wake-on-packet Wake-on-timer/GPIO/USB/IRQ 23

24 Public Key Cryptography Modular Arithmetic Elliptic Curve Cryptographic Functions RSA Encryption, Decryption Cryptographic Authentication MD5 SHA-1 SHA-224, SHA-256, SHA-384, SHA-512 Message Authentication Codes (MAC) HMAC - all hashing algorithms SSL 3.0 MAC (SMAC) - MD5, SHA-1 only CMAC (AES) XCBC-MAC (AES) Kasumi f9 SNOW 3G f9 Advanced Protocol Support IPsec SSL 3.0/TLS SRTP Pkt Encap/Decap DTLS Rec Encap/Decap IEEE i WiFi IEEE WiMAX IEEE 802.1AE MacSec / LinkSec LTE PDCP C-Plane, U-Plane, 3gpp RLC Support for protocol-specific padding Symmetric key block ciphers AES (128, 192 or 256 bit keys) DES (56 bit keys plus optional key parity) 3DES (112 or 168 bit keys plus optional key parity) Cipher modes ECB, CBC, CFB, OFB for all block ciphers CCM, CTR, GCM, XTS for AES Symmetric key stream ciphers ArcFour (Alleged RC4, with bit keys) Kasumi f8 support for 3GPP, ECSD/EDGE and GSM Snow 3G f8 Random Number Generation NIST-compliant pseudo RNG Run Time Integrity Checking SHA-256 authentication support Support for up to 4 independent memory blocks 24

25 Port1 Port3 Spirent Test Center Port2 Port Plain Text UDP Packets CAPWAP DTLS Packets Plain Text UDP Packets PCI Net Card 0 PCI Net Card 1 P5040 Left (CAPWAP Demo app) XAUI 1 Control channel Data channel XAUI 1 P5040 Right (CAPWAP Demo app) PCI Net Card 0 PCI Net Card

26 Device P2/5 (2-4 Core) MHz P102x (Dual Core) MHz Scalable Performance SAMBA RAID5 Access 2Gbps Line Speed in Read and Write SAMBA RAID5 Access DMIPS Headroom for Features File Services Multiple file systems RSYNC, etc. Media Streaming DLNA Compatible UPnP Network DVD player compatible, etc. Network Security Encrypted network logins Secure Sockets Layer (SSL) Enterprise 10GbE NAS SMB 2-4+ Bay NAS 1Gbps Line Speed in Read and Write Network Options DHCP or static IP NTP P101X (Single Core) MHz SAMBA RAID0 Access 90+MB/s and 60+MB/s in Read and Write System Management Performance options Device status alerts and event logs etc. Backup Backup Manager, etc. SOHO 2 Bay NAS 26

27 PCIe SRIO SRIO PCIe PCIe SATA 2.0 SATA 2.0 eopenpic PreBoot Loader Security Monitor Internal BootROM Power Mgmt SD/MMC SPI 2x DUART 4x I 2 C 2x USB 2.0 PHY Clocks/Reset GPIO CCSR elbc 16b Rapid IO RMan Pattern Match Engine 2.0 CoreNet Coherency Fabric 1024 KB Frontside CPCache bit DDR3/3L Memory Controller Peripheral PAMU PAMU PAMU PAMU PAMU Access Mgmt Unit SEC 4.0 Queue Mgr. Buffer Mgr. Power Architecture e500mc Core 32 KB 32 KB D-Cache I-Cache Frame Manager Parse, Classify, Distribute 1GE 1GE Buffer 1GE 1GE 1GE DMA x2 10-Lane 5 GHz SerDes Real Time Debug Watchpoint Cross Trigger Perf Monitor Aurora CoreNet Trace Quad e500mc Power Architecture 4 cores (up to 1.2GHz) 1MB Shared CoreNet Platform Cache w/ecc Memory Controller DDR3/3L SDRAM up to 1200MHz 32/64 bit data bus w/ecc High Speed Interconnect 3 PCIe 2.0 Controllers 2 srapidio 2.1 Controllers Type 9 and 11 messaging 2 SATA 2.0 CoreNet Switch Fabric Ethernet 5 x 10/100/1000 Ethernet Controllers Or 4x 2.5Gb/s SGMII All w/ Classification, H/W Queueing, policing, and Buffer Management, Checksum Offload, QoS, Lossless Flow Control, IEEE 1588 Up to 5 SGMII or 2.5Gb/s SGMII, 2 RGMII Datapath Acceleration SEC 4.0 PME 2.0 Device 45nm SOI Process 783-pin package 23x23mm, 0.8mm pitch 10W thermal max (est) w/o I/O at 1.0GHz

28 PCIe PCIe SRIO SRIO PCIe PCIe SATA 2.0 SATA 2.0 eopenpic PreBoot Loader Security Monitor Internal BootROM Power Mgmt SD/MMC SPI DUART 4x I 2 C 2x USB 2.0 PHY Clocks/Reset GPIO CCSR elbc Power Architecture 512 KB e5500 Core Backside L2 Cache 32 KB 32 KB D-Cache I-Cache Pattern Match Engine 2 Frame Manager Parse, Classify, Distribute 10GE Buffer CoreNet Coherency Fabric Peripheral PAMU PAMU PAMU PAMU Access Mgmt Unit SEC 4 RAID 5/6 Engine Queue Mgr. Buffer Mgr. SRIO Mgr. 1GE 1GE 1GE 1GE 1GE 1024 KB Frontside L3 Cache DMA x2 18-Lane 5 GHz SerDes 64-bit DDR-3 Memory Controller PAMU Real Time Debug Watchpoint Cross Trigger Perf Monitor Aurora CoreNet Trace 2x e5500 Power Architecture 2x 64-bit cores (up to 2.2 GHz) with 512 KB backside L2 cache Dual 1MB Shared L3 Cache w/ecc Memory Controller Dual 32/64bit DDR3/3L w/ecc up to 1.3 GHz Ethernet 5 x 10/100/1000 Ethernet controllers 1 x 10GE controller (XAUI) High Speed Interconnect 4 PCI Express (PCIe) 2.0 controllers 2 Serial RapidIO (SRIO) controllers 2 SATA 3Gb/s 2 USB 2.0 with PHY CoreNet Switch Fabric Trusted Architecture Data Path Acceleration Architecture Security Engine (SEC) Pattern Matching Engine (PME) Device RAID 5/6 Engine Enhanced RapidIO Messaging (Rman) 45nm SOI Process 1295-pin package: Pin compatible with P4080 and P

29 GbE I/O Zone RAID 5 Benchmark NAND/NOR P1022 >92 MB/s read (w/headroom) P1013 >90 MB/s read DIU Security SD Advanced Power Management e500 Core 32 kb I-cache DDR3 DDR3 P1022 Dual Core 32 kb D-cache 256 KB L2 e500 Core 32 kb 32 kb I-cache D-cache Flash RGMII RGMII Boot from support WAN GbE PHY LAN GbE PHY USB2.0 NTFS/FAT32 Support SATA esata Hard Disk PCI-e 4 lanes SATA Expander x4 RAID WLAN 11n QorIQ Value Propositions: Great NAS performance Competitively priced Low power Single-chip solution Options Highly integrated I/O & acceleration blocks Best HW & SW scaling 29

30 Hardware: F 10G Patch Cable XAUI P5040/20 A P5020DS (2.0GHz / 1333MT/s) LSI SAS RAID card Seagate 600GB SAS Drive HP Server w/ 10G NIC Intel 10GE Ethernet Card HP ProLiant G6 Tower Server PCIe x4 to SAS PCIe x4 to SAS 4x SAS Drives - 6 Gbps/Drive Software: Client PC Software: Linux 64 Bit Ubuntu Workload: Open-iSCSI with RAID5 iscsi SAS drives Benchmark: IOmeter 30

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