LNBP10 SERIES LNBP20 LNB SUPPLY AND CONTROL VOLTAGE REGULATOR (PARALLEL INTERFACE)

Transcription

1 LNBP0 SERIES LNBP20 LNB SUPPLY AND CONTROL VOLTAGE REGULATOR (PARALLEL INTERFACE) COMPLETE INTERFACE FOR TWO LNBs REMOTE SUPPLY AND CONTROL LNB SELECTION AND STAND-BY FUNCTION BUILT-IN TONE OSCILLATOR FACTORY TRIMMED AT 22KHz FAST OSCILLATOR START-UP FACILITATES DiSEqC ENCODING TWO SUPPLY INPUTS FOR LOWEST DISSIPATION BYPASS FUNCTION FOR SLAVE OPERATION LNB SHORT CIRCUIT PROTECTION AND DIAGNOSTIC AUXILIARY MODULATION INPUT EXTENDS FLEXIBILITY CABLE LENGTH COMPENSATION INTERNAL OVER TEMPERATURE PROTECTION BACKWARD CURRENT PROTECTION Multiwatt-5 0 PowerSo-20 PowerSO-0 DESCRIPTION Intended for analog and digital satellite receivers, the LNBP is a monolithic linear voltage regulator, assembled in Multiwatt-5, PowerSO-20 and PowerSO-0, specifically designed to provide the powering voltages and the interfacing signals to the LNB downconverter situated in the antenna via the coaxial cable. Since most satellite receivers have two antenna ports, the output voltage of the regulator is available at one of two logic-selectable output pins (LNBA, LNBB). When the IC is powered and put in Stand-by (EN pin LOW), both regulator outputs are disabled to allow the antenna downconverters to be supplied/controlled by others satellite receivers sharing the same coaxial lines. In this occurrence the device will limit at 3 ma (max) the backward current that could flow from LNBA and LNBB output pins to GND. For slave operation in single dish, dual receiver systems, the bypass function is implemented by an electronic switch between the Master Input pin (MI) and the LNBA pin, thus leaving all LNB powering and control functions to the Master Receiver. This electronic switch is closed when the device is powered and EN pin is LOW. The regulator outputs can be logic controlled to be 3 or 8 V (typ.) by mean of the VSEL pin for remote controlling of LNBs. Additionally, it is possible to increment by V (typ.) the selected voltage value to compensate the excess voltage drop along the coaxial cable (LLC pin HIGH). In order to reduce the power dissipation of the device when the lowest output voltage is selected, the regulator has two Supply Input pins VCC and VCC2. They must be powered respectively at 6V (min) and 23V (min), and an internal switch automatically will select the suitable supply pin according to the selected output voltage. If adequate heatsink is provided and higher power losses are acceptable, both supply pins can be powered by the same 23V source without affecting any other circuit performance. The ENT (Tone Enable) pin activates the internal oscillator so that the DC output is modulated by a ±0.3 V, 22KHz (typ.) square wave. This internal oscillator is factory trimmed within a tolerance of ±2KHz, thus no further adjustments neither external components are required. A burst coding of the 22KHz tone can be September 998 /8

2 accomplished thanks to the fast response of the ENT input and the prompt oscillator start-up. This helps designers who want to implement the DiSEqC protocols (*). In order to improve design flexibility and to allow implementation of newcoming LNB remote control standards, an analogic modulation input pin is available (EXTM). An appropriate DC blocking capacitor must be used to couple the modulating signal source to the EXTM pin. When external modulation is not used, the relevant pin can be left open. Two pins are dedicated to the overcurrent protection/monitoring: CEXT and OLF. The overcurrent protection circuit works dynamically: as soon as an overload is detected in either LNB output, the output is shut-down for a time Toff determined by the capacitor connected between CEXT and GND. Simultaneously the OLF pin, that is an open collector diagnostic output flag, from HIGH IMPEDANCE state goes LOW. After the time has elapsed, the output is resumed for a time t on =/5t off (typ.) and OLF goes in HIGH IMPEDANCE. If the overload is still present, the protection circuit will cycle again through toff and t on until the overload is removed. Typical t on +t off value is 200ms when a.7µf external capacitor is used. This dynamic operation can greatly reduce the power dissipation in short circuit condition, still ensuring excellent power-on start up even with highly capacitive loads on LNB outputs. The device is packaged in Multiwatt5 for thru-holes mounting and in PowerSO-20 for surface mounting. When a limited functionality in a smaller package matches design needs, a range of cost-effective PowerSO-0 solutions is also offered. All versions have built-in thermal protection against overheatingdamage. (*): External components are needed to comply to level 2.x and above (bidirectional) DiSEqC bus hardware requirements. DiSEqC is a trademark of EUTELSAT. ORDERING NUMBERS Type Multiwatt-5 PowerSO-20 PowerSO-0 LNBP0 LNBP LNBP2 LNBP3 LNBP LNBP5 LNBP6 LNBP20 LNBP20CR LNBP20PD LNBP0SP LNBPSP LNBP2SP LNBP3SP LNBPSP LNBP5SP LNBP6SP PIN CONFIGURATIONS Multiwatt-5 PowerSO-20 PowerSO-0 2/8

3 TABLE A: PIN CONFIGURATIONS SYMBOL NAME FUNCTION PIN NUMBER vs SALES TYPE (LNBP) 20CR 20PD 0SP SP 2SP 3SP SP 5SP 6SP VCC Supply Input 5V to 25V supply. It is automatically selected when VOUT =3orV V CC2 Supply Input 2 22V to 25V supply. It is automatically selected when V OUT =8or9V LNBA Output Port See truth tables for voltage and port selection. In stand-by mode this port is powered by the MI pin via the internal Bypass Switch VSEL Output Voltage Selection: 3 or 8V (typ) Logic control input: See truth table EN Port Enable Logic control input: See truth table OSEL Port Selection Logic control input: See truth table GND Ground Circuit Ground. It is internally connected to the die frame ENT 22 KHz Tone Enable Logic control input: See truth table CEXT External Capacitor Timing capacitor used by the Dynamic Overload Protection. Typical application is.7 µffora 200 ms cycle EXTM LLC External Modulation Line Length Compens. (V typ) External Modulation Input. Needs DC decoupling to the AC source. If not used, can be left open. Logic control input: See truth table OLF Over Load Flag Logic output (open Collector). Normally in HIGH IMPEDANCE, goes LOW when current or thermal overload occurs. MI Master Input In stand-by mode, the voltage on MI is routed to LNBA pin. Can be left open if bypass function is not needed NA NA NA NA NA NA NA NA NA 9 NA NA NA 9 NA 9 NA NA 9 NA NA 0 0 NA 8 NA NA NA NA LNBB Output Port See truth tables for voltage NA NA NA NA NA NA and port selection. NOTE: The limited pin availability of the PowerSO-0 package leads to drop some functions. 3/8

4 ABSOLUTE MAXIMUM RATING Symbol Parameter Value Unit Vi DC Input Voltage (VCC, VCC2, MI) 28 V I o Output Current (LNBA, LNBB) Internally limited Vi Logic Input Voltage (ENT, EN, OSEL, VSEL, LLC) -0.5 to 7 V I SW Bypass Switch Current 900 ma Ptot Power Dissipation at Tcase <85 o C W T stg Storage Temperature Range - 0 to 50 o C T op Operating Junction Temperature Range - 0 to 25 o C Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied THERMAL DATA Symbol Parameter Value Unit R thj-case Thermal Resistance Junction-case 2 o C/W LOGIC CONTROLS TRUTH TABLES Control I/O Pin Name L H OUT OLF IOUT >IOMAX or Tj >50 O C IOUT <IOMAX IN ENT 22KHz tone OFF 22KHz tone ON IN EN See table below See table below IN OSEL See table below See table below IN VSEL See table below See table below IN LLC See table below See table below EN OSEL VSEL LLCP VLNBA VLNBB L X X X VMI -0.V (typ.) Disabled H L L L 3V (typ.) Disabled H L H L 8V (typ.) Disabled H L L H V (typ.) Disabled H L H H 9V (typ.) Disabled H H L L Disabled 3V (typ.) H H H L Disabled 8V (typ.) H H L H Disabled V (typ.) H H H H Disabled 9V (typ.) NOTE: All logic input pins have internal pull-down resistor (typ. = 250KΩ) /8

5 BLOCK DIAGRAM 5/8

6 ELECTRICAL CHARACTERISTICS FOR LNBP SERIES (T j = 0 to 85 o C, C i = 0.22 µf, C o = 0. µf, EN=H, ENT=L, LLC= L, VIN = 6V, VIN2 = 23V, IOUT = 50mA, (unless otherwise specified) Symbol Parameter Test Conditions Min. Typ. Max. Unit V IN V CC Supply Voltage I O = 500mA, ENT=H, VSEL=L, LLC=L I O = 500mA, ENT=H, VSEL=L, LLC=H V IN2 V CC2 Supply Voltage I O = 500mA, ENT=VSEL=H, LLC=L IO = 500mA, ENT=VSEL=H, LLC=H VO Output Voltage IO = 500 ma, VSEL=H, LLC=L I O = 500 ma, VSEL=H, LLC=H VO2 Output Voltage IO = 500 ma, VSEL=L, LLC=L I O = 500 ma, VSEL=L, LLC=H V O Line Regulation V IN =5to8V, V OUT =3V VIN2 =22to25V, VOUT =8V V O Load Regulation V IN =V IN2 =22V, V OUT = 3 or 8V, IO =50to500mA V V V V 8.7 V V 3.5 V V 0 0 mv mv mv SVR Supply Voltage Rejection V IN =V IN2 =23±0.5V ac, f ac = 50 KHz 5 db IMAX Output Current Limiting ma toff Dynamic Overload Protection Output shorted, CEXT =.7µF 00 ms OFF Time ton Dynamic Overload Protection Output shorted, CEXT =.7µF toff/5 ms ON Time FTONE Tone Frequency ENT=H KHz A TONE Tone Amplitude ENT=H Vpp DTONE Tone Duty Cucle ENT=H % tr, tf Tone Rise or Fall Time ENT=H µs GEXTM External Modulation Gain VOUT/ VEXTM, f = 0Hz to 0KHz 5 V EXTM External Modulation Input Voltage AC Coupling 00 mv pp Z EXTM External Modulation f = 0Hz to 0KHz 00 Ω Impedance VSW Bypass Switch Voltage Drop EN=L, ISW= 300mA, VCC2-VMI =V V (MI to LNBA) V OL Overload Flag Pin Logic Low I OL = 8mA V I OZ Overload Flag Pin OFF State V OH =6V 0 µa Leakage Current V IL Control Input Pin Logic Low 0.8 V VIH Control Input Pin Logic High 2.5 V IIH Control Pins Input Current VIH =5V 20 µa ICC Supply Current Outputs Disabled (EN=L) 0. 3 ma I CC Supply Current ENT=H, I OUT = 500 ma 3. 6 ma I OBK Output Backward Current EN=L, V LNBA =V LNBB = 8V ma VIN = VIN2 = 22V or floating T SHDN Thermal Shutdown Threshold 50 o C 6/8

7 TYPICAL PERFORMANCE CHARACTERISTICS (unless otherwise specified T j =25 o C) Output Voltage vs Output Current Tone Frequency vs Temperature Tone Duty Cycle vs Temperature Tone Rise Time vs Temperature Tone Fall Time vs Temperature Tone Amplitude vs Temperature 7/8

8 TYPICAL PERFORMANCE CHARACTERISTICS (continued) S.V.R. vs Frequency LNBA External Modulation Gain vs Frequency External Modulation vs Temperature Bypass Switch Drop vs Output Current Bypass Switch Drop vs Output Current Overload Flag pin Logic Low vs Flag Current 8/8

9 TYPICAL PERFORMANCE CHARACTERISTICS (continued) Supply Current vs Temperature Supply Current vs Temperature Dynamic Overload protection (I SC vs Time) Tone Enable Tone Disable 22 KHz Tone 9/8

10 TYPICAL PERFORMANCE CHARACTERISTICS (continued) Enable Time Disable Time 8V to 3V Change 3V to 8V Change 0/8

11 TYPICAL APPLICATION SCHEMATICS TWO ANTENNA PORTS RECEIVER MCU+V 7V 2V AUX DATA 0uF C2 R EXTM VCC VCC2 2 ANT CONNECTORS JA 7K 3 OLF LNBA 3 LNBB 5 MI JB 9 VSEL 5 ENT 7 EN OSEL 2 LLC LNBP20CR CEXT 0.7µF C C3 C C5 C6 + GND 8 2x 0.µF 2x 7nF TUNER Vcc MCU SINGLE ANTENNA RECEIVER WITH MASTER RECEIVER PORT MCU+V 7V 2V 0uF AUX DATA C2 R EXTM VCC VCC2 2 ANT 7K 3 OLF LNBA LNBB MI 3 5 MASTER VSEL ENT EN OSEL LLC LNBP20CR 0 CEXT.7µF GND 8 C + C3 C 2x 0.µF C5 7nF TUNER Vcc MCU /8

12 TYPICAL APPLICATION SCHEMATICS (continued) USING SERIAL BUS TO SAVE MPU MCU+V R 7K AUX DATA C2 0uF 3 EXTM OLF VCC VCC2 2 LNBA 3 LNBB 5 MI 7V 2V ANT CONNECTORS JA JB STR D CLK OE Q Q2 Q3 Q Q5 Q6 Q7 Q VSEL ENT EN OSEL LLC LNBP20CR CEXT GND 8 0.7µF C + C3 2x 0.µF C C5 2x 7nF C6 TUNER QS QS SERIAL BUS MCU+V Vcc MCU TWO ANTENNA PORTS RECEIVER: LOW COST SOLUTION 7V 2V VCC VCC2 LNBA LNBB ANT CONNECTORS JA JB MCU+V VSEL ENT EN OSEL LNBP0SP CEXT GND 8.7µF C C3 C C5 C x 0.µF 2x 7nF TUNER Vcc MCU 2/8

13 TYPICAL APPLICATION SCHEMATICS (continued) CONNECTING TOGETHER VCC AND VCC2 2V VCC VCC2 2 ANT CONNECTORS JA LNBA 3 LNBB 0 JB VSEL ENT EN OSEL CEXT 8 GND 6.7µF C + C C5 C6 TUNER MCU+V LNBP0SP 0.µF 2x 7nF Vcc MCU SINGLE ANTENNA RECEIVER WITH MASTER RECEIVER PORT: LOW COST SOLUTION 7V 2V C2 AUX DATA 0µF 9 EXTM VCC VCC2 LNBA 2 3 ANT MCU+V 7 5 VSEL ENT EN LNBP3SP 0 MI 8 CEXT.7µF GND 6 C + C3 2x 0.µF C C5 7nF TUNER MASTER Vcc MCU 3/8

14 TYPICAL APPLICATION SCHEMATICS (continued) SINGLE ANTENNA RECEIVER WITH OVERLOAD DIAGNOSTIC MCU+V C2 7V 2V AUX DATA R 7K 0µF 9 0 EXTM OLF VCC 2 VCC2 LNBA 3 ANT 7 VSEL 5 ENT EN CEXT 8.7µF C + C3 C C5 TUNER LNBP5SP GND 6 2x 0.µF 7nF Vcc MCU /8

15 MULTIWATT-5 MECHANICAL DATA DIM. mm inch MIN. TYP. MAX. MIN. TYP. MAX. A B C D E F G G H H L L L L L L M M S S Dia /8

16 PowerSO-20 MECHANICAL DATA DIM. mm inch MIN. TYP. MAX. MIN. TYP. MAX. A a a a b c D () E e e E () E G h L N 0 o (max.) S 8 o (max.) T () D and E do not include mold flash or protusions - Mold flash or protusions shall not exceed 0.5mm (0.006 ) N N R a2 A c b DETAILA e3 e DETAILB E a D lead DETAILA 20 a3 slug DETAILB E2 T E Gage Plane C- S L SEATING PLANE G C 0 (COPLANARITY) hx5 PSO20MEC /8

17 PowerSO-0 MECHANICAL DATA DIM. mm inch MIN. TYP. MAX. MIN. TYP. MAX. A A B c D D E E E E E e F H h L q α 0 o 8 o B 0.0 A B 0 6 H = = E = = E2 = = E3 = = E = = E = = 5 SEATING PLANE e B DETAIL A A 0.25 M D Q C A h = D= = = SEATING PLANE F A A DETAIL A L α C 7/8

18 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a trademark of STMicroelectronics 998 STMicroelectronics Printed in Italy All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - France - Germany - Italy - Japan - Korea - Malaysia - Malta - Mexico - Morocco - The Netherlands - Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A.. 8/8