Curriculum Vitae Stijn Eyerman

Transcription

1 Curriculum Vitae Stijn Eyerman PERSONAL DETAILS Dr. ir. Stijn Eyerman Born June 12, 1981 in Ghent, Belgium Home address: Buntstraat Evergem Belgium Cell phone: Work address: Universiteit Gent Vakgroep Elektronica en Informatiesystemen (EA06) Sint-Pietersnieuwstraat Gent Belgium Phone: Fax: [email protected] EDUCATION Master level Title of degree at master level: Computer Science Engineer Burgerlijk ingenieur in de computerwetenschappen Grade obtained: Maxima cum laude Grootste onderscheiding Institution: Ghent University Year: 2004 PhD Title of the dissertation: Supervisor: University: Analytische prestatieanalyse en modellering van superscalaire en meerdradige processors. Analytical Performance Analysis and Modeling of Superscalar and Multi- Threaded Processors Prof. dr. ir. Lieven Eeckhout Ghent University Date awarded: May 8, 2008 Other degrees/diplomas Title of degree or diploma Institution Year Basic Lecturer Training Ghent University 2010 English for Lecturers Ghent University 2012

2 FULL CAREER Function Institution or employer from to FWO PhD Fellow Ghent University / Research 1/10/ /9/2008 Foundation Flanders (FWO) FWO Postdoctoral Fellow Ghent University / Research 1/10/ /9/2014 Foundation Flanders (FWO) Postdoctoral Researcher Ghent University / EU FP7 ADEPT project 1/10/ /8/2016 TEACHING Institution Duration Subject; course title Ghent University Teaching Assistant Basic Computer Architecture (lab sessions) Ghent University present Teaching Assistant Advanced Computer Architecture (project coach and teaching exercises) ACADEMIC HONOURS AND DISTINCTIONS, AWARDS, PRIZES 2 papers selected for IEEE Micro Top Picks (2006 and 2009), as one of the most significant research publications in computer architecture based on novelty and industry relevance. HiPEAC technology transfer award for Sniper, a multicore simulator based on my work. Value: 1, HiPEAC paper awards (1 in 2009, 3 in 2010, 1 in 2012, 1 in 2013 and 1 in 2014). Value: 1,000 (only once). 2 best paper nominations at ISPASS 2012 and ISPASS 2015 INTERNATIONAL EXPERIENCE April 22, 2014 May 28, 2014: Research stay at INRIA Rennes, France (group of André Seznec) March 23, 2015 June 26, 2015: Host for a visiting PhD student: Josué Feliu Peréz from the University of Valencia From August 2015: co-supervision of the PhD of Runar B. Olsen from NTNU (Norway) Several international research collaborations leading to multiple publications: o University of Wisconsin: Jim Smith and Tejas Karkhanis (4 papers) o University of Texas at Austin: Lizy John and Arun Nair (2 papers) o INRIA Saclay, France and ICT, Beijing, China: Olivier Temam, Zheng Li, Yang Chen and Chengyong Wu (1 paper) o INRIA Rennes, France: Pierre Michaud (2 papers) Maximilien Breughe (a PhD student I have advised) has done a 1-year internship at Samsung in Austin, Texas.

3 PUBLICATIONS Journal publications 1. Arun Nair, Stijn Eyerman, Lieven Eeckhout, Lizy John, Jian Chen, Mechanistic Modeling of Architectural Vulnerability Factor, ACM Transactions on Computer Systems, Vol. 32, issue 4, January (impact factor 0.615) 2. Maximilien Breughe, Stijn Eyerman, Lieven Eeckhout, Mechanistic Analytical Modeling of Superscalar In-Order Processor Performance, ACM Transactions on Architecture and Code Optimization, vol. 11, issue 4, article 50, January (impact factor 0.597) 3. Stijn Eyerman, Pierre Michaud, Wouter Rogiest, Multi-Program Throughput Metrics: a Systematic Approach, ACM Transactions on Architecture and Code Optimization, vol. 11, issue 3, article 34, September (impact factor 0.597) 4. Trevor Carlson, Wim Heirman, Stijn Eyerman, Ibrahim Hur, Lieven Eeckhout, An Evaluation of High-Level Mechanistic Core Models, ACM Transactions on Architecture and Code Optimization, vol. 11, issue 3, article 28, September (impact factor 0.597) 5. Stijn Eyerman, Lieven Eeckhout, Restating the Case for Weighted-IPC Metrics to Evaluate Multiprogram Workload Performance, IEEE Computer Architecture Letters, published online, 2013 (impact factor: 0.852). 6. Kristof Du Bois, Stijn Eyerman, Lieven Eeckhout, Per-Thread Cycle Accounting in Multi-Core Processors, ACM Transactions on Architecture and Code Optimization, vol. 9, issue 1, article 1, 29 pages, January (impact factor 0.568) 7. Stijn Eyerman, Lieven Eeckhout, Probabilistic Modeling for Job Symbiosis Scheduling on SMT Processors, ACM Transactions on Architecture and Code Optimization, vol. 9, issue 2, article 7, 27 pages, June (impact factor 0.568) 8. Stijn Eyerman, Lieven Eeckhout, Fine-Grained DVFS Using On-Chip Regulators, ACM Transactions on Architecture and Code Optimization, vol. 8, issue 1, article 1, 24 pages, April (impact factor 0.568) 9. Stijn Eyerman, Lieven Eeckhout, A Counter Architecture for Online DVFS Profitability Estimation, IEEE Transactions on Computers, vol. 59, issue 11, pp , November (impact factor 1.103) 10. Stijn Eyerman, Lieven Eeckhout, Probabilistic Job Symbiosis Modeling for SMT Processor Scheduling, ACM Sigplan Notices, vol. 45, issue 3, pp , March (impact factor 0.090) 11. Stijn Eyerman, Lieven Eeckhout, Per-thread Cycle Accounting, IEEE Micro, vol. 30, issue 1, pp , January (impact factor 2.527) 12. Stijn Eyerman, Lieven Eeckhout, Tejas Karkhanis, James E. Smith, A Mechanistic Performance Model for Superscalar Out-of-Order Processors, ACM Transactions on Computer Systems, vol. 27, issue 2, article 3, 37 pages, May (impact factor 2.381) 13. Stijn Eyerman, Lieven Eeckhout, Memory-Level Parallelism Aware Fetch Policies for Simultaneous Multithreading Processors, ACM Transactions on Architecture and Code Optimization, vol. 6, issue 1, article 3, 33 pages, March (impact factor 0.595) 14. Stijn Eyerman, Lieven Eeckhout, Per-Thread Cycle Accounting in SMT Processors, ACM Sigplan Notices, vol. 44, issue 3, pp , March (impact factor 0.280) 15. Stijn Eyerman, Lieven Eeckhout, System-Level Performance Metrics for Multiprogram Workloads, IEEE Micro, vol. 28, issue 3, pp , May (impact factor 2.565) 16. Stijn Eyerman, Lieven Eeckhout, Tejas Karkhanis, James E. Smith, A Top-Down Approach to Architecting CPI Component Performance Counters, IEEE Micro, vol. 27, issue 1, pp , January (impact factor 1.701) 17. Stijn Eyerman, Lieven Eeckhout, Tejas Karkhanis, James E. Smith, A Performance Counter Architecture for Computing Accurate CPI Components, ACM Sigplan Notices, vol. 44, issue 3, pp , November (impact factor 0.108)

4 Conference papers mentioned in ISI Web of Science 1. Stijn Eyerman, Lieven Eeckhout, The Benefit of SMT in the Multi-Core Era: Flexibility towards Degrees of Thread-Level Parallelism, in Proceedings of the 19th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), pp , Kristof Du Bois, Jennifer B Sartor, Stijn Eyerman, Lieven Eeckhout, Bottle graphs: visualizing scalability bottlenecks in multi-threaded applications, in Proceedings of the 2013 ACM SIGPLAN international conference on Object oriented programming systems languages & applications (OOPSLA), pp , Kristof Du Bois, Stijn Eyerman, Jennifer Sartor, Lieven Eeckhout, Criticality Stacks: Identifying Critical Threads in Parallel Programs using Synchronization Behavior, in Proceedings of 40th International Symposium on Computer Architecture (ISCA 2013), pp., Arun Nair, Stijn Eyerman, Lieven Eeckhout, Lizy K. John, A First-Order Mechanistic Model for Architectural Vulnerability Factor 39 th Annual International Symposium on Computer Architecture (ISCA 2012), pp , Stijn Eyerman, Lieven Eeckhout, Probabilistic Job Symbiosis Modeling for SMT Processor Scheduling, 15 th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS 2010), pp , Davy Genbrugge, Stijn Eyerman, Lieven Eeckhout, Interval Simulation: Raising the Level of Abstraction in Architectural Simulation, 16 th International Symposium on High Performance Computer Architecture (HPCA 2010), pp , Stijn Eyerman, Lieven Eeckhout, Modeling Critical Sections in Amdahl's Law and its Implications for Multicore Design, 37 th Annual International Symposium on Computer Architecture (ISCA 2010), pp , Kenzo Van Craeynest, Stijn Eyerman, Lieven Eeckhout, MLP-Aware Runahead Threads in a Simultaneous Multithreading Processor, 4 th International Conference on High Performance Embedded Architectures and Compilers (HiPEAC 2009), pp , Stijn Eyerman, Lieven Eeckhout, Studying Compiler Optimizations on Superscalar Processors through Interval Analysis, 3 rd International Conference on High Performance Embedded Architectures and Compilers (HiPEAC 2008), pp , Stijn Eyerman, Lieven Eeckhout, A Memory-Level Parallelism Aware Fetch Policy for SMT Processors, 13 th International Symposium on High Performance Computer Architecture (HPCA 2007), pp , Stijn Eyerman, James E. Smith, Lieven Eeckhout, Characterizing the Branch Misprediction Penalty, IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS 2006), pp , Stijn Eyerman, Lieven Eeckhout, Efficient Design Space Exploration of High Performance Embedded Out-of-Order Processors, Design, Automation and Test in Europe Conference and Exhibition (DATE 06), pp , Stijn Eyerman, Lieven Eeckhout, Koen De Bosschere, The Shape of the Processor Design Space and its Implications for Early Stage Explorations, 7 th International Conference on Automatic Control, Modeling and Simulation, pp , Other conference papers 1. Stijn Eyerman, Pierre Michaud, Wouter Rogiest, Revisiting Symbiotic Job Scheduling, IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS 2015), pp. xx-yy, 2015.

5 2. Sander De Pestel, Stijn Eyerman, Lieven Eeckhout, Micro-architecture Independent Branch Behavior Characterization, IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS 2015), pp. xx-yy, Sam Van den Steen, Sander De Pestel, Moncef Mechri, Stijn Eyerman, Trevor Carlson, David Black-Schaffer, Erik Hagersten, Lieven Eeckhout, Micro-architecture Independent Analytical Processor Performance and Power Modeling, IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS 2015), pp. xx-yy, Osman Allam, Stijn Eyerman, Lieven Eeckhout, An Efficient CPI Stack Counter Architecture for Superscalar Processors, The Great Lakes Symposium on VLSI (GLS-VLSI 2012), pp , Maximilien Breughe, Stijn Eyerman, Lieven Eeckhout, A Mechanistic Performance Model for Superscalar In-Order Processors, IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS 2012), pp , Stijn Eyerman, Kristof Du Bois, Lieven Eeckhout, Speedup Stacks: Identifying Scaling Bottlenecks in Multi-Threaded Applications, IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS 2012), pp , Maximilien Breughe, Zheng Li, Yang Chen, Stijn Eyerman, Olivier Temam, Chengyong Wu, Lieven Eeckhout, How Sensitive is Processor Customization to the Workload's Input Datasets?, IEEE 9th Symposium on Application Specific Processors (SASP 2011), pp. 1-7, Stijn Eyerman, Kenneth Hoste, Lieven Eeckhout, Mechanistic-Empirical Processor Performance Modeling for Constructing CPI Stacks on Real Hardware, IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS 2011), pp , Stijn Eyerman, Lieven Eeckhout, James E. Smith, Studying Compiler-Microarchitecture Interactions through Interval Analysis, 16th International Conference on Parallel Architecture and Compilation Techniques (PACT 2007), p. 406, Lieven Eeckhout, Stijn Eyerman, Bert Callens, Koen De Bosschere, Accurately Warmed-up Trace Samples for the Evaluation of Cache Memories, The High Performance Computing Symposium (HPC2003), pp , 2003 Patents 1. Lieven Eeckhout, Stijn Eyerman, Wim Heirman, Trevor Carlson, Instruction window centric processor simulation, filed June 17, 2012 as U.S. Provisional, Application Number: 61/ Trevor Carlson, Wim Heirman, Stijn Eyerman, Lieven Eeckhout, Issue Contention modeling for interval simulation, filed June 17, 2012 as U.S. Provisional, Application Number: 61/ Trevor Carlson, Wim Heirman, Stijn Eyerman, Lieven Eeckhout, Osman Allam, Interval simulation with cycle level memory hierarchy support, filed June 17, 2012 as U.S. Provisional, Application Number: 61/ Lieven Eeckhout, Stijn Eyerman, A Counter Architecture for Online DVFS Profitability Estimation, filed Dec. 10, 2010 as U.S. Patent, Application Number: 13/516,850, granted Aug. 19, 2014 as US Patent B2. 5. Lieven Eeckhout, Stijn Eyerman, Davy Genbrugge, Methods and Systems for Simulating a Processor, filed June 1, 2010 as U.S. Patent, Application Number: 12/791,306, published Dec. 1, 2011.

6 Presentations at international conferences 1. Revisiting Symbiotic Job Scheduling, Stijn Eyerman, Pierre Michaud, Wouter Rogiest, IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS 2015), Philadelphia, USA, April Paper presentation. 2. Multiprogram Throughput Metrics: a Systematic Approach, Stijn Eyerman, Pierre Michaud, Wouter Rogiest, HiPEAC 2015 Conference, Amsterdam, January Paper presentation. 3. Speedup Stacks: Identifying Scaling Bottlenecks in Multi-Threaded Applications, Stijn Eyerman, Kristof Du Bois, Lieven Eeckhout, IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS 2012), New Brunswick, NJ, USA, 1-3 April Paper presentation. 4. Mechanistic-Empirical Processor Performance Modeling for Constructing CPI Stacks on Real Hardware, Stijn Eyerman, Kenneth Hoste, Lieven Eeckhout, IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS 2011), Austin, TX, USA, April Paper presentation. 5. Probabilistic Job Symbiosis Modeling for SMT Processor Scheduling, Stijn Eyerman, Lieven Eeckhout, 15 th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS 2010), Pittsburgh, PA, USA, March Paper presentation. 6. Studying Compiler Optimizations on Superscalar Processors through Interval Analysis, Stijn Eyerman, Lieven Eeckhout, 3 rd International Conference on High Performance Embedded Architectures and Compilers (HiPEAC 2008), Göteborg, Sweden, January Paper presentation. 7. Studying Compiler-Microarchitecture Interactions through Interval Analysis, Stijn Eyerman, Lieven Eeckhout, James E. Smith, 16th International Conference on Parallel Architecture and Compilation Techniques (PACT 2007), Brasov, Romania, September Poster presentation. 8. A Memory-Level Parallelism Aware Fetch Policy for SMT Processors, Stijn Eyerman, Lieven Eeckhout, 13 th International Symposium on High Performance Computer Architecture (HPCA 2007), Phoenix, AZ, USA, February Paper presentation. 9. Characterizing the Branch Misprediction Penalty, Stijn Eyerman, James E. Smith, Lieven Eeckhout, IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS 2006), Austin, TX, USA, March Paper presentation. 10. Efficient Design Space Exploration of High Performance Embedded Out-of-Order Processors, Stijn Eyerman, Lieven Eeckhout, Design, Automation and Test in Europe Conference and Exhibition (DATE 06), München, Germany, March Paper presentation. 11. The Shape of the Processor Design Space and its Implications for Early Stage Explorations, Stijn Eyerman, Lieven Eeckhout, Koen De Bosschere, 7 th International Conference on Automatic Control, Modeling and Simulation, Prague, Czechia, March Paper presentation. Obtained research funding 1. Collaboration Grant (Spanish government) for Josué Feliu, PhD student at the University of Valencia (costs of a 3-month research stay at Ghent University), March-June IWT PhD scholarship of Sam Van den Steen, (advisor) 3. IWT PhD scholarship of Sander De Pestel, (advisor) 4. IOF StartTT project, Ghent University, 75, Postdoctoral Fellow FWO, extension, , FWO-Flanders. 6. Postdoctoral Fellow FWO, , FWO-Flanders 7. PhD Fellow FWO, extension, , FWO- Flanders. 8. PhD Fellow FWO, , FWO- Flanders.

7 Master theses and doctoral dissertations supervising Master students 1. Kenzo Van Craeynest, Optimaliseren van geheugenparallellisme in een SMT processor, academiejaar Bart Minnaert, Analytische prestatiemodellering van DRAM-geheugen, academiejaar Maarten Heyse, Nauwkeurige on-the-fly prestatie-analyse van multi-core processors, academiejaar Stijn Souffriau, Simulatie van many-core processors, academiejaar Jeroen Rommens, Dynamische migratie van virtuele machines in een heterogeen datacenter, academiejaar PhD students 1. Maximilien Breughe (graduated December 2014) 2. Kristof Du Bois (graduated June 2014) 3. Sam Van den Steen (2nd year PhD student) 4. Sander De Pestel (2nd year PhD student) 5. Mutaz Adileh (2nd year PhD student) Member of PhD jury Stijn Polfliet, Characterization and Synthesis of Data Center Workload Optimization, supervisor Lieven Eeckhout, graduated in April Trevor Carlson, Speeding Up Architectural Simulation through High-Level Core Abstractions and Sampling, supervisor Lieven Eeckhout, graduated in May Kristof Du Bois, Performance Analysis Methods for Understanding Scaling Bottlenecks in Multi-Threaded Applications, supervisors Lieven Eeckhout and Stijn Eyerman, graduated in June 2014 Maximilien Breughe, Efficient Design Space Exploration of Embedded Microprocessors, supervisors Lieven Eeckhout and Stijn Eyerman, graduated in December Program committee member 1. FastPath 2012: Workshop on Performance Modeling and Analysis of Workload Optimized Systems (April 2012) 2. IISWC 2012: IEEE International Symposium on Workload Characterization (October 2012) 3. ISPASS 2013: International Symposium on Performance Analysis of Systems and Software (April 2013) 4. ICPP 2013: International Conference on Parallel Processing (October 2013) 5. DATE 2014: Design Automation and Test in Europe (March 2014) 6. ISPASS 2014: International Symposium on Performance Analysis of Systems and Software (March 2014) 7. HPCA 2015: International Symposium on High Performance Computer Architecture (February 2015) 8. ISPASS 2015: International Symposium on Performance Analysis of Systems and Software (March 2015) 9. CLUSTER 2015: IEEE International Conference on Cluster Computing (September 2015)

8 10. APPT 2015: International Conference on Advanced Parallel Processing Technology (August 2015) Reviewer Conferences: Euro-par 2008, DATE 2008, ISPASS 2009, FastPath 2012, IISWC 2012, MICRO 2012, ISPASS 2013, ISCA 2013, ICPP 2013, DATE 2014, ISPASS 2014, HPCA 2015, ISPASS 2015, ISCA 2015, CLUSTER 2015, APPT 2015 Journals: IEEE Transactions on Computers, ACM Transactions on Architecture and Code Optimization, Journal of Computer Science and Technology (Springer), IEEE Transactions on Parallel and Distributed Systems, Microprocessors and Microsystems (Elsevier), Journal of Parallel and Distributed Computing (Elsevier), ACM Transactions on Embedded Computing Systems, Journal of Zhejiang University Science C (Computers & Electronics) (Springer), Concurrency and Computation: Practice and Experience (Wiley), Journal of Systems Architecture (Elsevier), Parallel Processing Letters (World Scientific) Distinguished reviewer for ACM Transactions on Architecture and Code Optimization Other Best paper selection committee member for MICRO Member of IEEE and ACM