Scalable Cache Miss Handling For High MLP

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1 Scalable Cache Miss Handling For High MLP James Tuck, Luis Ceze, and Josep Torrellas University of Illinois at Urbana-Champaign

2 Introduction Checkpointed processors are promising superscalar architectures" Runahead, CPR, Out-of-order commit, CFP, CAVA Deliver high numbers of in-flight instructions" Effectively hide long memory latencies Dramatically increase Memory-Level Parallelism (MLP) Current miss handling structures are woefully under-designed! 2 of 25

3 Miss Handling Architecture (MHA) Kroft, ISCA 81 Scheurich & Dubois, SC 88 Farkas & Jouppi, ISCA 94 Cache Miss! Core = Miss Information/Status Holding Registers file Cache Primary Secondary Secondary Primary Miss Miss MHA Cache hierarchy Subentry Entry Register in processor Block offset Type (rd/wr) Data (or pointer) 3 of 25

4 Background on MHA Processor Processor Cache file Unified MHA ed MHA Kroft [ISCAʼ81] proposed first non-blocking cache" file Sohi and Franklin [ISCAʼ91]" Evaluated cache bandwidth file banked with cache 4 of 25

5 Motivation MHAs must support many more misses" Brute force approach will not do" Imbalance induced processor stall Processor Processor Cache file Unified MHA Centralized design has low bandwidth ed MHA ing may cause access imbalance (and lockup) or inefficient area usage 5 of 25

6 Proposal: Hierarchical MHA Processor A small per-bank file with Bloom filter" High bandwidth A larger, Shared file" Bloom Filter Bloom Filter Bloom Filter High effective capacity Low lock-up time Shared MHA 6 of 25

7 Contributions Show that state-of-the-art designs are a significant bottleneck" Propose a Hierarchical MHA to meet high MLP demands" Thoroughly evaluate on Checkpointed processors with SMT and show" Over state-of-the-art, avg. speed-ups of 32% to 95% Over large Unified design, avg. speed-ups of 1% to 18% Performs close to unlimited size MHA 7 of 25

8 Why not reuse load/store queue state? High MLP: need state in LSQ and in MHA" Could simplify MHA by leveraging complex LSQ " Allocate on primary miss Keep all secondary miss state in LSQ Disadvantage of leveraging LSQ" Induces additional global searches in the LSQ from the cache side Searches would use ID or line address---not word address" Some checkpointed microarchitectures speculatively retire instructions and discard LSQ state LSQ is timing critical: better not put restrictions on it We keep primary and secondary miss info in MHA and rely on no specific LSQ design " 8 of 25

9 Outline Requirements of new MHAs" Hierarchical MHA" Experimental setup and evaluation" 9 of 25

10 Requirements for the new MHAs High capacity" Checkpointed Conventional 10 of 25

11 Requirements for the new MHAs High capacity" High bandwidth" Average increase of 30% 11 of 25

12 Requirements for the new MHAs High capacity" High bandwidth" Average increase of 30% ed MHAs may suffer from access imbalance lockups" From 15% to 23% slow down Need many entries and subentries" 32 Entries (primary misses) 16 to 32 subentries (secondary misses) These are our design goals 12 of 25

13 Outline Requirements of new MHAs" Hierarchical MHA" Experimental setup and evaluation" 13 of 25

14 Hierarchical MHA Secondary miss will often hit in Dedicated file Processor Allocate in Dedicated Dedicated Bloom Filter Dedicated Bloom Filter Dedicated Bloom Filter is Full! Displace to Shared file and Bloom filter Shared MHA Bloom filter averts Shared file accesses 14 of 25

15 Hierarchical meets design goals Infrequent lock-up while using MHA area efficiently " Processor Use Shared file for displacements High bandwidth" Per-bank Dedicated file Allocate in Dedicated file Locality ensures it is in the Dedicated file" Bloom filter for Shared file Averts most useless accesses to Shared file" Prevents a bottleneck at the Shared file" Bloom Filter Bloom Filter Shared MHA Bloom Filter 15 of 25

16 Overall organization and timing Dedicated file" Small and fully pipelined Few entries and subentries Per bank Bloom filter" Accessed in parallel with Dedicated file No false negatives Shared file" Highly associative and unpipelined Contains many entries and subentries Bloom Filter Processor Bloom Filter Shared MHA Bloom Filter 16 of 25

17 Outline Requirements of new MHAs" Hierarchical MHA" Experimental setup and evaluation" 17 of 25

18 Experimental setup 5 GHz processor" 5-issue, SMT with 2 contexts" Conventional Checkpointed LargeWindow (2K entry ROB) 32 KB Data Cache" 8 banks, 2-way, 64B line, 3 cycle access, 1 port Memory bus bandwidth: 15 GB/s" Workloads: CINT, CFP, Mix" SESC simulator (sesc.sourceforge.net)" 18 of 25

19 Compare MHAs with the same area 8%, 15%, and 25% of cache area" Area estimated using CACTI 4.1 structures are fully associative Unified, ed, and Hierarchical at each area! Current: 8 misses like Pentium 4" Cache Cache Cache 8% 15% 25% MHA MHA MHA 19 of 25

20 Performance at 15% area for Checkpointed Current is much worse" Hierarchical is better than Unified and ed" 1 to 18% over Unified 10 to 21% over ed Hierarchical is very close to Unlimited" 20 of 25

21 Performance at 15% area for other processors Conventional! Less gain across the board LargeWindow! Current bottlenecks the processor Hierarchical outperforms the rest Other architectures can leverage this design" Conventional LargeWindow 21 of 25

22 Performance at different area points Speedup over ed-15% Checkpointed running Mixes" Unified saturates at 15%" ed continues to increase as it scales up" Hierarchical is most efficient for these areas" 22 of 25

23 Characterization Bloom filter averts majority of Shared file accesses" On average, from 89% to 95% Most secondary misses hit in the Dedicated file" Reasons for displacing an entry from Dedicated" No free subentries: 18% to 40% No free entries: 60% to 82% 23 of 25

24 Conclusions State-of-the-art MHA designs are a large bottleneck" Hierarchical speeds-up 32% to 95% over state-of-the-art Brute force Unified & ed designs are suboptimal" Hierarchical speeds-up 1% to 18% over Unified Hierarchical speeds-up 10% to 21% over ed Hierarchical performs best over a range of areas" Additional complexity of Hierarchical is reasonable" 24 of 25

25 Questions? Scalable Cache Miss Handling For High MLP James Tuck, Luis Ceze, and Josep Torrellas University of Illinois at Urbana-Champaign 25 of 25

Scalable Cache Miss Handling for High Memory-Level Parallelism

Scalable Cache Miss Handling for High Memory-Level Parallelism James Tuck, Luis Ceze,andJosep Torrellas University of Illinois at Urbana-Champaign {jtuck,luisceze,torrellas}@cs.uiuc.edu http://iacoma.cs.uiuc.edu