Factoring Finite State Machines

Transcription

1 Chapter 17 Factoring Finite State Machine Factoring a tate machine i the proce of plitting the machine into two or more impler machine. Factoring can greatly implify the deign of a tate machine by eparating orthogonal apect of the machine into eparate FSM where they can be handled independently. The eparate FSM communicate via logic ignal. One FSM provide input control ignal to another FSM and ene it output tatu ignal. Such factoring, if done properly, make the machine impler and alo make it eaier to undertand and maintain by eparating iue. In a factored FSM, the tate of each ub-machine repreent one dimenion of a multi-dimenional tate pace. Collectively the tate of all of the ubmachine define the tate of the overall machine a ingle point in thi tate pace. The combined machine ha a number of tate that i equal to the product of the number of tate of the individual ub-machine the number of point in the tate pace. 1 With individual ub-machine having a few 10 of tate, it i not unuual for the overall machine to have thouand to million of tate. It would be impractical to handle uch a large number of tate without factoring. We have already een one form of factoring in Section 16.3 where we developed a tate machine with a data path component and a control component. In effect we factored the total tate of the machine into a datapath portion and a control portion. Here we generalize thi concept by howing how the control portion itelf can be factored. In thi chapter we illutrate factoring by working two example. In the firt example, we tart with a flat FSM and factor it into multiple impler FSM. In the econd example we derive a factored FSM directly from the pecification, without bothering with the flat FSM. Mot real FSM are deigned uing the latter method. A factoring i uually a natural outgrowth of the pecification 1 For mot machine, not all point in the tate pace are reachable. 301

2 302 EE108A Cla Note in OFF out = 0 in A1 A2 A3 A4 A5 A6 out = 1 out = 1 out = 1 out = 1 out = 1 out = 1 B1 B2 B3 B4 out = 0 out = 0 out = 0 out = 0 C1 C2 C3 C4 C5 C6 out = 1 out = 1 out = 1 out = 1 out = 1 out = 1 D1 D2 D3 D4 out = 0 out = 0 out = 0 out = 0 E1 E2 E3 E4 E5 E6 out = 1 out = 1 out = 1 out = 1 out = 1 out = 1 Figure 17.1: State diagram for the light flaher. of a machine. It i rarely applied to an already flat machine A Light Flaher Suppoe you have been aked to deign a light flaher. The flaher ha a ingle input in and a ingle output out. Whenin goe high (for one cycle) it initiate the flahing equence. During thi equence output out, which drive a lightemitting diode (LED) flahe three time. For each flah out goe high (LED on) for ix cycle. Output out goe low for four cycle between flahe. After the third flah your FSM return to the off tate awaiting the next pule on in. A tate diagram for thi light flaher i hown in Figure The FSM contain 27 tate ix for each of the three flahe, four for each of the two period between flahe, and one OFF tate. We can implement thi FSM with a big cae tatement, with 27 cae. However, uppoe the pecification change to require 12 cycle for each flah, 4 flahe, and 7 cycle between flahe. Becaue thi machine i flat any one of thee change would require completely changing the cae tatement. We will illutrate the proce of factoring with our light flaher. Thi machine

3 Copyright (c) by W.J Dally, all right reerved 303 in done done done done done OFF in A done B done C done D done E done (a) tload= 1 tel = 1 out = 0 tload = done tel = 0 out = 1 tload = done tel = 1 out = 0 tload = done tel = 0 out = 1 tload = done tel = 1 out = 0 out = 1 in FSM out (b) tload tel done Timer tload tload tel (c) DONE tload tel T5 T4 T3 T2 T1 done = 1 done=0 done=0 done=0 done=0 done=0 Figure 17.2: State diagram for the light flaher. With on and off timing factored out into a timer. (a) State diagram of mater FSM. (b) Block diagram howing connection between mater FSM and timer FSM. (c) State diagram of timer FSM. can be factored in two way. Firt, we can factor out the counting of on and off interval into a timer. Thi allow each of the ix or four tate equence for a given flah or interval to be reduced to a ingle tate. Thi factoring of timing both implifie the machine and make it coniderably impler to change the on and off interval. Second, we can factor out the three flahe (even though the lat i lightly different). Thi again implifie the machine and alo allow u to change the number of flahe. Figure 17.2 how how the flaher i factored to eparate the proce of counting time interval into a eparate machine. A hown in Figure 17.2(b), the factored machine conit of a mater FSM that accept in and genreate out and a timer FSM. The timer FSM receive two control ignal from the mater and return a ingle tatu ignal. The tload control ignal intruct the timer to load a value into a count-down timer (i.e., to tart the timer), and tel elect the value to be loaded. When tel i high, the timer i et to count ix cycle. The counter count four cycle when tel i low. When the counter ha completed it count down the done ignal i aerted and remain aerted until the counter i reloaded. A tate diagram for thi timer i hown

4 304 EE108A Cla Note in Figure 17.2(c). 2 The timer i implemented a a datapath FSM a dicued in Section A tate diagram of the mater FSM i hown in Figure 17.2(a). The tate correpond exactly to the tate of Figure 17.1 except that each equence of repeated tate (e.g., A1 to A6) i replaced by a ingle tate (e.g., A). The machine tart in the OFF tate. Thi tate repeatedly load the timer with the count-down value for the on equence (tel = 1). When in goe true, the FSM enter tate A, out goe high, and the timer begin counting down. The mater FSM tay in tate A waiting for the timer to finih counting and ignal done. It will remain in thi tate for ix cycle. During the lat cycle in tate A, done i true, o tload i aerted (tload = done) and the counter i loaded with the count-down value for the off equence (tel = 0). Note that tload i aerted only during thi final cycle of tate A, when done i true. If it wa aerted during each cycle of tate A the timer would continually reet and never reach done. Since done i true in thi final cycle, the machine enter tate B on the next cycle and out goe low. The proce repeat in tate B through E with each tate waiting for done before moving to the next tate. Each of thee tate (except E) load the counter for the next tate during it lat cycle by pecifying tload = done. If we compare the FSM of Figure 17.2 to the flat FSM of Figure 17.1 we realize that the tate of the flat machine ha been eparated. The portion of the tate that repreent the cycle count during the current flah or pace (the numeric part of the tate name, or the horizontal poition in Figure 17.1) i held in the counter, while the portion of tate that reflect which flah or pace we are currently on (the alpha part of the tate name, or the vertical poition in Figure 17.1) i held in the mater FSM. By decompoing the tate into horizontal and vertical in thi manner, we are able to repreent all 27 tate of the original machine with jut two ix-tate machine. Verilog code for the mater FSM of Figure 17.2(a) i hown in Figure The Flah module intantiate a tate regiter and a timer (ee Figure??) and then ue a cae tatement to decribe the combinational next tate and output logic. For each of the ix tate a ingle concatenated aignment i ued to et the output ignal, out, the two timer control, tload and tel, andthenext tate next1. Note that the value aigned to timer control tload depend on the value of the timer tatu done. Thiianexampleofatatemachinewhere an input done directly affect an output tload with no delay. In each tate, the next tate i determined with a? : tatement that wait for either in or done before advancing to the next tate. A final aign tatement reet the machine to the OFF tate. For completene the verilog code for the timer i hown in Figure The approach taken i imilar to that decribed in Section The waveform diplay from a imulation of the factored flaher of Figure 17.2 i hown in Figure The output, the fourth line from the top, how the 2 Thi tate diagram only how tload being active in tate DONE. In fact, our timer can be loaded in any tate. The additional edge are omitted for clarity.

5 Copyright (c) by W.J Dally, all right reerved 305 // define tate for flah1 define SWIDTH 3 define S_OFF 3 b000 // off tate define S_A 3 b001 // firt flah define S_B 3 b010 // firt pace define S_C 3 b011 // econd flah define S_D 3 b100 // econd pace define S_E 3 b101 // third and final flah // Flah - flahe out three time 6 cycle on, 4 cycle off // each time in i aerted. module Flah(clk, rt, in, out) ; input clk, rt, in ; // in trigger tart of flah equence output out ; // out drive LED reg out ; // output wire [ SWIDTH-1:0] tate, next ; // current tate reg [ SWIDTH-1:0] next1 ; // next tate without reet reg tload, tel ; // timer input wire done ; // timer output // intantiate tate regiter DFF #( SWIDTH) tate_reg(clk, next, tate) ; // intantiate timer Timer1 timer(clk, rt, tload, tel, done) ; // next tate and output logic or rt or in or done) begin cae(tate) S_OFF: {out, tload, tel, next1} = {1 b0, 1 b1, 1 b1, in? S_A : S_OFF } ; S_A: {out, tload, tel, next1} = {1 b1, done, 1 b0, done? S_B : S_A } ; S_B: {out, tload, tel, next1} = {1 b0, done, 1 b1, done? S_C : S_B } ; S_C: {out, tload, tel, next1} = {1 b1, done, 1 b0, done? S_D : S_C } ; S_D: {out, tload, tel, next1} = {1 b0, done, 1 b1, done? S_E : S_D } ; S_E: {out, tload, tel, next1} = {1 b1, done, 1 b1, done? S_OFF : S_E } ; default:{out, tload, tel, next1} = {1 b1, done, 1 b1, done? S_OFF : S_E } ; endcae end // reet to off tate aign next = rt? S_OFF : next1 ; endmodule Figure 17.3: Verilog decription of the mater FSM from Figure 17.2(a).

6 306 EE108A Cla Note // define time interval // load 5 for 6-cycle interval 5 to 0. define T_WIDTH 3 define T_ON 3 d5 define T_OFF 3 d3 // Timer 1 - reet to done tate. Load time when tload i aerted // Load with T_ON if tel, otherwie T_OFF. If not being loaded or // reet, timer count down each cycle. Done i aerted and timing // top when counter reache 0. module Timer1(clk, rt, tload, tel, done) ; parameter n= T_WIDTH ; input clk, rt, tload, tel ; output done ; wire [n-1:0] count ; reg [n-1:0] next_count ; wire done ; // tate regiter DFF #(n) tate(clk, next_count, count) ; // ignal done aign done =!( count) ; // next count logic alway@(rt or tload or tel or done or count) begin caex({rt, tload, tel, done}) 4 b1xxx: next_count = T_WIDTH b0 ; 4 b011x: next_count = T_ON ; 4 b010x: next_count = T_OFF ; 4 b00x0: next_count = count - 1 b1 ; 4 b00x1: next_count = count ; default: next_count = count ; endcae end endmodule Figure 17.4: Verilog decription for the timer FSM ued by the light flaher of Figure 17.2.

7 Copyright (c) by W.J Dally, all right reerved 307 Figure 17.5: A waveform diplay howing a imulation of the factored light flaher of Figure 17.2.

8 308 EE108A Cla Note deired three pule with each pule ix clock wide and pace four clock wide. The tate of the mater FSM i directly below the output, and the tate of the timer i on the bottom line. The waveform how how the mater FSM tay in one tate while the timer count down from 5 to 0 for flahe, and from 3 to 0 for pace. The timer control line (directly above the timer tate) how how in tate A-E (1-5) tload follow done. We can factor our flaher further by recognizing that tate A, C, and E are repeating the ame function. The only difference i the number of remaining flahe. We can factor the number of remaing flahe out into a econd counter a hown in Figure Here the mater FSM ha only three tate that determine whether the machine i off, in a flah, or in a pace. The tate that determine the poition within a flah or pace i held in a timer (jut a in Figure Finally, the tate that determine the number of remaining flahe i held in a counter. Collectively the three FSM, the mater, the timer, and the counter, determine the total tate of the factored machine. Each of the three ub-machine determine the tate along one axi of a three-dimenional tate pace. The tate diagram of the mater FSM for the doubly factored machine i hown in Figure 17.6(b). The machine ha only three tate. It tart in the OFF tate. In the off tate, both the timer and the counter are loaded. The timer i loaded with the count-down value for a flah. The counter i loaded with one le than the number of flahe required (i.e. the counter i loaded with a 3 for 4 flahe). Having input in go high caue a tranition to the FLASH tate. In the FLASH tate the output out i true, the timer count down, and the counter i idle. During the lat cycle of the FLASH tate the timer ha reached it zero tate and tdone i true. During thi cycle the timer i reloaded with the count-down value for a pace. With tdone true, the FSM proceed from the FLASH tate to the SPACE tate if the counter i not done (cdone fale). Otherwie, if thi wa the lat flah (cdone true) the machine return to the OFF tate. In the SPACE tate, the output i fale, the timer count down, and the counter i idle. In the final cycle of the SPACE tate, tdone i true. Thi caue the counter to decrement, reducing the count of the number of remaining flahe, and the timer to reload with the count-down value for a flah. The Verilog code for the doubly factored flaher of Figure 17.6 i hown in Figure 17.7 and the Verilog decription of the counter module i hown in Figure The next-tate and output function for the mater FSM again ue a concatenated aignment to et the next tate, the output, and the four control ignal with a ingle aignment. A neted? : tatement i ued to compute the next tate for the FLASH tate to tet both tdone and cdone. In everal tate, tatu ignal tdone i paed directly through to control ignal tload and cdec. The counter module i nearly identical to the timer module but with lightly different control becaue the counter only decrement when cdec i aerted while the timer alway decrement. With ome generalization a ingle parameterized module could be ued for both function. The waveform from a imulation of the doubly factored light flaher are hown in Figure For thi imulation, the counter wa initialized with a

9 Copyright (c) by W.J Dally, all right reerved 309 in Mater FSM out (a) tload tel tdone cload cdec cdone Timer Counter tdone cdone in tdone tdone (b) OFF in FLASH tdone cdone SPACE tdone tload= 1 tel = 1 cload = 1 cdec = 0 out = 0 tload = tdone tel = 0 cload = 0 cdec = 0 out = 1 tload = tdone tel = 1 cload = 0 cdec = tdone out = 0 Figure 17.6: The light flaher of Figure 17.1 factored twice. The poition within the current flah i held in a timer. The number of flahe remaining i held in a counter. Finally, whether we are off, in a flah, or a pace i determined by the mater FSM. (a) Block diagram of the twice factored machine. (b) State diagram of the mater FSM.

10 310 EE108A Cla Note // define for doubly factored tate define XWIDTH 2 define X_OFF 2 b00 define X_FLASH 2 b01 define X_SPACE 2 b10 module Flah2(clk, rt, in, out) ; input clk, rt, in ; // in trigger tart of flah equence output out ; // out drive LED reg out ; // output wire [ XWIDTH-1:0] tate, next ; // current tate reg [ XWIDTH-1:0] next1 ; // next tate without reet reg tload, tel, cload, cdec ; // timer and countr input wire tdone, cdone ; // timer and counter output // intantiate tate regiter DFF #( XWIDTH) tate_reg(clk, next, tate) ; // intantiate timer and counter Timer1 timer(clk, rt, tload, tel, tdone) ; Counter1 counter(clk, rt, cload, cdec, cdone) ; or rt or in or tdone or cdone) begin cae(tate) X_OFF: {out, tload, tel, cload, cdec, next1} = {1 b0, 1 b1, 1 b1, 1 b1, 1 b0, in? X_FLASH : X_OFF } ; X_FLASH:{out, tload, tel, cload, cdec, next1} = {1 b1, tdone, 1 b0, 1 b0, 1 b0, tdone? (cdone? X_OFF : X_SPACE) : X_FLASH } ; X_SPACE:{out, tload, tel, cload, cdec, next1} = {1 b0, tdone, 1 b1, 1 b0, tdone, tdone? X_FLASH : X_SPACE } ; default:{out, tload, tel, cload, cdec, next1} = {1 b0, tdone, 1 b1, 1 b0, tdone, tdone? X_FLASH : X_SPACE } ; endcae end aign next = rt? X_OFF : next1 ; endmodule Figure 17.7: Verilog decription of the mater FSM from Figure 17.6.

11 Copyright (c) by W.J Dally, all right reerved 311 // define for pule counter // load with 3 for four pule define C_WIDTH 2 define C_COUNT 3 // Counter1 - pule counter // cload - load counter with C_COUNT // cdec - decrement counter by one if not already zero // cdone - ignal when count ha reached zero module Counter1(clk, rt, cload, cdec, cdone) ; parameter n= C_WIDTH ; input clk, rt, cload, cdec ; output cdone ; wire [n-1:0] count ; reg [n-1:0] next_count ; wire cdone ; // tate regiter DFF #(n) tate(clk, next_count, count) ; // ignal done aign cdone =!( count) ; // next count logic alway@(rt or cload or cdec or cdone or count) begin caex({rt, cload, cdec, cdone}) 4 b1xxx: next_count = C_WIDTH b0 ; 4 b01xx: next_count = C_COUNT ; 4 b0010: next_count = count - 1 b1 ; 4 b00x1: next_count = count ; default: next_count = count ; endcae end endmodule Figure 17.8: Verilog decription of the counter from Figure 17.6.

12 312 EE108A Cla Note Figure 17.9: A waveform diplay howing a imulation of the doubly factored light flaher of Figure 17.6.

13 Copyright (c) by W.J Dally, all right reerved o that the mater FSM produce 4 flahe. The different time cale of the three tate variable are clearly viible. The counter (bottom line) move mot lowly, counting down from 3 to 0 over the four-flah equence. It decrement after the lat cycle of each pace. At each point in time, it repreent the number of flahe left to do after the current flah i complete. The mater FSM tate move the next mot lowly. After tarting on the 0 (OFF) tate, it alternate between the 1 (FLASH) tate and the 2 (SPACE) tate until the four flahe are complete. Finally, the timer tate move mot rapidly counting down from 5 to 0forflahe,or3to0forpace Traffic Light Controller A a econd example of factoring, we conider a more ophiticated verion of the traffic-light controller we introduced in Section Thi machine ha two input car ew and car lt that indicate that car are waiting on the eat-wet road (ew) and that car are waiting in a left-turn lane (lt). The machine ha nine output line that drive three et of three light each one et each for the north-outh road, the eat-wet road, and the left-turn lane (from the northouth road). Each et of light conit of a red light, a yellow light, and a green light. Normally the light will be green for the north-outh road. However, if a car i detected on the eat-wet road or the left-turn lane, we wih to witch the light o that the eat-wet or left-turn light i green (with priority going to the left-turn lane). Once the light are witched to eat-wet or left-turn, we leave them witched until either no more car are detected in that direction, or until a timer expire. The light then return to green in the north-outh direction. Each time we witch the light we witch the light in the active direction from green to yellow. Then, after a time interval, we witch them to red. Then, after a econd time interval, we witch them to green. The light are not allowed to change again until they have been green for a third time interval. Given thi pecification we decide to factor the finite-tate machine that implement thi traffic-light controller into five module a hown in Figure A mater FSM accept the input and decide which direction hould be green dir. To time when it i time to force the light back to north-outh, it ue a timer, Timer1. It alo receive a ignal ok back from the combiner that indicate that the equence from the lat direction change i complete and the direction i allowed to change again. The combiner module maintain a current direction tate, and combine thi current direction tate with the light ignal from the light FSM to generate the 9 light output light. The combiner alo receive direction requet from the mater FSM on the dir ignal and equence the light FSM in repone to thee requet. When a new direction requet occur, the combiner deaert on (et it low) to ak the light FSM to witch the light to red. Once the light are red, the current direction i et equal to the direction requet and the on ignal i aerted to requet that the light be equenced to green. Only after

14 314 EE108A Cla Note car_ew car_lt Mater FSM dir 2 ok Combiner 9 light load time 4 tdone on done light 3 Timer1 Light FSM tload time 3 ltdone Timer2 Figure 17.10: Block diagram of a factored traffic-light controller. the done ignal from the light FSM i aerted, ignaling that the equence i complete and the light have been green for the required time interval i the ok ignal aerted to allow another direction change. The module here illutrate two type of relationhip. The mater FSM and combiner module form a pipeline. Requet flow down thi pipeline from left to right. A requet i input to the Mater FSM in the form of a tranition on the car_ew and car_lt input. The Mater procee thi requet and in turn iue a requet to the combiner on the dir line. The combiner in turn procee the requet and output the appropriate equence on the light output in repone. We will dicu pipeline in more depth in Chapter 21. The ok ignal here i an example of a flow control ignal. It provide backpreure on the mater FSM to prevent it from getting ahead of the combiner and light FSM. The mater FSM make a requet and it i not allowed to make another requet until the ok ignal indicate that the ret of the circuit i finihed proceing the firt requet. The other relationhip in Figure are mater-lave relationhip. The Mater FSM act a a mater to Timer1, giving it command, and Timer1 act a a lave, receiving the command and carrying them out. In a imilar manner the combiner i the mater of the Light FSM which in turn i the mater of Timer2. The light FSM equence the traffic light from green to red and then back to green. It receive requet from the combiner on the on ignal and repond to thee requet with the done ignal. It alo generate the 3-bit light ignal which indicate which light in the current direction hould be illuminated. When

15 Copyright (c) by W.J Dally, all right reerved 315 ok & (!car_lt tdone) ok & car_lt LT dir = lt load = 0 NS ok & car_ew &!car_lt dir = n load = 1 EW ok & (!car_ew tdone) dir = ew load = 0 Figure 17.11: State diagram for the mater FSM of Figure the on ignal i et high, it requet that the light ignal witch the light ignal to green. When thi i completed, and the minimum green time interval ha elaped, the light FSM repond by aerting done. When the on ignal i et low, it requet that the light FSM equence the light ignal to red via a yellow tate and oberving the required time interval. When thi i completed done i et low. The light FSM ue it own timer (Timer2) to count out the time interval required for light equencing. For the inteface between the light FSM and the combiner, the done ignal provide flow control. The combiner can only toggle on high when done i low and can only toggle on low when done i high. After toggling on, itmutwait for done to witch to the ame tate a on before witching on again. A tate diagram for the mater FSM i hown in Figure The machine tart in the NS tate. In thi tate Timer1 i loaded o it can count down in the LT and EW tate, and the requeted direction i NS. State NS i exited when the ok ignal indicate that a new direction can be requeted and when one of the car ignal indicate that there i a car waiting in another direction. In the EW and LT tate, the new direction i requeted and the tate i exited with ok i true and either there i no longer a car in that direction or the timer ha expired, a ignaled by tdone. The light FSM i a imple light equencer imilar to our light flaher of Section A tate diagram for the light FSM i hown in Figure Like the light flaher, during the lat cycle in each tate the timer i loaded with the timeout for the next tate. The machine tart in the RED tate. It tranition to GREEN when the timer i done and the on ignal from the combiner indicate

16 316 EE108A Cla Note tdone RED tdone & on GREEN tdone &!on YELLOW light = RED tload = tdone & on time = T_GREEN done =!tdone light = GREEN tload = tdone &!on time = T_YELLOW done = tdone light = YELLOW tload = tdone time = T_RED done = 1 Figure 17.12: State diagram for the light FSM of Figure that a green light i requeted. The done ignal i aerted after the timer in the GREEN tate ha completed it count down. The tranition to YELLOW i triggered by the timer being complete and the on ignal being low. The tranition from YELLOW to RED occur on the timer alone. The done ignal i held high during the YELLOW tate. It i allowed to go low, ignaling that the tranition to RED i complete, only after the timer ha completed it countdown in the RED tate. A Verilog decription of the mater FSM for the factored traffic-light controller i hown in Figure Thi module intantiate a timer and then ue a cae tatement to realize a three-tate FSM that exactly follow the tate diagram of Figure Verilog elect,? :, tatement are ued for the next-tate logic. A triply-neted elect tatement i ued in tate M_NS to tet in turn ignal ok, car_lt, andcar_ew. The mater FSM doe not intantiate the combiner. Both the mater and combiner are intantiated a peer module at the top level. A Verilog decription of the combiner module i hown in Figure Thi module accept a dir input from the mater FSM, repond to the mater FSM with flow-control ignal ok, and generate the light output. The key piece of tate in the combiner module i the current direction regiter cur_dir. Thi hold the direction that the light FSM i currently equencing. It i updated with the requeted direction, dir, whenon and done are both low. Thi occur when the combiner ha requeted that the light be equence to red (on low), and the light FSM ha completed thi requeted action (done low). The on command, which requet the light FSM to equence the light to green, i aerted any time the current direction and the requeted direction match. When the mater FSM requet a new direction, thi caue on to go low - requeting the light FSM to equence the light red in preparation for the new direction. The ok repone to the mater FSM i aerted when on and done are both true. Thi occur when the light FSM ha completed equencing the requeted direction to green. The light output i computed by a cae tatement with the current direction a the cae variable. Thi cae tatement inerte the light output from

17 Copyright (c) by W.J Dally, all right reerved 317 // mater FSM tate // thee alo erve a direction value define MWIDTH 2 define M_NS 2 b00 define M_EW 2 b01 define M_LT 2 b10 //Mater FSM // car_ew - car waiting on eat-wet road // car_lt - car waiting in left-turn lane // ok - ignal that it i ok to requet a new direction // dir - output ignaling new requeted direction module TLC_Mater(clk, rt, car_ew, car_lt, ok, dir) ; input clk, rt, car_ew, car_lt, ok ; output [1:0] dir ; wire [ MWIDTH-1:0] tate, next ; // current tate and next tate reg [ MWIDTH-1:0] next1 ; // next tate without reet reg tload ; // timer load reg [1:0] dir ; // direction output wire tdone ; // timer completion // intantiate tate regiter DFF #( MWIDTH) tate_reg(clk, next, tate) ; // intantiate timer Timer #( TWIDTH) timer(clk, rt, tload, T_EXP, tdone) ; or rt or car_ew or car_lt or ok or tdone) begin cae(tate) M_NS: {dir, tload, next1} = { M_NS, 1 b1, ok? (car_lt? M_LT : (car_ew? M_EW : M_NS)) : M_NS} ; M_EW: {dir, tload, next1} = { M_EW, 1 b0, (ok & (!car_ew tdone))? M_NS : M_EW} ; M_LT: {dir, tload, next1} = { M_LT, 1 b0, (ok & (!car_ew tdone))? M_NS : M_LT} ; default: {dir, tload, next1} = { M_NS, 1 b0, M_NS} ; endcae end aign next = rt? M_NS : next1 ; endmodule Figure 17.13: Verilog decription of the mater FSM for the traffic-light controller.

18 318 EE108A Cla Note // // Combiner - // dir - direction requet from mater FSM // ok - acknowledge to mater FSM // light - 9-bit to control traffic light {NS,EW,LT} // module TLC_Combiner(clk, rt, dir, ok, light) ; input clk, rt ; input [1:0] dir ; output ok ; output [8:0] light ; wire done ; wire [2:0] light ; reg [8:0] light ; wire [1:0] cur_dir ; // requet green from light FSM until direction change wire on = (cur_dir == dir) ; // update direction when light FSM ha made light red wire [1:0] next_dir = rt? 2 b0 : ((!on &!done)? dir : cur_dir) ; // ok to take another change when light FSM i done wire ok = on & done ; // current direction regiter DFF #(2) dir_reg(clk, next_dir, cur_dir) ; // combine cur_dir and light to get light or light) begin cae(cur_dir) M_NS: light = {light, RED, RED} ; M_EW: light = { RED, light, RED} ; M_LT: light = { RED, RED, light} ; default: light = { RED, RED, RED} ; endcae end // light FSM TLC_Light lt(clk, rt, on, done, light) ; endmodule Figure 17.14: Verilog decription of the combiner for the traffic-light controller.

19 Copyright (c) by W.J Dally, all right reerved 319 the light FSM into the poition correponding to the current direction and et the other poition to be red. A Verilog decription of the light FSM i hown in Figure The module intantiate a timer and then ue a cae tatement to implement a FSM with tate tranition a hown in Figure Verilog elect tatement are ued for the next-tate logic. Waveform from a imulation of the factored traffic-light controller are hown in Figure The machine i initally reet with the Mater FSM in the NS tate (00). Output dir i alo NS (00). The ok line i initially low becaue the light FSM ha not yet finihed it equencing to make the light green in the NS direction. The light are initially all red (444) but change after one cycle to be green in the north-outh direction (144). The light FSM i initialized to the RED (00) tate and advance to the green tate becaue on and tdone are both aerted. In the green tate it tart a timer and wait until tdone i again aerted before ignaling done to the combiner which in turn caue the combiner to ignal ok to the Mater FSM. Becaue car_ew i aerted, once the ok ignal goe high, the Mater FSM requet a change in direction to eat-wet by etting dir to 01. The combiner repond by etting on low to requet the light FSM to equence the current direction light to red. The light FSM in turn repond by tranitiong to the YELLLOW tate (10) which caue light to go to yellow (2) and light to go to yellow in the north outh direction. When the light timer complete it countdown, the light machine enter the RED tate (00), light become 4 (RED), and light become red in all direction. Once the light timer count down the minimum time in the all-red tate, the light FSM et done low ignaling that it ha completed the tranition. With on and done both low, the combiner update cur_dir to eat-wet (01) and et on high to requet the light FSM to equence the light green in the eat-wet direction. When the light FSM complete thi action - including timing the green tate - it et done true. Thi in turn caue the combiner to et ok true, ignaling the Mater FSM that it i ready to accept a new direction. When ok i aerted the econd time, the Mater FSM requet the northouth direction again (dir = 00). Thi deciion i driven by the car_ew line being low and the mater timer being done. Thi new direction caue on to go low, equencing the light to the all red tate. Then, after cur_dir i updated, etting on high to equence them back to the green tate. When thi i all complete, ok i aerted again. On thi third aertion of ok, ignalcar_lt i true, o a left-turn i requeted (dir = 10) and the light are equenced to red and back to green again. When the equencing i completed, ok i aerted for a fourth time. Thi time car_lt i till aerted, but the mater timer i done, o a north-outh direction i again requeted.

20 320 EE108A Cla Note // // Light FSM // module TLC_Light(clk, rt, on, done, light) ; input clk, rt, on ; output done ; output [2:0] light ; reg [2:0] light ; reg done ; wire [ LWIDTH-1:0] tate, next ; // current tate, next tate reg [ LWIDTH-1:0] next1 ; // next tate w/o reet reg tload ; reg [ TWIDTH-1:0] tin ; wire tdone ; // intantiate tate regiter DFF #( LWIDTH) tate_reg(clk, next, tate) ; // intantiate timer Timer timer(clk, rt, tload, tin, tdone) ; or rt or on or tdone) begin cae(tate) L_RED: {tload, tin, light, done, next1} = {tdone & on, T_GREEN, RED,!tdone, (tdone & on)? L_GREEN : L_RED} ; L_GREEN: {tload, tin, light, done, next1} = {tdone &!on, T_YELLOW, GREEN, tdone, (tdone &!on)? L_YELLOW : L_GREEN} ; L_YELLOW: {tload, tin, light, done, next1} = {tdone, T_RED, YELLOW, 1 b1, tdone? L_RED : L_YELLOW} ; default: {tload, tin, light, done, next1} = {tdone, T_RED, YELLOW, 1 b1, tdone? L_RED : L_YELLOW} ; endcae end aign next = rt? L_RED : next1 ; endmodule Figure 17.15: Verilog decription of the light FSM for the traffic-light controller.

21 Copyright (c) by W.J Dally, all right reerved 321 Figure 17.16: A waveform diplay howing a imulation of the factored trafficlight controller.

22 322 EE108A Cla Note 17.3 Exercie 17 1 Flaher. Modify the flaher FSM to flah an SOS equence - three hort flahe (one clock each) followed by three long flahe (four clock each) followed by three hort flahe again Traffic Light Controller. Modify the traffic light controller o that northouth and eat-wet have equal priority. Add an additional input, car_n that indicate when a car i waiting in the north-outh direction. In either the NS or EW tate, change to the other if there i a car waiting in the other direction and the mater timer i done Traffic Light Controller. Modify the traffic light controller o that a witch from a red light to a green light i preceeded by both red and yellow being on for three clock.

23 Chapter 18 Microcode Realizing the next-tate and output logic of a finite-tate machine uing a memory array give a flexible way of realizing a FSM. The function of the FSM can be altered by changing the content of the memory. We refer to the content of the memory array a microcode and a machine realized in thi manner i called a microcoded FSM. Each word of the memory array determine the behavior of the machine for a particular tate and input combination and i referred to a a microintruction. We can reduce the required ize of a microcode memory by augmenting the memory with pecial logic to compute the next tate, and by electively updating infrequently changing output. A ingle microintruction can be provided for each tate, rather than one for each tate input combination, by providing an intruction equencer and a branch microintruction to caue change in control flow. Bit of the microintruction can be hared by different function by defining different microintruction type for control, output, and other function. Microcode wa originated by Maurice Wilke at Cambridge Univerity in 1951 to implement the control logic for the EDSAC computer [?]. It ha been widely ued ince that time in many different type of digital ytem A Simple Microcoded FSM Figure 18.1 how a block diagram of a imple microcoded FSM. A memory array hold the next-tate and output function. Each word of the array hold the next tate and output for a particular combination of input and next tate. The array i addreed by the concatenation of the current tate and the input. A pair of regiter hold the current tate and current output. In practice the memory could be realized a a RAM or EEPROM allowing oftware to reprogram the microcode. Alternatively the memory could be a ROM. With a ROM, a new mak et i required to reprogram the microcode. However, thi i till advantageou a changing the program of the ROM doe not otherwie alter the layout of the chip. Some ROM deign even allow the 323

24 324 EE108A Cla Note next D Q tate +i a Memory d +o input i n_out o D Q o out clk Figure 18.1: Block diagram of a imple microcoded FSM. program to be changed by altering only a ingle metal-level mak reducing the cot of the change. Some deign take a hybrid approach putting mot of the microcode into ROM (to reduce cot) but keeping a mall portion of microcode in RAM. A method i provided to redirect an arbitrary tate equence into the RAM portion of the microcode to allow any tate to be patched uing the RAM. A verilog decription of thi FSM i hown in Figure It follow the chematic exactly with the addition of ome logic to reet the tate when rt i aerted. The module ROM i a read-only-memory that take an addre {tate, in} and return a microintruction uint. The microintruction i then plit into it next-tate and output component. The FSM of Figure 18.1 and 18.2 i very imple becaue it ha no function until the ROM i programmed. To ee how to program the ROM to realize a finite tate machine, conider our imple traffic-light controller from Section The tate diagram of thi controller i repeated in Figure To fill our microcode ROM, we imply write down the next tate and output for each current tate/input combination a hown in Table Conider the firt line of the table. Addre 0000 correpond to tate GNS (green north-outh) with input car_ew = 0. Forthi tate, the output i (green north-outh, red eat-wet) and the next tate i GNS (000). Thu, the content of ROM location 0000 i the , the concatenation of the next tate 000 with the output. For the econd line of the table, addre 0001 correpond to GNS with car_ew = 1. The output here i the ame a for the firt line, but the next tate i now YNS (001) hence the content of thi ROM location i The remaining row of the table are derived in a imilar manner. The ROM itelf i loaded with the content of the column labeled Data. The reult of imulating the microcoded FSM of Figure 18.2 uing the ROM content from Table 18.1 are hown in Figure The output, tate, and microcode ROM addre, and microcode ROM data (microintruction) (the bottom four ignal) are diplayed in octal (bae 8). The ytem intitialize to tate 0 (GNS) with output 41 (green (4) north-outh, red (1) eat-wet). Then

25 Copyright (c) by W.J Dally, all right reerved 325 module ucode1(clk,rt,in,out) ; parameter n = 1 ; // input width parameter m = 6 ; // output width parameter k = 3 ; // bit of tate input clk, rt ; input [n-1:0] in ; output [m-1:0] out ; wire [k-1:0] next, tate ; wire [k+m-1:0] uint ; DFF #(k) tate_reg(clk, next, tate) ; // tate regiter DFF #(m) out_reg(clk, uint[m-1:0], out) ; // output regiter ROM #(n+k,m+k) uc({tate, in}, uint) ; // microcode tore aign next = rt? {k{1 b0}} : uint[m+k-1:m] ; // reet tate endmodule Figure 18.2: Verilog decription of a imple microcoded FSM carew gn carew yn gew yew tate output gyr gyr n ew Figure 18.3: State diagram of imple traffic-light controller.

26 326 EE108A Cla Note Addre State car_ew Next State Output Data 0000 GNS (000) 0 GNS (000) GNS (000) 1 YNS (001) YNS (001) 0 GEW (010) YNS (001) 1 GEW (010) GEW (010) 0 YEW (011) GEW (010) 1 YEW (011) YEW (011) 0 GNS (000) YEW (011) 1 GNS (000) Table 18.1: State table for imple microcoded traffic-light controller the input line (car_ew) goe high witching the ROM addre from 00 to 01. Thi caue the microintruction to witch from 041 to 141 which elect a next tate of 1 (YNS) on the next clock. The machine then proceed through tate 2 (GEW) and 3 (YEW) before returning to tate 0. The beauty of microcode i that we can change the function of our FSM by changing only the content of the ROM. Suppoe for example that we would like to modify the FSM o that: 1. The light tay green in the eat-wet direction a long a car_ew i true. 2. The light tay green in the north outh direction for a minimum of three cycle (tate GNS1, GNS2, and GNS3). 3. After a yellow light, the light hould go red in both direction for one cycle before turning the new light green. Table 18.2 how the tate table that implement thee modification. We plit tate GNS into three tate and add two new tate (RNS and REW). Note that the GEW tate now tet car_ew and tay in GEW a long a it i true. The reult of imulating our FSM of Figure 18.2 with thi new microcode i hown in the waveform diplay of Figure Intruction Sequencing A microcoded FSM can be made coniderably more efficient by uing a equencer to generate the addre of the next intruction. Performing intruction equencing ha two big advantage. Firt, for microintruction that imply proceed to the next intruction, thi intruction addre can be generated with a counter, eliminating the need to tore the addre in the microcode memory. Second, by uing logic to elect or combine the different input, the microcode tore can tore a ingle microintruction for each tate, rather than having to tore eparate (and nearly identical) intruction for each poible combination of input.

27 Copyright (c) by W.J Dally, all right reerved 327 Figure 18.4: A waveform diplay howing a imulation of the microcoded FSM of Figure 18.2 uing the microcode from Table 18.1.

28 328 EE108A Cla Note Figure 18.5: A waveform diplay howing a imulation of the microcoded FSM of Figure 18.2 uing the microcode from Table 18.2.

29 Copyright (c) by W.J Dally, all right reerved 329 Addre State car_ew Next State Output Data 0000 GNS1(000) 0 GNS2(001) GNS1(000) 1 GNS2(001) GNS2(001) 0 GNS3(010) GNS2(001) 1 GNS3(010) GNS3(010) 0 GNS3(010) GNS3(010) 1 YNS (011) YNS (011) 0 RNS (100) YNS (011) 1 RNS (100) RNS (100) 0 GEW (101) RNS (100) 1 GEW (101) GEW (101) 0 YEW (110) GEW (101) 1 GEW (101) YEW (110) 0 REW (111) YEW (110) 1 REW (111) REW (111) 0 GNS (000) REW (111) 1 GNS (000) Table 18.2: State table for imple microcoded traffic-light controller A review of the microcode from Table 18.2 how the redundancy a equencer can eliminate. Each intruction include an explicit next-tate field while all intruction either elect themelve or the next intruction in equence for the next tate. Alo, all intruction are duplicated for both input tate, with only two having a mall difference in the next tate field. Thi overhead would be even higher if there were more than one input ignal. Adding a equencer to our microcoded FSM i the firt tep from an FSM (where the next tate i determined by a logic function) to a tored-program computer, where the next intruction i determined by interpreting the current intruction. With a equencer, like a tored program computer, our microcoded machine execute microintruction in equence until a branch intruction redirect execution to a new addre. Figure 18.6 how a microcoded FSM that ue an intruction equencer. The tate regiter here i replaced with a microprogram counter (μpc or upc) regiter. At any point in time thi regiter repreent the current tate by electing the current microintruction. With thi deign we have reduced the number of microintruction in the microcode memory from 2 +i to 2,thati from 2 i per tate to 1 per tate. The cot of thi reduction i increaing the width of each microintruction from + o bit to + o + b bit. Each microintruction conit of three field a hown in Figure 18.7: an o-bit field that pecifie the current output, an -bit field that pecifie the addre to branch to (the branch target), and a b-bit field that pecifie a branch intruction. With the intruction equencer, input are teted by the branch logic a directed by a branch intruction from the current microintruction. A a reult

30 330 EE108A Cla Note branch_target Mux nupc upc 1 D Q a Memory d +o+b 0 2 n_out 3 D Q o input i Branch Logic clk o out branch_intruction b Figure 18.6: A microcoded FSM uing an intruction equencer. A multiplexer and incrementer compute the next microintruction addre (next tate) baed on a branch intruction and the input condition. br int b br target output o Figure 18.7: Microintruction format for the microcoded FSM with intruction equencer of Figure 18.6.

31 Copyright (c) by W.J Dally, all right reerved 331 Encoding OpCode Decription 000 NOP Never branch, alway proceed to upc B0 Branch on input 0. If in[0] branch to br_upc otherwie continue to upc B1 Branch on input BA Branch any. Branch if either input i true. 100 BR Alway branch. Select br_upc a the next upc regardle of the input. 101 BN0 Branch on not input 0. If in[0] i fale, branch, otherwie continue to upc BN1 Branch on not input BNA Branch only if input 0 and 1 are both fale. Table 18.3: Branch intruction encoding. of thi tet, the equencer either branche (by electing the branch target field a the next upc) or doen t (by electing upc+1 a the next UPC). Conider an example with a two-bit input field. We can define a three-bit branch intruction brint a follow. branch = (brint[0] & in[0] brint[1] & in[1]) ^ brint[2] ; Branch intruction bit 0 and 1 elect whether we tet input bit 0 or 1 (or either). Branch intruction bit 2 control the polarity of the tet. If brint[2] i low, we branch if the elected bit() i high. Otherwie we branch if the elected bit() i low. Uing thi encoding of the branch intruction, we can perform the branche hown in Table Other encoding of the branch intruction are poible. A common n-bit encoding ue n 1-bit to elect one of 2 n 1 input to tet and the remaining bit to elect whether to branch on the elected input high or low. One of the input i et alway high to allow the NOP and BR intruction to be created. For thi encoding the branch ignal would be: branch = brint[n-1] ^ in[brint[n-2:0]] ; The branch intruction created by thi alternate encoding (for a 3-bit brint and three input are lited in Table To provide the NOP and BR intruction, we ue a contant 1 for the fourth input. Here each branch intruction tet exactly one input, while in the encoding of Table 18.3 the intruction may tet zero, one, or two input. Many other poible encoding beyond to the two preented here are poible. A Verilog decription of the microcoded FSM with an intruction equencer i hown in Figure The Verilog follow the block diagram of Figure 18.6 cloely. One aign tatement calculate ignal branch which i true if the equencer i to branch on the next cycle. A econd aign tatement then calculate the next micro program counter (nupc) baed on branch and rt.

32 332 EE108A Cla Note Encoding OpCode Decription 000 B0 Branch on input B1 Branch on input B2 Branch on input BR Alway branch. (Input 3 i the contant 1 ). 100 BN0 Branch on not input BN1 Branch on not input BN2 Branch on not input NOP Never branch. Table 18.4: Alternate branch intruction encoding. module ucode2(clk,rt,in,out) ; parameter n = 2 ; // input width parameter m = 9 ; // output width parameter k = 4 ; // bit of tate parameter j = 3 ; // bit of intruction input clk, rt ; input [n-1:0] in ; output [m-1:0] out ; wire [k-1:0] nupc, upc ; // microprogram counter wire [j+k+m-1:0] uint ; // microintruction word // plit off field of microintruction wire [m-1:0] nxt_out ; // = uint[m-1:0] ; wire [k-1:0] br_upc ; // = uint[m+k-1:m] ; wire [j-1:0] brint ; // = uint[m+j+k-1:m+k] ; aign {brint, br_upc, nxt_out} = uint ; DFF #(k) upc_reg(clk, nupc, upc) ; // microprogram counter DFF #(m) out_reg(clk, nxt_out, out) ; // output regiter ROM #(k,m+k+j) uc(upc, uint) ; // microcode tore // branch intruction decode wire branch = (brint[0] & in[0] brint[1] & in[1]) ^ brint[2] ; // equencer aign nupc = rt? {k{1 b0}} : branch? br_upc : upc + 1 b1 ; endmodule Figure 18.8: Verilog decription of a microcoded FSM with an intruction equencer

33 Copyright (c) by W.J Dally, all right reerved 333 Addre State Br Int Target NS LT EW Data 0000 NS1 BLT (001) LT1(0101) NS2 BNEW (110) NS1(0000) EW1 NOP (000) EW2 BEW (010) EW2(0011) EW3 BR (100) NS1(0000) LT1 NOP (000) LT2 BLT (001) LT2(0110) LT3 BR (100) NS1(0000) Table 18.5: Microcode for traffic light controller with equencer of Figure To make the code more readable we ue an aign tatement to plit out the three field of the microintruction into the output (nxt_out), the branch target (br_upc), and the branch intruction (brint). Uing thee mnemonic name, rather than indexing field of uint make the remainder of the code eaier to follow. Conider a lightly more involved verion of our traffic-light controller that include a left-turn ignal a well a north-outh and eat-wet ignal. Table 18.5 how the microcode. Here input 0 i car_lt and input 1 i car_ew o we rename our branche BLT (branch if car_lt), BNEW (branch if not car_ew) and o on. The microcode of Table 18.5 tart in tate NS1 where the light i green in the north-outh direction. In thi tate the left-turn enor i checked with a BLT to LT1. If car_lt i true, control tranfer to LT1. Otherwie the upc proceed to the next tate, NS2. In NS2 the microcode branche back to NS1 if car_ew i fale (BNEW NS1). Otherwie control fall through to EW1 where the north-outh light goe yellow. EW1 i alway followed by EW2 where the eat-wet light i green. A BEW EW2 keep the upc in tate EW2 a long a car_ew i true. When car_ew goe fale, the upc proceed to tate EW3 where the eat-wet light i yellow and a BR NS1 tranfer control back to NS1. The left turn equence (LT1, LT2, LT3) operate in a imilar manner. Waveform from a imulation of the microcoded equencer of Figure 18.8 running the microcode of Table 18.5 i hown in Figure The fifth row from the top how the microprogram counter upc. The machine i reet to upc = 0 (NS1) advance to 1 (NS2), then back to 0 (NS1) before branching to 5 (LT1). It proceed from 5 (LT1) to 6 (LT2) and remain in 6 until car_lt goe low. At that point it advance to 7 (LT3) and back to 0 (NS1). At thi point car_ew=1, and the equence followed i 0, 1, 2, 3 (NS1, NS2, EW1, EW2). The machine tay in 3 (EW2) until car_ew goe low and then proceed to 4 (EW3) and back to0(ns1). ThemachinecyclebetweenNS1andNS2afewtimeuntilboth car_ew and car_lt go high at the ame time. A the machine i in NS1 when thi happen, car_lt i checked firt and the upc i directed to LT1. Becaue the microcoded FSM of Figure 18.6 can only branch one way in each microintruction, it take two tate (NS1 and NS2) to perform a three-

34 334 EE108A Cla Note Figure 18.9: A waveform diplay howing a imulation of the microcoded FSM of Figure 18.2 uing the microcode from Table 18.2.

35 Copyright (c) by W.J Dally, all right reerved 335 Addre State Br Int Target NS LT EW Data 0000 NS1 BNA (111) NS1(0000) NS2 BLT (001) LT1(0100) EW1 BEW (010) EW1(0010) EW2 BR (100) NS1(0000) LT1 BLT (001) LT1(0100) LT2 BR (100) NS1(0000) Table 18.6: Alternate microcode for traffic light controller with equencer of Figure way branch between taying with north-outh, going to eat-wet, or going to left-turn. Thi reult in two tate with the light green in the north-outh direction (NS1 and NS2) and two tate with the light yellow in the north-outh direction (EW1 and LT1). The real olution to thi problem i to upport a multi-way branch (which we will dicu below). However we can partially olve the problem in oftware by uing the alternate microcode hown in Table In the alternate microcode of Table 18.6, the upc tay in tate NS1 a long a car_ew and car_lt are both fale by uing a BNA NS1 (branch on not any input to NS1). NS1 i now the only tate with the light green in the northouth direction. If any input are true, the upc proceed to tate NS2 which i the ingle tate with the light yellow in the north-outh direction. State NS2 tet the car_lt input and branche to tate LT1 if true (BLT LT1). If car_lt i fale, the upc proceed to EW1. The remainder of the machine i imilar to that of Table 18.5 except that the EW and LT tate have been renumbered. Simulation waveform for thi alternate microcode are hown in Figure Multi-way Branche A we aw in the previou ection, uing an intruction equencer greatly reduce the ize of our microcode memory but at the expene of retricting each tate to have at mot two next tate (upc+1 and br_upc). Thi retriction can be a problem if we have an FSM that ha a large number of exit from a particular tate. For example, in a microcoded proceor, it i typical to branch to one of 10 to 100 of next tate baed on the opcode of the current intruction. Another multi-way branch i then needed on the addreing mode of the intruction. Implementing uch a multi-way dipatch uing the equencer of Section 18.2 would reult in very poor efficiency a n cycle would be required to tet for n different opcode. We can overcome thi limitation of two-way branche by uing an intruction equencer that upport multi-way branche a hown in Figure Thi equencer i imilar to that of Figure 18.6 except that the branch target, br_upc, i generated from the branch intruction, brint, and input rather than being provided directly from the microintruction. With thi approach, we can branch

36 336 EE108A Cla Note Figure 18.10: A waveform diplay howing a imulation of the microcoded FSM of Figure 18.2 uing the microcode from Table 18.2.

37 Copyright (c) by W.J Dally, all right reerved 337 input i Branch Target Logic +1 br_upc 0 Mux3 0 nupc D Q upc a Memory d +o+b branch_target n_out o D Q o out i Branch Logic clk branch_intruction b Figure 18.11: A microcoded FSM with an intruction equencer that upport multi-way branche. Encoding Opcode Decription BRx 00xx Branch on condition x. (A in Table 18.4 include BR) BRNx 01xx Branch on not condition x. (A in Table 18.4 include NOP) BR Branch four way. nupc = br_upc + in. Table 18.7: branche. Branch intruction for microcoded FSM upporting multi-way to up to 2 i next tate (one for each input combination) from each tate. The branch intruction encode not jut the condition to tet, but alo how to determine the branch target. Table 18.7 how one poible method of encoding multi-way branch intruction. The BRx and BRNx intruction are two-way branch intruction identical to thoe pecified in Table The BR4 intruction i a four-way branch that elect one of four adjacent tate (from br_upc to br_upc+3) depending on the input. To ue the BR4 intruction require ome care in mapping tate to microintruction addree and may require that ome tate are duplicated. Conider, for example, the tate diagram of Figure A mapping of thi tate diagram to microcode addree for a machine with a four-way branch intruction that add the input to the branch target i hown in Table The four-way branch from X target addre 000, o we mut lay out branch target A1, B1, C1, and X in location 000, 001, 010, and 011 repectively. In a imilar manner we locate tate o that the four-way branch from C1 target addre 100. Thu we mut place tate C2, C3, X, and C1 at location 100, 101, 110, and 111 repectively. To make thi work we need two copie of X, one at 011 and one at

38 338 EE108A Cla Note in=d in=a A1 A2 X in=b B1 in=c C1 in=a C2 in=c in=b in=d C3 Figure 18.12: State diagram with two four-way branche. Addre State Branch Int Branch Target 000 A1 BR A2 001 B1 BR C2 010 C1 BR4 C2 011 X BR4 A1 100 C2 BR X 101 C3 BR X 110 X BR4 A1 111 C1 BR4 C2 Table 18.8: Mapping of tate diagram of Figure onto microcode addree. State X and C1 are duplicated becaue they each appear in two four-way branche. 110 and two copie of C1 (at 010 and 111). When we duplicate a tate in thi manner we imply arrange for the two copie (e.g., X and X ) to have identical behavior Multiple Intruction Type So far we have coniderd microcoded FSM that update all output bit in every microintruction. In general, mot FSM need to update only a ubet of the output in a given tate. Our traffic-light controller FSM, for example, change at mot one light on each tate change. We can ave bit of the microintruction by modifying our FSM to update only a ingle output regiter in any given tate. We wate other microintruction bit by pecifying a branch intruction and branch target in each microintruction even though many microintruction

39 Copyright (c) by W.J Dally, all right reerved 339 Branch Intruction 1 condition branch target Store Intruction 0 detination value Figure 18.13: Intruction format for a microcoded FSM with eparate output and branch intruction. target/value Mux nupc upc 1 D Q a Memory d x input i Branch Logic intruction x x Output Decode n o e1 o en D Q E clk D Q E clk o o out1 outn Figure 18.14: Block diagram of a microcoded FSM with output intruction. alway proceed to the next tate and don t branch. We can ave thee redundant branch bit by only branching in ome intruction and updating output in other intruction. Figure how the intruction format for a microcoded FSM with two microintruction type: a branch intruction and a tore (output) intruction. Each microintruction i one or the other. A branch intruction, identified by a 1 in the left-mot bit, pecifie a branch condition and a branch target. When the FSM encounter a branch microintruction, it branche (or doen t) a pecified by the condition and target. No output are updated. A tore intruction, identified by a 0 in the left-mot bit, pecifie an output regiter and a value. When the FSM encounter a tore microintruction it tore the value to the pecified output regiter and then proceed to the next microintruction in equence. No branching take place with a tore intruction. Figure how a block diagram of a microcoded FSM that upport the two intruction type of Figure Each microintruction i plit into an x-bit intruction field and a -bit value field. The intruction field hold the operation-code (opcode) bit (the left-mot bit that ditinguihe between branch and tore) and either the condition (for a branch) or the detination (for

40 340 EE108A Cla Note a tore). The value field hold either the branch target (for a branch) or the new output value (for a tore). The intruction equencer of Figure i identical to that of Figure 18.6 except that the branch logic alway elect the next microintruction upc+1 when the current microintruction i a tore intruction. 1 The major difference i with the output logic. Here a decoder enable at mot one output regiter to receive the value field on a tore intruction. A Verilog decription for the microcode engine with two intruction type of Figure i hown in Figure Here the microintruction i plit into an opcode (0=tore, 1=branch), an intruction (detination for tore, condition for branch), and a value. For a tore, the detination i decoded into a onehot enable vector, e, that i ued to enable the value to be tored into one of the three output regiter (n=0, ew=1, lt=2) or to load the timer (det = 3). For a branch, int[2] determine the polarity of the branch, and the low two bit, int[1:0], determine the condition to be teted (lt=0, ew=1, lt ew=2, timer=3). Table 18.9 how the microcode for a more ophiticated traffic-light controller programmed on the microcode engine of Figure The firt three tate load the three output regiter with RED in the eat-wet and left-turn regiter and GREEN in the north-outh regiter. Next tate NS1 and NS2 wait for eight cycle by loading the timer and waiting for it to ignal done. State NS4 then wait for either input. The north-outh light i et to YELLOW in NS5. NS6 and NS7 then et the timer and wait for it to be done before advancing to NS8 where the north-outh light i et to RED. If the left-turn input i true NS9 branche to LT1 to equence the left-turn light. Otherwie the eat-wet light are equenced in tate EW1 through EW9. Waveform from a imulation of thi microcode are hown in Figure Microcode Subroutine The tate equence in Table 18.9 are very repetitive. The NS, EW, and LT equence perform largely the ame action. The only alient difference i the output regiter being written. Jut a we hared common tate equence by factoring FSM in Chapter 17, we can hare common tate equence in a microcoded FSM by upporting ubroutine. A ubroutine i a equence of intruction that can be called from everal different point and after exiting return control to the point from which it wa called. Figure how the block diagram of a microcode engine that upport one level of ubroutine. Thi machine i identical to that of Figure except for two difference: (a) a return upc regiter, rupc and aociated logic have been added to the equencer, and (b) a elect regiter and aociated logic have been added to the output ection. 1 One can jut a eaily add multiple intruction type and output regiter to a FSM that upport multi-way branche (Figure 18.11).

41 Copyright (c) by W.J Dally, all right reerved 341 module ucodemi(clk,rt,in,out) ; parameter n = 2 ; // input width parameter m = 9 ; // output width parameter o = 3 ; // output ub-width parameter k = 5 ; // bit of tate parameter j = 4 ; // bit of intruction input clk, rt ; input [n-1:0] in ; output [m-1:0] out ; wire [k-1:0] nupc, upc ; // microprogram counter wire [j+k-1:0] uint ; // microintruction word wire done ; // timer done ignal // plit off field of microintruction wire opcode ; // opcode bit wire [j-2:0] int ; // condition for branch, det for tore wire [k-1:0] value ; // target for branch, value for tore aign {opcode, int, value} = uint ; DFF #(k) upc_reg(clk, nupc, upc) ; // microprogram counter ROM #(k,k+j) uc(upc, uint) ; // microcode tore // output regiter and timer DFFE #(o) or0(clk, e[0], value[o-1:0], out[o-1:0]) ; // NS DFFE #(o) or1(clk, e[1], value[o-1:0], out[2*o-1:o]) ; // EW DFFE #(o) or2(clk, e[2], value[o-1:0], out[3*o-1:2*o]) ; // LT Timer #(k) tim(clk, rt, e[3], value, done) ; // timer // enable for output regiter and timer wire [3:0] e = opcode? 4 b0 : 1<<int ; // branch intruction decode wire branch = opcode? (int[2] ^ (((int[1:0] == 0) & in[0]) // BLT ((int[1:0] == 1) & in[1]) // BEW ((int[1:0] == 2) & (in[0] in[1])) //BLE ((int[1:0] == 3) & done))) // BTD : 1 b0 ; // for a tore opcode // microprogram counter aign nupc = rt? {k{1 b0}} : branch? value : upc + 1 b1 ; endmodule Figure 18.15: Verilog decription of a microcoded FSM with two intruction type.

42 342 EE108A Cla Note Addre State Intruction Value Data RST1 SLT (0010) RED RST2 SEW (0001) RED NS1 SNS (0000) GREEN NS2 STIM(0011) TGRN NS3 BNTD(1111) NS NS4 BNLE(1110) NS NS5 SNS (0000) YELLOW NS6 STIM(0011) TYEL NS7 BNTD(1111) NS NS8 SNS (0000) RED NS9 BLT (1000) LT EW1 STIM(0011) TRED EW2 BNTD(1111) EW EW3 SEW (0001) GREEN EW4 STIM(0011) TGRN EW5 BNTD(1111) EW EW6 SEW (0001) YELLOW EW7 STIM(0011) TYEL EW8 BNTD(1111) EW EW9 BTD (1011) RST LT1 STIM(0011) TRED LT2 BNTD(1111) LT LT3 SLT (0010) GREEN LT4 STIM(0011) TGRN LT5 BNTD(1111) LT LT6 SLT (0010) YELLOW LT7 STIM(0011) TYEL LT8 BNTD(1111) LT LT9 BTD (1011) RST Table 18.9: Microcode to implement traffic-light controller on FSM with two intruction type.

43 Copyright (c) by W.J Dally, all right reerved 343 Figure 18.16: A waveform diplay howing a imulation of the microcoded FSM of Figure uing the microcode from Table 18.9.

44 344 EE108A Cla Note 3 3 D Q n en E +1 0 input nupc Mux Branch Logic erpc D E D Q upc Q a intruction Memory d x+ x target/value x Output Decode 5 3 elt 3 D Q E lt 3 3 D Q ew eew E 2 2 D Q el eel E 3 In dn etim L Figure 18.17: Microcoded FSM with upport for one level of ubroutine. The rupc regiter i ued to hold the upc to which a ubroutine hould branch when it complete. When a ubroutine i called, the branch target i elected a the next upc and upc+1, the addre of the next intruction in equence i aved in the rupc regiter. A pecial branch intruction CALL i ued to caue the enable line to the rupc regiter, erpc, to be aerted. When the ubroutine i complete, it return control to the aved location uing another pecial branch intruction RET to elect the rupc a the ource of the next upc. The elect regiter i ued to allow the ame tate equence to write to different output regiter when called from different place. A two-bit regiter identifier (n=0, ew=1, lt=2) can be tored in the elect regiter. A pecial tore intruction SSEL can then be ued to tore to the regiter pecified by the elect regiter (rather than by the detination bit of the intruction). Thu, the main program can tore 0 (n) into the elect regiter and then call a ubroutine to equence the north-outh light on and off. The program can then tore 1 (ew) into the elect regiter and call the ame ubroutine to equence the eat-wet light on and off. The ame ubroutine can equence different light becaue it perform all of it output uing the SSEL intruction. EXAMPLE CODE HERE 18.6 A Simple Computer 18.7 Bibliographic Note 18.8 Exercie microcode equence detector