Douglas W. Clark. Aiken Computation Lab. Cambridge, MA look only at performance, and in fact only at performance. architecture.

Transcription

1 Performance from Architecture: Comparing a RISC and a CISC with Similar Hardware Organization Dileep Bhandarkar Digital Equipment Corp. 146 Main Street (MLO5-2/G1) Maynard, MA Dougla W. Clark Aiken Computation Lab Harvard Univerity Cambridge, MA Abtract Performance comparion acro dierent computer architecture cannot uually eparate the architectural contribution from variou implementation and technology contribution to performance. Thi paper compare an example implementation from the RISC and CISC architectural chool (a MIPS M/2000 and a Digital VAX 8700) on nine of the ten SPEC benchmark. The organizational imilarity of thee machine provide an opportunity to examine the purely architectural advantage of RISC. The RISC approach offer, compared with VAX, many fewer cycle per intruction but omewhat more intruction per program. Uing reult from a oftware monitor on the MIPS machine and a hardware monitor on the VAX, thi paper how that the reulting advantage in cycle per program range from lightly under a factor of 2 to almot a factor of 4, with a geometric mean of 2.7. It alo demontrate the correlation between cycle per intruction and relative intruction count. Variou reaon for thi correlation, and for the conitent net advantage of RISC, are dicued. 1 Introduction The lat decade ha een the emergence and rapid ucce of Reduced Intruction Set Computer, or RISC, architecture. Following early work by Cray [32, 27] and Cocke [6, 7] and an implementation at IBM [25], univerity reearcher, epecially at Berkeley [23] and Stanford [16] developed deign principle, built proceor, and founded companie. Today the ucce of RISC architecture from SUN (the Berkeley-inpired SPARC deign), MIPS (the Stanfordinpired MIPS deign), and traditional emiconductor companie (Motorola, Intel) i evident big computer companie like IBM, Hewlett Packard, and Digital have alo embraced the concept. The RISC approach promie many advantage over Complex Intruction Set Computer, or CISC, architecture, including uperior performance, deign implicity, rapid development time, and other [19, 22]. Studying all of thee factor at once i beyond the cope of thi paper, which will on leave from Digital Equipment Corp., look only at performance, and in fact only at performance from the architectural perpective. That i, we will try to control for all inuence on performance other than architecture. We will do thi by tudying two machine, one from each architectural chool, that are trikingly imilar in hardware organization, albeit quite dierent intechnology and cot. We will how that thee dierence are not due to architecture. Our fundamental frame of reference will be the nowfamiliar expreion of performance a a product of the number of intruction executed, the average numberofmachine cycle needed to execute one intruction, and the cycle time: time program = intruction program cycle intruction time cycle We (along with many other) have found thi formulation to be a powerful tool for analyzing, comparing, and projecting proceor performance. The three term are function of variou apect of a ytem deign. The number of intruction executed i a function (for a xed algorithm and ource program) of the compiler and the target architecture, and i uually independent of the detailed hardware implementation and the technology. The machine' baic cycle time, however, i a function mot trongly of the underlying technology (gate peed, RAM peed, and o on), and alo of the hardware tructure or microarchitecture of the machine, particularly the degree of pipelining. The cycle time may alo be aected by the intruction-et architecture. The middle term average number of cycle per executed intruction, or CPI ha the mot complex determinant. The intruction-et architecture i a primary one: in a complex architecture like the VAX, there are individual intruction (uch acharacter-tring-move) whoe execution require hundred of cycle a RISC would accomplih the ame function with (ay) hundred of intruction each taking only one or two cycle. Another important determinant i the hardware organization, epecially the degree of pipelining and the tructure of the cache-memory ubytem. Finally, the compiler can aect thi factor too, through it choice of certain intruction equence over other, through the general quality of it code optimization, and (for ome architecture) through it ability tochedule intruction to avoid tall. The eence of the RISC performance objective i thi: compared with the CISC approach exemplied by VAX, intruction-et architecture hould facilitate implementation that achieve a gro reduction in cycle per intruction

2 MIPS M/2000 Intruction Fetch from I-Cache Read regiter, prepare I-tream contant ALU one cycle - TLB + D-Cache Write regiter with cache data or ALU reult VAX 8700 VAX intruction decode (optional) Microintruction Fetch from control tore Read regiter, prepare I-tream contant ALU TLB + Cache, write regiter with ALU reult Write regiter with cache data Figure 1: Simplied illutration of the two intruction pipeline. A new intruction (microintruction on the VAX) can tart every cycle. The VAX decode cycle i omitted when a microroutine i more than one microintruction long [4]. and poibly ome improvement in cycle time while allowing an increae in the number of intruction executed. The goal i a ubtantial net improvement in execution time. The qualitative evidence that thi goal ha been achieved i by now nearly overwhelming. What i lacking, though, i a careful architectural analyi, and that i what we intend to provide in thi paper. We will need to make two aumption for our tudy: rt, that the compiler are of equivalent quality and econd, that cycle time i not a function of architecture. We arenotentirely happy with the compiler aumption, particularly ince it i quite imprecie and dicult to meaure, but we did ue the bet available compiler for each machine. Our cycle time aumption i valid for technologie and deign approache in which the cycle time i determined by uch architecture-neutral thing a the time to get through an integer ALU and the time to read the rt-level cache. If, on the other hand, ome VAX-pecic function, uch ain- truction decoding or control-tore equencing, limit cycle time, then the neceary adjutment to our reult i a imple multiplication. In any event, we are not addreing the cycle time quetion here. In eence we are looking at thi architectural quetion: what performance advantage doe a RISC have over a VAX with the ame cycle time and imilar hardware organization, given good compiler for each machine? The next ection of thi paper dicue in more detail our two machine, the meaurement method ued for each, and the benchmark that were run. Section 3 preent the baic reult from our meaurement, including intruction count and average cycle per intruction for each machine. Section 4 i a dicuion of thee reult and of everal type of explanatory factor. Section 5 then briey conider variation on implementation tyle for both architecture and ummarize our baic reult, concluding the paper. 2 Apparatu and Method 2.1 The Machine We meaured Digital' VAX 8700 (a ingle proceor verion of the 8800) [4, 11, 30] againt MIPS Computer Sytem' MIPS M/2000 [19, 26]. We concede at the outet that thee two machine are very dierent in technology, ize, and cot: the VAX proceor i nine board full of ECL gate array the MIPS proceor i one board with two cutom CMOS chip. However, there i another VAX, the model 4000/300, whoe proceor i organizationally imilar to the 8700' and technologically imilar to the MIPS M/2000'. The exitence of thi VAX demontrate that the technology dierence between our two meaured machine i not a conequence of architecture. But why not compare the two CMOS machine directly? The main reaon i that only the 8700 had the hardware intrumentation demanded by our meaurement [5]. And in fact, a we will ee, the CMOS VAX' reemblance to the MIPS engine i omewhat le than the 8700'. There are trong organizational imilaritie between the VAX 8700 and the MIPS M/2000. Figure 1 i a impli- ed repreentation of the main CPU pipeline in the two machine. Both illutration have abtracted away ome half-cycle boundarie that appear in the actual hardware, but neither mirepreent the fundamental operation of the pipe. Both machine can iue a new intruction (microintruction on the VAX) every cycle. Figure 1 how that the pipeline match up quite cloely, with the obviou exception of the VAX intruction decode tage. But note that we are matching the MIPS intruction fetch tage with the VAX microintruction fetch tage. Indeed, the 8700 micro-engine hare with the MIPS implementation the following feature: a large et of general purpoe regiter ingle-cycle three-regiter intruction bypaing of ALU reult around the regiter le and to the ALU input o that a regiter can be read in the intruction immediately after the one in which it i written ingle-cycle load and tore intruction that make an addre by adding a diplacement to a regiter bypaing of cache read data around the regiter le and to the ALU input a one-cycle delay lot following a load that can be lled by any intruction not uing the loaded regiter and delayed branche (but the VAX delay i longer ee Section 4.3 below). Thi trong imilarity between MIPS intruction and VAX 8700 microintruction mean that the comparative performance challenge for thi VAX might be viewed a the problem of mapping VAX intruction into microintruction eciently. Awe will dicu in Section 4, ecient mapping i ometime eay but more often quite dicult. Both implementation repreent reaonable tate-of-theart \mid-range" technology. Even though the VAX 8700

3 Table 1: Machine Implementation Parameter VAX 4000/300 MIPS M/2000 VAX 8700 Chip Firt Silicon n/a Sytem Ship CPU REX520 R3000 n/a Technology Cutom CMOS Cutom CMOS ECL gate array Component count CPU 140K tranitor, 115K tranitor approx. 100 gate array, 180Kbit mem 1200 gate each FPU 134K tranitor 105K tranitor (included above) Feature ize 1.5 micron 1.2 micron Die ize CPU 12x12 mm 2 7.6x8.7 mm 2 n/a FPU 12.7x11 mm x12.6 mm 2 Cycle time 28 n. 40 n. 45 n. On-chip cache 2KB none n/a Board cache 128KBI+D 64 KB I, 64 KB D 64 KB I+D TLB 64 entrie 64 entrie 1024 entrie Page ize 512 byte 4Kbyte 512 byte Memory acce time 13 cycle 12 cycle 16 cycle FP multiply 15 cycle 5cycle 15 cycle FP Add 14 cycle 2cycle 11 cycle Lit price $100K $80K $492K Performance Overall SPECmark Integer SPECmark FP SPECmark ue ECL gate-array technology, an adaptation of it microarchitecture ha been implemented in a VLSI CMOS chip [2, 13] that appear in VAX 6000 Model 400 and VAX 4000 Model 300 ytem. Table 1 ummarize the alient implementation characteritic of our two machine together with the VAX 4000/300. The MIPS M/2000 and the VAX 4000/300 are both implemented in cutom CMOS technology, both having a one-chip CPU connected to a one-chip FPU. A direct comparion of thee machine would be complicated by the fact that one ha an on-chip cache and the other doe not. The VAX chip ue omewhat more tranitor, and the CPU ue additional bit of memory for it on-chip cache and microcode. Hence the cot of the VAX chip would be greater than the cot of the MIPS chip, if they ued the ame fabrication proce. We believe that the lower chip cot would be a mall part of the overall cot of a ytem ytem price, of coure, are determined by market factor and buine conideration. Digital' price for it 1990 worktation employing the VAX and MIPS chip are cloe: $12K for the VAXtation 3100/76 (6.6 SPECmark) and $15K for the DECtation 5000/200 (18.5 SPECmark). The VAX 8700 and the MIPS M/2000 have ditractingly imilar cycle time. Thi imilarity we regard merely a a coincidence it i the machine' organizational imilarity that we rely on to jutify our ide-by-ide comparion, not their cycle time. The MIPS machine ha a few advantage: it ha a eparate intruction cache, lightly fater main memory, and coniderably fater oating point. We will argue in Section 4 that the dierence in oating-point performance ha an architectural bai. The M/2000 allow ome overlap of oating-point intruction [19], wherea the VAXe have very minimal overlap. Thee factor hould all contribute to a lightly wider dierence in cycle per intruction between the MIPS ytem and the VAX ytem. 2.2 The Benchmark We ue the SPEC Releae 1 benchmark for our analyi [31]. SPEC i a non-prot corporation whoe member include major worktation and computer companie uch a Digital, HP, IBM, MIPS, Silicon Graphic, Sun, and other. SPEC wa founded to develop a tandard et of benchmark that are application baed. The rt releae ha been available ince October Ten benchmark were elected from a large number of propective candidate. Each repreent a real application or a ignicant kernel extracted from an application, run for an extended length of time, and put a reaonable load on mot modern ytem. Thee benchmark are much more meaningful meaure of CPU performance than \toy" benchmark (Tower of Hanoi, Puzzle, Dhrytone, Whettone, etc.) that have ometime been ued. All SPEC benchmark are portable, and the only program change allowed are SPEC-approved change for portability. They all produce ubtantially the ame anwer on all ytem teted. Reult are expreed in term of the SPECratio or performance relative to the VAX-11/780 for each benchmark. The geometric mean of all ten ratio i called SPECmark. The SPEC Releae 1 uite conit of four integer benchmark (gcc, epreo, eqntott, and li) written in C, and ix oating-point benchmark (pice, doduc, naa7, matrix300, fpppp, and tomcatv) written in Fortran. For detail on thee program, ee [31]. Even though pice wa meant tobea oating-point benchmark, the circuit being imulated reult in a fairly low ue of oating-point operation, and hould therefore be viewed a a mixed integer and oating-point

4 Table 2: RISC factor intruc. CPI RISC benchmark ratio MIPS VAX ratio factor pice2g matrix naa fpppp tomcatv doduc epreo eqntott li geo. mean benchmark [28]. We were not able to meaure gcc on our intrumented VAX 8700, o all of our reult are for the nine other benchmark only. Alo, our run of epreo ued jut one of the four input circuit (bca). We ued the mot up-to-date verion of compiler that were available to u in mid-1990 on both architecture: VAX Fortran V5.0-1 and VAX C V3.1 MIPS F77 v2.0 (v2.10 for matrix300) and CC v2.0. While we have een ome mall dierence in later verion of the compiler, only in the cae of matrix300 on MIPS did the dierence warrant repeating our meaurement. 2.3 The Monitor A hardware monitor deigned pecially for the VAX 8700 wa ued to meaure the SPEC benchmark in detail. Thi monitor, decribed in [5], ue the micro-pc hitogram technique introduced in [14]: a real-time count ikept for each microintruction, and in every cycle the microintruction then in execution in the ALU ha it count incremented. A microcoded machine uch a the VAX 8700 can reveal a great deal of it detailed behavior in thi way claication of the microaddree into appropriate group allow many thing to be meaured. Since the monitor provide count of all cycle and of all intruction, CPI can be calculated directly. Two toolwere ued on MIPS M/2000 ytem to produce execution prole of the SPEC benchmark: Pixie and Pixtat [21]. Pixie read an executable program, partition it into baic block, and write an equivalent program containing additional code that count the execution of each baic block. When thi Pixie-generated program i run, it generate a le containing the baic block count. Then Pixtat analyze the program execution and produce a report on opcode frequencie and variou other thing. CPI i calculated by dividing the CPU time in cycle from an unintrumented run by Pixtat' report of the intruction count (which exclude NOP). 3 Reult 3.1 Intruction and CPI Table 2 how that the chief architecturally-directed performance goal of the RISC approach ha been achieved for the MIPS deign (given the compiler). It how that for all of the SPEC benchmark, average CPI on the MIPS M/2000 i much le than on the VAX The number of intruction, on the other hand, ha increaed, but not nearly a much. The intruction ratio in the table i jut the ratio of MIPS intruction execution to VAX intruction execution, and i alway greater than 1, ranging from a little over 1 to nearly 4, with a geometric mean of The CPI ratio i average VAX CPI divided by average MIPS CPI (we dene it thi way tomake both ratio be greater than 1). It i never lower than 3, goe a high a 10.45, and ha a geometric mean over the nine program of The combined eectofthetwo ratio the net eect on performance i what we call the RISC factor: it i the ratio of the number of cycle per program on the VAX to the correponding number on the MIPS. It i alo obviouly jut the CPI ratio divided by the intruction ratio. Thi factor range from jut under 2 to jut under 4, with a geometric mean of In Table 2 and ubequent table we rank the benchmark in order of increaing RISC factor. Let u look rt at CPI. Both architecture diplay a wide pread of value, panning a range of about 3:1 for MIPS and 4:1 for VAX. The heavy oating-point benchmark have quite large CPI on the VAX, due to the oating-point hardware (Table 1) pice tand out becaue it actually doe very little oating point (Table 3, below). It would be quite mileading to ue the geometric mean of CPI a \typical" gure without reference to the pecic nine program they repreent. Depite the wide variance of intruction and CPI ratio, the RISC factor pan a range of jut under 2:1. The three highet RISC factor are attached to the three integer benchmark, which have the three lowet intruction ratio but only mean-valued CPI ratio. The three lowet RISC factor, on the other hand, come from benchmark that have three of the four lowet CPI ratio but mean-valued intruction ratio. In the middle of Table 2 lie the three benchmark with the highet value of both ratio. The correlation between intruction and CPI ratio i a central reult of thi paper, and will be dicued further below. 3.2 Operation count Table 3 how the execution frequency of oating-point intruction on the twoarchitecture. The MIPS frequency i alway lower than VAX becaue the MIPS architecture require load and tore intruction where the VAX ue operand pecier, whoe execution i charged to the oating-point intruction in which they appear. The RISC factor i clearly not a function of the oating-point percentage on either machine. Except for doduc, the raw number of oating-point intruction i eentially the ame between the two architecture, a indeed it ought tobeifthetwo Fortran compiler do an equally good job. The extra MIPS intruction in doduc ugget that the MIPS compiler mied ome optimization that the VAX compiler found. Table 3 alo report the number of load and tore per intruction together with the raw count of each operation on MIPS relative tovax. VAX almot alway doe more memory reference the exception i tore in fpppp. One explanation for the extra reference i the maller number of general regiter and the lack of oating-point regiter on the VAX, a point we will dicu in Section 4. A a rule the oating-point benchmark do more load and tore than the integer one both machine have 32-bit data path and o need two memory reference for a double-preciion operand. There i a wide range of load and tore per intruction, and nothing in the table i correlated with RISC factor. Only in li i a

5 Table 3: Floating-point operation and 32-bit load/tore oating-point operation 32-bit load 32-bit tore per intruction MIPS count per intruction MIPS count per intruction MIPS count RISC benchmark MIPS VAX (VAX=1) MIPS VAX (VAX=1) MIPS VAX (VAX=1) factor pice2g matrix naa fpppp tomcatv doduc epreo eqntott li Table 4: Cache behavior D-tream cache read mie I-tream cache mie mi ratio (%) per intruction MIPS count per intruction MIPS count RISC benchmark MIPS VAX MIPS VAX (VAX=1) MIPS VAX (VAX=1) factor pice2g matrix naa fpppp tomcatv doduc epreo eqntott li ignicant percentage of the VAX reference attributable to regiter aving and retoring in the procedure linkage intruction (48 percent of all load and tore). 3.3 Cache behavior Table 4 report the cache behavior of the nine benchmark on the two machine. The VAX reult come from the hardware monitor, which i attached not only to the micro-pc but alo to the memory bu [5] the MIPS reult come from cache imulation [20]. All three of the cache (mixed Intruction and Data on the VAX, eparate on MIPS) are 64 KByte, direct-mapped, and write-through (except the MIPS I-cache), with 64-byte block. SPEC benchmark cache performance in other conguration ha been invetigated by Pnevmatikato and Hill [24]. There i a relationhip between the RISC factor and the D-tream mi ratio, particularly on the VAX: roughly peaking, higher mi ratio are attached to lower RISC factor. In particular, the three benchmark with the highet mi ratio on both machine alo have the three lowet RISC factor. Thee three alo have three of the four highet relative count of mie on MIPS. The compelling explanation for the low RISC factor i of coure the fact that a cache mi of xed delay degrade the performance of a low-cpi RISC machine more than it doe a high-cpi VAX. The I-tream i much le important than the D-tream for almot all benchmark on both machine. Particularly in the MIPS M/2000, with it eparate I-cache, the I-tream cache behavior i excellent. The VAX implementation, with it hared cache, experience many more I-tream mie, but the eect i till mall: the program with the highet percentage of cycle lot to I-tream tall i li, which loe only 4 percent. The next-highet I-tream tall gure i 1.8 percent. One might aume that the MIPS D-tream mi ratio would be conitently lower than the VAX one, given the eparate D-cache. But Table 4 how that the MIPS number i actually wore on four benchmark and cloe on a fth. While detailed cache behavior i often quite incrutable, there i an intuitive explanation for thi. VAX load outnumber MIPS load in large part becaue VAX ha fewer regiter, and o the \extra" load are often reference to data that the MIPS compiler keep in regiter. If the compiler' judgement i good, then thee load ought to be more likely to hit in the VAX cache than the ret of the load. Thi eect would be tronget when the VAX I-tream i not a major factor in cache performance, and in fact Table 4 how that for the mot part mall VAX I-tream mi rate come from program in which the MIPS D-tream mi ratio i above or cloe to the VAX' (the exception i epreo). 4 Dicuion Figure 2 illutrate the relationhip between the intruction ratio and the CPI ratio. A we pointed out earlier, the RISC factor itelf ha lower variance than either of it contituent thi i illutrated in the gure by the tendency of the point to cluter around a ingle line of contant relative performance, namely the line MIPS = 2:66 VAX. The correlation ha a imple and natural explanation: given reaonable compiler, higher VAX CPI hould correpond to a higher relative intruction count on MIPS. In thi ection we will explore the correlation of the ratio, conider why RISC ha a ignicant net advantage, and look at explanation for what variance there i in RISC factor.

6 I N S T R A T I O MIPS =1 VAX 2 fpppp ; ;; tomcatv ; ;;; pice2g6 doduc matrix300 naa7 epreo li ; ;;; eqntott ; ;;; CPI RATIO 3 4 Figure 2: Intruction ratio veru CPI ratio. Line of contant RISC factor are hown. 4.1 Exploring the extreme Anumber of factor are at work in Figure 2. Some help explain the tradeo between MIPS intruction and VAX CPI, while other help explain the conitent net advantage of MIPS. There are even a few factor that favor VAX. Before conidering carefully thee variou factor we will take a cloer look at two of the SPEC benchmark, fpppp and eqntott. Benchmark fpppp ha the highet CPI ratio and the highet intruction ratio of any ofthebenchmark eqntott i jut the revere. Neither one, however, ha the highet or lowet CPI on either machine, and neither ha the highet or lowet RISC factor. Benchmark fpppp ha extraordinary intruction and CPI ratio: the MIPS intruction count i nearly 4 time the VAX count, and the 8700' average CPI i over 10 time the M/2000'! Our meaurement how that thi program ha the highet number of operand pecier per VAX intruction of any benchmark (Figure 3, below), the highet number of load per intruction in both architecture (Table 3), and the highet frequency of oating-point operation on VAX (Table 3). Becaue the number of load i imilar, and the number of oating-point operation nearly identical on the two architecture, it i reaonable to imagine a correpondence between a VAX oating-point intruction and a equence of MIPS intruction. Suppoe the operand are in memory on both architecture. Then the VAX will load it double-preciion operand with operand-pecier microcode, whoe cycle of execution are charged to the oating-point intruction. The MIPS machine will intead do two ingle-cycle 32-bit load intruction per double-preciion operand, followed by a oatingpoint intruction that operate on regiter. Any neceary addre calculation that can be done in operand pecier would further increae the MIPS intruction count and the VAX CPI. If the reult need to go to memory, the VAX will again ue a multiple-cycle operand pecier microroutine and charge the cycle to the oating-point intruction. The MIPS machine will do two ingle-cycle tore, poibly urrounded by addre arithmetic intruction. Compared with the other benchmark, fpppp will ee thee eect more trongly becaue of it large number of load and high denity of (double-preciion) operand pecier. The reult i an unuually high intruction ratio and CPI ratio. If thi were the entire tory, fpppp' RISC factor would be 1.0 and not 2.7. The main explanation i the relative performance of the oating-point hardware. The MIPS implementation i much fater (ee Table 1), and alo allow ome intruction overlap. The VAX pend more than half it CPI in oating-point intruction execution (not counting operand pecier) and ha only trivial intruction overlap. Other poible contributing factor are the eect of the larger number of regiter and the fater MIPS branche (ee below) but ince the number of load i cloe between the two machine, and the number of branche quite mall, we believe thee eect are much maller than the eect of the oating-point hardware. Benchmark eqntott i very dierent from fpppp. It ha the lowet CPI ratio and the lowet intruction ratio of all nine benchmark. In fact the two machine execute almot the ame number of intruction (Table 2). For thi program, then, we need to nd explanation that raie VAX CPI without imultaneouly raiing the MIPS intruction count. VAX operand pecier once again explain a good deal. Eqntott ha the lowet number of operand pecier per VAX intruction of any of the benchmark (Figure 3), and alo ha a very mall number of load and tore (Table 3). So to the extent thatwe can fairly imagine a VAX intruction mapping into ome equence of MIPS intruction, what i happening here i exactly the oppoite of what happened in fpppp. That i, operand pecier proceing doe not correpond to extra MIPS intruction very often. Alo, the frequent ue of regiter increae VAX CPI without increaing MIPS intruction count becaue the 8700 uually ue a eparate cycle for each regiter operand. A two-regiter integer add, for example, take one intruction on both architecture, but three cycle on the VAX 8700 veru MIPS' one. Although the number of load i mall, VAX doe almot twice a many a MIPS, raiing the VAX CPI and providing evidence that thi benchmark benet from the larger number of regiter in MIPS. Finally, both

7 I N S T rdoduc r pice2g6 fpppp rmatrix300 rnaa7 R rli repreo A reqntott 1 T I O OPERAND SPECIFIERS PER VAX INSTRUCTION r tomcatv r Figure 3: The correlation between the number of operand pecier per VAX intruction and the intruction ratio implementation of eqntott branch very frequently, which i relatively bad for VAX CPI, ince imple branche take more cycle on the VAX Architectural factor with compenating inuence We will now conider more cloely the factor we have encountered in looking at fpppp and eqntott, beginning with thoe that have compenating inuence on the two architecture: about the ame cot in MIPS intruction and VAX CPI. VAX operand pecier: load and tore. Mot VAX memory reference and load of immediate data are done by operand pecier microcode. Some of thee are quite imple, loading a ingle I-tream contant, ay, or uing the content of a regiter to addre memory. The MIPS architecture would need to ue eparate load and tore intruction to accomplih the ame function. Some pecier do variou kind of addre calculation (indexing, auto-increment, and o on) that take multiple VAX cycle and would correpond to multiple MIPS intruction. And nally, doublepreciion operand are loaded and tored by ingle(twocycle) operand pecier on VAX, where they would (in the imple cae) taketwo intruction on MIPS. The average number of operand pecier per VAX intruction i in fact correlated with intruction ratio, a hown in Figure 3. Fancy VAX intruction: neceary functionality. Some VAX intruction perform function more ophiticated than MIPS can accomplih in a ingle intruction. Loop control intruction, for example, increment the loop index, tet it againt a limit, and do a conditional branch. When the ame or a imilar function i required on MIPS, it will ue multiple intruction. If the VAX microcode and the MIPS equence ue the ame algorithm, we have, again, compenating eect on intruction ratio and CPI ratio. 4.3 Architectural factor favoring MIPS A number of factor contribute to the conitent net advantage of the M/2000. Mot reult in increaed VAX CPI, and two (number of regiter and branch diplacement ize) can alo inate the VAX intruction count. Operand pecier decoding. The VAX 8700 (and mot other model) uually take at leat one cycle to proce each operand pecier. When the pecier reference memory, there i a compenating inuence on MIPS intruction count. But for regiter and literal pecier, thi imply mean more VAX CPI without a matching eect on MIPS. A three-regiter integer add, for example, take four cycle on the 8700 but jut one on the MIPS machine. Number of regiter. The MIPS architecture ha 32 (32- bit wide) general regiter and 16 (64-bit wide) oatingpoint regiter VAX ha 15 (32-bit wide) general regiter that can be ued for both integer and oating-point data. Thi can obviouly lead to more memory reference on the VAX (done either with operand pecier, or with intruction, if an operand i to be loaded into a regiter and reued, or a reult aved), while having no compenating eect on MIPS. Thee extra memory reference take cycle to execute and may cot till more cycle if they mi in the cache or tall for ome other reaon. Floating-point hardware and intruction overlap. The ue of a large and eparate et of oating-point regiter help MIPS, epecially in late-1980 CMOS, where the oatingpoint unit i not in the ame chip a the CPU. Floating point operation can be performed without requiring data to be moved between chip. In a VAX microproceor implementation uch a the 6000/400 or the 4000/300, everal cycle are required to move both ource operand from the CPU into the FPU, and read the reult back into the CPU. For example, in thee VAXe the actual oating-point multiply take only ve cycle inide the FPU compared to the fteen cycle required for the entire multiply intruction. Since VAX ue the ame regiter for integer and oating point, ignicant overlapping of intruction would require complex regiter coreboarding. Thu the conguration of regiter i an architectural dierence with ignicant performance conequence when the FPU i not integrated within thecpu.having only regiter detination for oating-point intruction i another uch dierence becaue of thi it i much eaier to overlap execution of multi-cycle intruction on MIPS. Simple jump and branche. The time for the implet taken branch (or unconditional jump) on the VAX 8700 i ve cycle. On MIPS, which ha a delayed branch, it i one cycle if the delay lot i lled, and two otherwie. Thi dierence i due in large part to the VAX condition code, which are et in a late pipeline tage and inuence the earliet pipe tage (intruction decode) when a conditional branch i done, thereby creating a pipeline bubble. Thi bubble cannot be lled by other non-branch intruction becaue the condition code are et by almot every VAX intruction [9]. Thi in turn mean that adding an intruction cache would not pay unle branch prediction hardware were added too. The rarer unconditional jump could prot from an I-cache, but thi wa not reaon enough to jutify one in the 8700, and o thee jump alo take ve cycle. MIPS conditional branche intead ue the condition of a regiter, which i read in an early pipe tage, and which, of coure, i not changed by intruction inerted between the write of the regiter and the branch. Independent of the ue of the MIPS branch-delay lot, which we regard a a eparate eect (ee below), the lower branche cot VAX CPI. Dierent VAXe may have dierent implementation of the branch intruction, of coure, but it i dicult to ee how anyvax could achieve the MIPS peed without lot of extra hardware (e.g., branch prediction). Fancy VAX intruction: unneceary overhead and wated generality. Some complex VAX intruction imple-

8 ment functionality that i imply not needed, or i too general, or both. Perhap in ome of thee cae the VAX compiler could ue impler intruction, but where they do not, we have an eect on VAX CPI with no increae in MIPS intruction count. The claic example of thi i the VAX procedure call and return intruction. Sometime the extra overhead include memory reference, a in the procedure intruction, where regiter are ometime aved and retored needlely. Intruction cheduling: lled delay lot. The MIPS architecture allow intruction to be inerted in code poition that might otherwie be lot to pipeline delay. The intruction after a conditional branch i alway executed and the intruction after a load can do anything except reference the loaded regiter [19]. Thi ability i not preent inthevax architecture (although the 8700 microcode ue both delay lot when it can). Sometime the branch-delay or loaddelay lot cannot be ued, and mut be lled by a NOP. But when the delay lot i lled by a ueful intruction, the eect i a relative decreae in MIPS CPI. Tranlation buer. The MIPS architecture ha a much larger page ize, which mean, among other thing, that a MIPS TLB can map much more memory than a VAX TLB with the ame number of entrie. (The M/2000' mall TLB map one-half the memory of the 8700' much larger TLB.) Alo, MIPS TLB entrie are tagged with a proce ID, which mean that the TLB need not be uhed on a proce context witch. The uual arrangement onvaxe i to uh the proce half of the TLB on a context witch. Branch diplacement ize. Simple conditional branch intruction have 8-bit PC diplacement in the VAX architecture, and eectively 18-bit one in MIPS. When 8 bit i too few and 18 i enough, a VAX program will ue an extra intruction. 4.4 Architectural factor favoring VAX There are in fact twoarchitectural feature that favor VAX in thi comparion. Neither appear to have a ignicant eect in the SPEC benchmark. Big I-tream contant. The VAX architecture include addre diplacement and abolute addree of 32 bit, and immediate data of whatever ize the opcode demand. It i poible to implement the delivery of a 32-bit I-tream contant o that it i a fat a the delivery of a 16-bit or 8-bit contant. When a big diplacement, abolute addre, or large data contant ineededby the program but not available in a regiter, the MIPS architecture would ue two intruction in the imple cae, veru the VAX' one-cycle operand pecier. Not-taken branche. VAX implementation can eaily make not-taken conditional branche execute in one cycle (the 8700 doe thi). The MIPS architecture require the execution of one intruction after a conditional branch, and when that intruction i a NOP, the eective cot of the branch itwo cycle. 4.5 Variance of the RISC factor No ingle phenomenon explain the variance of the program' RISC factor around the mean of 2.66, but there are a couple of uggetive eect. The oating-point benchmark do relatively better on the VAX, the integer one on MIPS. However, the percentage of oating point (Table 3) eem not to be relevant: the lowet RISC factor, for example, i attached to the program (pice) with the mallet amount of oating point (leaving out the integer benchmark) the bigget oating-point percentage go with program with mean RISC factor (fpppp and tomcatv). All of the oatingpoint benchmark are written in Fortran and all the integer one in C, o in fact we can't dientangle the contribution of the compiler dierence from the contribution of oating point, but it eem likely to u that the eect of the compiler by itelf i mall. Both machine' cache behavior eem looely correlated with RISC factor, a i hown in Table 4. The D-tream cache mi ratio, epecially in the VAX, fall a the RISC factor rie, with a few exception in each architecture. There are ome peculiaritie of the two program with extreme RISC factor. Li ha the highet RISC factor, and tand out from the other benchmark in everal way: it ha the lowet (VAX) and econd-lowet(mips) D- tream cache mi ratio it pend the greatet percentage of it VAX cycle in the procedure call and return intruction (28 percent of all cycle, compared with the econd-highet value, 7.5 percent, for epreo) and it ha by far the highet proportion of addreunaligned memory reference in the VAX, which are handled by cotly microcode trap in the Spice ha the lowet RISC factor, and it own pecularitie. Saavedra-Barrera ha oberved that the particular input circuit ued in the SPEC verion caue pice to pend an unuually large amount of time in one mall integer routine [28]. We have already een that pice ha the highet D- tream mi ratio, with the MIPS value being quite high (26.9 percent). It alo ha the lowet number of load per intruction on MIPS, o that the high mi ratio hurt le than it otherwie might. 5 Concluion We now peculate briey on future implementation direction for each architecture, and then ummarize the paper. 5.1 Future CPI i a function of a computer' architecture, but alo of it hardware implementation, of coure. The VAX 8700 deigner trove to minimize cycle time at the poible expene of cycle per intruction, uing a traightforward pipelined microengine. It i poible to reduce VAX CPI further by adding gate (and complexity and cot). High-end VAX implementation uch a the model 8600 [8, 10] and 9000 [15, 12] attempt to do jut that. The model 9000, in particular, ue a large amount of logic (roughly one million gate-array gate for the ytem [1]) to achieve the lowet CPI of any VAX, a hown in Figure 4. The CPI improvement i the highet for the oatingpoint benchmark. The VAX 9000 attempt to iue imple (but multi-pecier) VAX intruction at the rate of one per cycle, and include the neceary regiter coreboarding and other hardware feature to allow ubtantial oating-point intruction overlap. The reult i a demontration that a large number of gate can yield a VAX implementation with

9 C P I VAX 8700 VAX 9000 pice2g6 matrix300 naa7 fpppp tomcatv doduc epreo eqntott li geo. mean Figure 4: CPI on two VAX implementation cycle per program comparable to a imple RISC implementation. It eem likely, however, that uch an implementation would not be able to achieve the cycle time that a RISC deign could, in the ame technology. A gate denitie increae, it i conceivable that ome future ingle-chip CMOS VAX implementation might achieve CPI number that are cloe to the VAX 9000'. Jut a VAX CPI can be improved by the gate-intenive approach of the model 9000 deign, o RISC CPI can be improved by upercalar or uperpipelined deign [18, 29]. The IBM RISC Sytem/6000 [17], for example, ha a peak iue rate of four intruction per cycle. So while VAX may \catch up" to current ingleintruction-iue RISC performance, RISC deign will puh on with earlier adoption of advanced implementation technique, achieving till higher performance. The VAX architectural diadvantage might thu be viewed a a time lag of ome number of year. 5.2 Summary and caveat In thi paper we have attempted to iolate architecture from implementation in our examination of organizationally imilar RISC and CISC engine. The RISC, the MIPS M/2000, ha ignicantly higher architecturally-determined performance than the CISC, the Digital VAX 8700, on the SPEC benchmark. We oberved a wide variability in both intruction ratio and CPI ratio, but found that thee two ratio are correlated. A the following table how, the pan of the net performance advantage what we called the RISC factor i ignicantly narrower than the pan of either ratio: min geo. mean max VAX CPI MIPS CPI CPI ratio (VAX/MIPS) Int. ratio (MIPS/VAX) RISC factor We examined a number of architectural factor that help Three caveat go along with our reult. Firt, we cannot eaily dientangle the inuence of the compiler from the inuence of the architecture. Thu, trictly peaking, our reult do not compare the VAX and MIPS architecture per e, but rather the combination of architecture with compiler. We have aumed that the compiler quality (in term of generated code peed) i the \ame" for both, while at the ame time demontrating occaional intance of quality difference. So contrary to our aumption, it may very well be that compiler dierence, not architecture, are reponible for ome of the performance dierence we meaured. Second, we meaured a rather mall number of program. Meaurement that attempt to characterize machine broadly hould be baed on much more data. It would be deirable, too, to have a wider variety of programming language and application repreented in the et. Finally, wehave looked in thi paper at application-level proceor performance only. At the ytem level, other architectural factor may aect relative performance. Anderon et al. [3] have recently tudied ome operating ytem primitive and found that the performance of thee primitive on RISC, a compared to VAX, ha not caled with application program performance. And of coure the I/O ytem will determine the performance of ome program, quite independent of proceor architecture. But while our quantitative reult maychange omewhat a compiler evolve, a more program are meaured, and a operating-ytem eect are included, we believe that the fundamental nding will tand up: from the architectural point of view (that i, neglecting cycle time), RISC a exemplied by MIPS oer a ignicant proceor performance advantage over a VAX of comparable hardware organization. Acknowledgment. We would like to thank Rajeh Kothari and Simon Steely for their aitance in performing the meaurement, Earl Killian for providing cache imulation reult for the M/2000, and John DeRoa, Joel Emer, Bob Sproull, Bob Supnik, and an anonymou referee for their comment on an earlier draft of thi paper. explain the variance of the ratio, and the overall advantage of MIPS.

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