L1 Tracking Trigger. Baseline per il Technical Proposal Sviluppo di un System-Demonstrator per il TDR (2016) usando tecnologie state-of-the-art

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1 Scopo: L1 Tracking Trigger Ricostruzione in tempo reale O(5µs) di tutte le tracce con pt>2 GeV con l Outer Tracker (R>20 cm) Utilizzo delle tracce assieme ad altre primitive (Muoni, Calorimetri) per il Trigger di L1con una latenza <10 µs e L1-Accept rate <1MHz Come? Elettroni, Muoni, Tau, Jet, Missing ET, fotoni isolati Riduzione on-detector con moduli ad-hoc (pt-modules) Uso di memorie associative (AM) per velocizzare la pattern-recognition e di FPGA per il track fit Stato in CMS Baseline per il Technical Proposal Sviluppo di un System-Demonstrator per il TDR (2016) usando tecnologie state-of-the-art 1

2 Uso del Tracker nel L1 Trigger Technical Content: Track Trigger Simulation studies demonstrate addition of L1 tracking trigger provides significant reductions in rate with good efficiency for physics objects. Trigger, Threshold Single Muon, 20 GeV Algorithm Rate reduction Full eff. at the plateau Improved Pt, via track matching ~ 13 (central region) - Track Trigger Integration group, E. Perez, A. Ryd Comments ~ 90 % Tracker isolation may help further. Single Electron, 20 GeV Match with cluster > 6 (current granularity) >10 (crystal granularity) (! < 1 ) 90 % Tracker isolation can bring an additional factor of up to 2. Single Tau, 40 GeV Single Photon, 20 GeV Multi-jets, HT CaloTau track matching + tracker isolation O(5) O(50 %) (for 3-prong decays) Very preliminary. Work in progress. IMPORTANT! Tracker isolation 40 % 90 % Probably hard to do much better. Require that jets come from the same vertex Performances depend a lot on the trigger & threshold. 2 O. Buchmueller, Imperial College, W. Smith, U. Wisconsin, October 25, 2013 CMS Upgrade Plenary: L1T & HLT - 8

3 Cosa facciamo a Pisa e in Italia? Studi di performance e simulazione (L. Martini, E. Gallo (Fi), R. Dell Orso, F. Palla) Suddivisione in settori di trigger, dimensioni delle banche di AM in funzione dei parametri del chip e del pt minimo delle tracce. Simulazione di performance per tracce (fake rate e efficienze) e canali di fisica (dopo che il codice verrà integrato in CMSSW) Sviluppo di una mezzanina per la pattern recognition e il track fitting (D. Magalotti (Pg), L. Servoli (Pg)) Sviluppo di firmware per il data formatter e/o il data organizer (G. Magazzù, + Ts?) 3

4 1 Pattern Recognition AM chips STUBS Data Organizer 2 Roads 3 Track Fitter L1 Tracks FPGA

5 INFN Hardwareas of interest (1) Hardware Develop and build novel Mezzanine concept Develop Perform and build pattern novel Mezzanine recognition concept and track fitting integrating a! Perform FPGA pattern and AM recognition chips and track fitting integrating a FPGA and AM chips Equip with latest version of the AM chip available (tbd)!" #$%&'()*+&)',-'.-+-/'0&123+%&-4$+0&50-'.-6789:6;! Equip Experience with!"#$%&'(&")*"'+(",!-./,0"12"3+%&%3'(&14(5"')"162(&'"'+("7&%38"91''16:");(&%'1)6"51&(3'<="6(%&"'+( latest version in programming of the AM AM chip chip available (tbd)!-"3+1;"16215("'+("2%>("?)%&5@ Aree di interesse INFN (1)! Experience Interest A("&(3(1B("16"16;$'"C"2(&1%<"?$2"'+&)$:+"'+("3(6'&%<"3)66(3')&"D1'+"%"216:<("90E!@ in to programming develop FPGA AM chip firmware! Interest Interests to develop in new FPGA Track firmware fitting algorithms );(&%'1)6@"7+(")$';$'"5%'%"12"2(65"16")$';$'"*&)>"'+("3)66(3')&@! Interests in new Track fitting algorithms 7+12"90E!">%6%:("'+12"16;$'"5%'%"%65"512'&1?$'("'+(>"')"'+("%<<"!-F+1;"%<D%=2"D1'+"2(&1%<"<168@ 7+(")$';$'"5%'%"&)%5"*&)>"'+("!-3+1;"12"&(3(1B(5"?="'+("90E!"%65"3)>;<('("'+("'&%38"*1''16: 5

6 Simulation Aree di interesse INFN (2) Pattern bank size as a function of the system parameters, like: Lower pt threshold Number of Don t Care (DC) bits Sector size Data Organizer simulation Data flow Efficiency and data losses vs parameters of the system Cross-coordinate with the HW experts Impact of the system parameters on dimuons final states Possible use cases J/ψ µµ, B µµ, Z µµ Isolation, vertexing and mass resolution 6

7 BACKUP

8 CMS Upgraded Tracker Layout Outer Tracker 2S (Strip-Strip) Pt modules PS (Pixel-Strip) Pt modules NEW! L1 Latency 10 µs L1A rate 1 MHz HLT rate 10 khz Pixel Option 7004 PS modules (60% in the barrel) S modules (50% in the barrel) Better (40%) pt resolution than current tracker and smaller material budget Good vertexing performance for Outer Tracker only (for L1 Trigger) Material Budget CMS Upgrade Pixel 8

9 Select only hits from high-p T tracks Send data from relatively high-p T tracks (>2 GeV) by correlating hits in 2 nearby sensors. F. Palla, G. Parrini, PoS VERTEX2007 (2007) 034, 057/034/Vertex%202007_034.pdf J. Jones, A. Rose, C. Foudas, G. Hall, Ø In the barrel, ΔR is given directly by the sensors spacing Ø In the end-cap, it depends on the location of the detector End-cap configuration typically requires wider spacing (up to ~ 4 mm) R z ΔR Δz = ΔR / tg ϑ 9

10 p T modules type 5 cm long strips (both sides) 90 µm pitch P = 2.72 W ~ 92 cm 2 active area Efficiency Barrel Stub Prod. Eff. given Digi Layer 1 Layer 2 Layer 3 Layer 4 Layer 5 Layer 6 2S Pions (Barrel) TrackingParticle p [GeV/c] T Endcap Stub Prod. Eff. given Digi 2.4 cm long strips + pixels 100 µm pitch P = 5.01 W ~ 45 cm 2 active area PS Efficiency Pions (Endcaps) Disk 1 Disk 2 Disk 3 Disk 4 Disk TrackingParticle p T [GeV/c] 10

11 Possible trigger architecture 8(r-ϕ)x6(r-z) trigger sectors Nearly 200 stubs/sectors - 6 layers and 140 pileup To be compared with ~ 1000 from FTK with 5 strip layers and 70 pileup Two track findings under investigation i. Associative Memory (pattern recognition) + FPGA (track fitting) ii. FPGA boards (pattern recognition + track fitting) 11

12 Track fitting - high quality helix parameters and χ 2 Principal component analysis (Other techniques under consideration) Over a narrow region in the detector, equations linear in the local silicon hit coordinates give resolution nearly as good as a time-consuming helical fit. Nucl.Instrum.Meth.A623: ,2010 doi: /j.nima piʼs are the helix parameters and 2 components. xjʼs are the hit coordinates in the silicon layers. aij & bi are pre-stored constants determined from full simulation or real data tracks. The range of the linear fit is a sector which consists of a single silicon module in each detector layer. This is VERY fast in FPGA DSPs. ~3000 fitting engines/trigger sector for CMS 12

13 Data flow 200 ns <5 µs Latency Modules 400 FEDs 3.2 Gbps Module FED Gbps 4 Tbps Switches Sector Processors Evt 1 Evt 2 Evt 3 Sector 1 FED FED A switch time multiplexes events to different sector processors A FED receives stub info, adds geographical info and routes to sector processors Evt 1 Evt 2 Evt 3 Sector 12

14 CMS: toward a demonstrator Input Data Board x 8 Up to 48 pairs of connection, Bidirectional. One Trigger Tower Pattern Recognition Board x 4 Up to 48 inputs with 3.25Gbps each With 40G full-mesh backplane Up to 48 pairs of connection, Bidirectional. 10Gbps each HH UU BB I N A M With 40G full-mesh backplane Could also be pure FPGA based approach 14

15 15,000 modules/48 towers = 312 modules/tower on average Each board is capable to receive data from up to 48 modules at 3.25Gbps, with total 156 Gbps per Board/RTM. 8 boards can receive up to 384 modules (one trigger tower worth) The input data is then divided into 4 time slices, each slice is sent to 1 of 4 Pattern Recognition board, with 40Gbps full-mesh (4x40=160Gbps > 156Gbps). Phi Eta Each Pattern Recognition board receives up to 8 x 40Gbps = 320 Gbps input data over full Mesh backplane. The events can then be time multiplexed on board for each mezzanine to handle (x1, x2, x4 possible, flexible). Each board send out its output from RTM to next stage for each time slice. Also communicate with other boards in other crates for data sharing in phi & eta for each time slice

16 Tower interconnections φ Neighbors data sharing 48 x 10 Gbps bidirectional η 16

17 The actual prototype design (Pulsar IIa) design goal: I/O capability reachingrtm ~ 1 Tbps Mother Board

18 The actual prototype design (Pulsar IIa) design goal: I/O capability reachingrtm ~ 1 Tbps Mother Board FPGA (Kintex7)

19 The actual prototype design (Pulsar IIa) design goal: I/O capability reachingrtm ~ 1 Tbps Mother Board FPGA (Kintex7) FMC Connector

20 The actual prototype design (Pulsar IIa) design goal: I/O capability reachingrtm ~ 1 Tbps Mother Board FPGA (Kintex7) FMC Connector ZONE2 Connector for ATCA fabric

21 The actual prototype design (Pulsar IIa) design goal: I/O capability reachingrtm ~ 1 Tbps Mother Board ZONE3 Connector FPGA (Kintex7) FMC Connector ZONE2 Connector for ATCA fabric

22 The actual prototype design (Pulsar IIa) design goal: I/O capability reachingrtm ~ 1 Tbps Mother Board ZONE3 Connector 8 Quad SFP+ 40 Gbps each FPGA (Kintex7) FMC Connector ZONE2 Connector for ATCA fabric 6 SFP+ 10 Gbps each

23 The actual prototype design (Pulsar IIa) design goal: I/O capability reachingrtm ~ 1 Tbps Mother Board ZONE3 Connector 8 Quad SFP+ 40 Gbps each FPGA (Kintex7) FMC Connector ZONE2 Connector for ATCA fabric 6 SFP+ 10 Gbps each

24 CMS Gains for µ, e Triggers (over Phase 1 Trigger, " < 1 ) S. Dutta, A. Modak, A. Savin µ Present e/!, WP = 90% efficiency x 10 for E T > 20 GeV $ P.L. Zotto # x 6 for E T > 20 GeV Matching Drift Tube trigger primitives with L1Tracks: large rate reduction: > 10 at threshold > ~ 14 GeV. Normalized to present trigger at 10 GeV. Removes flattening at high P t Rate reduction brought by matching L1 e/! to L1Track stubs for " < 1. Red: with current (5x5 xtal) L1Cal granularity. Green : using single crystal-level position resolution improves matching 18 O. Buchmueller, Imperial College, W. Smith, U. Wisconsin, October 25, 2013 CMS Upgrade Plenary: L1T & HLT - 9

25 Tracking Isolation: Higgs to!! E. Perez O. Buchmueller, Imperial College, W. Smith, U. Wisconsin, October 25, 2013 CMS Upgrade Plenary:19 L1T & HLT - 10

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