Atmel MSL3040/41/50/60/80/86/87/88 Programmers Guide

Transcription

1 Atmel MSL3040/41/50/60/80/86/87/88 Programmers Guide 4-String 120mA 5/6/8-String 60mA LED Drivers with Integrated Boost Controller Phase Shifted Dimming APPLICATION NOTE Description: MSL3040/41/50/60/80/86/87/88 LED drivers offer a complete solution to drive up to eight parallel LED strings at up to 40V. LED current sinks of the MSL3050, MSL3060, MSL3080, MSL3086, MSL3087, MSL3088 control up to 60mA each, the MSL3040 MSL3041 current sinks control up to 120mA each, for up to 19W of LED power. MSL3050, MSL3060 MSL3080 allow parallel driver connection, increasing string current capability. A single resistor sets LED current with string matching accuracy within ±3%. Each driver varies by the number of current sinks features (see Table 1 below). Basic features include integrated boost regulator controller, PWM circuitry that allows up to 4095:1 dimming, phase-shifted LED PWM dimming, up to eight LED drive outputs, integrated or separate duty cycle frequency control inputs, a 1MHz I 2 C compatible serial interface internal registers for PWM dimming control. Additionally, integrated fault detection circuitry acts on string opencircuit LED short circuit faults, boost regulator over-voltage faults, die over-temperature faults. proprietary Efficiency Optimizer minimizes power use while maintaining proper LED current, supports interconnecting multiple drivers to power more than eight strings while maintaining optimum efficiency. Table 1. LED Driver Parts Comparison MAX CURRENT PER STRING PHASE SHIFTED STRING DRIVERS RESISTOR SET LED SHORT CIRCUIT THRESHOLD PART NUMBER OF LED STRINGS INTERNAL BOOST CONTROLLER SEPARATE SYNC INPUT*** BEST FOR MSL mA YES YES YES NO MONITOR, INDUSTRIAL PANEL MSL3087* 8 60mA YES NO YES NO SMALL TV MSL mA YES YES NO YES SMALL TV 8 60mA NO YES YES NO MONITOR, INDUSTRIAL PANEL MSL3080 4** 120mA NO YES YES NO MONITOR, INDUSTRIAL PANEL 2** 240mA NO YES YES NO MONITOR, INDUSTRIAL PANEL 1** 480mA NO YES YES NO MONITOR, INDUSTRIAL PANEL MSL3040* 4 120mA YES YES YES NO MONITOR, AUTOMOTIVE MSL3041* 4 120mA YES YES YES YES MONITOR, AUTOMOTIVE MSL3050* 5 60mA NO YES YES NO INDUSTRIAL PANEL 1** 300mA NO YES YES NO INDUSTRIAL PANEL 6 60mA NO YES YES NO MONITOR, INDUSTRIAL PANEL MSL3060* 3** 120mA NO YES YES NO MONITOR, INDUSTRIAL PANEL 2** 180mA NO YES YES NO MONITOR, INDUSTRIAL PANEL 1** 360mA NO YES YES NO MONITOR, INDUSTRIAL PANEL * Future product, contact factory for information. ** Drivers without phase shift allow parallel connection of string drive outputs for increased string current. *** Drivers with separate SYNC input expect two input control signals, one for dimming duty cycle one for dimming frequency. 1 DBIE

2 Table of Contents 1.0 Document Scope Hardware Basic Operation I²C/SMBus Compatible Serial Interface Overview & Timing I 2 C Bus Timeout I 2 C Bit Transfer I 2 C STOP Conditions I 2 C STOP Conditions I 2 C Slave Address I 2 C Message Format for Writing to the MSL3040/41/50/60/80/86/87/ I 2 C Message Format for Reading Registers Register Map Register Details System Control Register 0x Fault Enable Register 0x String Fault Enable Register 0x Short Circuit Threshold Control Register 0x Fault Status Register 0x String Open Circuit Status Register 0x String Short Circuit Status Register 0x String Enable Status Register 0x Boost/Boot-Load Status Register 0x Efficiency Optimizer DAC Readback Register 0x0C Efficiency Optimizer Status Register 0x0D PWM Control Register 0x PWM Frequency/Phase Registers 0x11 0x PWM Duty Cycle Registers 0x13 0x Reserved registers 0x20-0x Sleep Registers 0x7F Efficiency Optimizer Control Registers 0x84 0x85*

3 1.0 Document Scope This MSL3040/41/50/60/80/86/87/88 Programmers Guide is an addendum to the datasheets MSL3040/MSL3041, MSL3050/MSL3060/MSL3080 MSL3086/MSL3087/MSL3088, gives detailed information instructions on how to configure, monitor, control the LED drivers through the I 2 C compatible serial interface. se drivers operate without I 2 C serial port access; using the serial port allows access to advanced features, dimming modes, fault detection monitoring modes, test debug features. All registers are volatile reset when power is removed, when the driver is turned off by the hardware enable input (EN), or when automatically shut-off due to an over-temperature event. If a configuration other than the default programmed configuration is used, it must be loaded each time the driver is turned on. Note that non-stard configurations are available from the factory, contact the factory for information. Register default values for each driver are listed in the Register Details section where appropriate. 3

4 2.0 Hardware MSL3040/41/50/60/80/86/87/88 Programmers Guide Hardware Figure 1.1: LED Driver Block Diagram Figure 1. LED Driver Block Diagram Basic Operation All MSL30xx drivers, except the MSL3087, include a boost regulator controller to make a voltage, V LED, that powers the LEDs. boost regulator accepts an input voltage of 5V to 32V boosts it up to a maximum of 40V (limited by the voltage st-off rating of the STRn driver outputs). V LED is controlled by a resistive voltage divider, R TOP R BOTTOM in Figure 1 above, connected to the controller feedback input FB. Efficiency Optimizer monitors LED driver voltage drives FB to control the V LED voltage to minimize power use while assuring proper LED current. MSL3087 controls an external boost regulator with its Efficiency Optimizer output, FBO, which also allows daisy-chaining with other drivers in the family to drive additional strings from a single optimized power supply. Provision is made for boost regulator control loop compensation via the COMP input. Internally or externally generated PWM dimming signals gate the LED string current-sink outputs STRn (the number of strings vary for different members of the MSL30xx family, Table 1 on page 1). A single external PWM signal connected to the PWM input distributes to all strings via the string drive logic (Figure 1), with most drivers phase shifting the dimming signals (Table 1). additional SYNC input allows separate frequency control for the MSL3088 MSL3041. All drivers allow internal register control of PWM dimming frequency duty cycle (in the place of external inputs) via the I2C compatible serial interface. All parts in this family have Atmel a requirement MSL3040/41/50/60/80/86/87/88 of minimum on time Programmers of 3µs. Guide Page 2 of 15 4

5 3.0 Basic Operation All MSL30xx drivers, except the MSL3087, include a boost regulator controller to make a voltage, V LED, that powers the LEDs. boost regulator accepts an input voltage of 5V to 32V boosts it up to a maximum of 40V (limited by the voltage st-off rating of the STRn driver outputs). V LED is controlled by a resistive voltage divider, R TOP R BOTTOM in Figure 1 above, connected to the controller feedback input FB. Efficiency Optimizer monitors LED driver voltage drives FB to control the V LED voltage to minimize power use while assuring proper LED current. MSL3087 controls an external boost regulator with its Efficiency Optimizer output, FBO, which also allows daisy-chaining with other drivers in the family to drive additional strings from a single optimized power supply. Provision is made for boost regulator control loop compensation via the COMP input. Internally or externally generated PWM dimming signals gate the LED string current-sink outputs STRn (the number of strings vary for different members of the MSL30xx family, Table 1 on page 1). A single external PWM signal connected to the PWM input distributes to all strings via the string drive logic (Figure 1), with most parts in the family phase shifting the dimming signals (Table 1). additional SYNC input allows separate frequency control for the MSL3088 MSL3041. All drivers allow internal register control of PWM dimming frequency duty cycle (in the place of external inputs) via the I 2 C compatible serial interface. All parts in this family have a requirement of minimum on time of 3µs. 5

6 I²C/SMBus Compatible Serial Interface I²C/SMBus Compatible Serial Interface Overview Timing 4.0 I²C/SMBus Overview I 2 C Compatible serial interface Timing Serial allows access Interface to the control status registers. Register Map section shows register definitions I 2 C serial interface the Register allows Details access section to the shows control detailed status register registers. functions Register default Map settings. section shows register 4.1 definitions MSL3040/41/50/60/80/86/87/88 Overview & Timing the Register Details operate section as shows I²C/SMBus detailed slaves register that send functions receive default data settings. to a master. interface is MSL3040/41/50/60/80/86/87/88 needed only to allow control operate monitoring as I²C/SMBus over some slaves functions that send advanced receive features, data to a master. is not required interface for basic is needed operation. I 2 C serial only When interface to allow not allows control using access the serial to monitoring the control interface, over status connect some registers. functions Register advanced to Map GND. section features, shows register is definitions not required the for basic operation. Register Details When section not shows using detailed the serial register interface, functions connect default settings. MSL3040/41/50/60/80/86/87/88 to GND. operate as I²C/SMBus slaves serial that send interface receive is suitable data to a for master. 100kHz, interface 400kHz is needed 1MHz only communication. to allow control monitoring interface over uses some bi-directional functions data lin advanced features, is not required for basic operation. When not using the serial interface, connect to GND. serial clock interface input is suitable to achieve for 100kHz, bidirectional 400kHz communication 1MHz communication. between master interface slaves. uses bi-directional FLTB fault output data lin optionally serial interface clock alerts input the host is suitable system for to 100kHz, achieve to faults. 400kHz bidirectional During 1MHz over temperature communication. between shutdown interface master the serial uses bi-directional slaves. interface data is line FLTB disabled fault clock output regist optionally input settings to are alerts achieve reset the bidirectional to host their system default communication to values. faults. between During master over temperature slaves. shutdown FLTB fault output the serial optionally interface alerts the is host disabled system to registe settings faults. During are over reset temperature to their shutdown default values. the serial interface is disabled register settings are reset to their default values. master, typically a microcontroller, initiates all data transfers, generates the clock that synchronizes the transf master, typically a microcontroller, initiates all data transfers, generates the clock that synchronizes the transfers. operates as both master, operates an input typically as both an open-drain a an microcontroller, input an output. operates initiates open-drain only all as data output. a slave transfers, operates input (master output), generates only as a does the slave not clock input perform that (master clock-stretching. synchronizes output), Use the transfe doe not perform pull-ups operates clock-stretching. on, as both FLTB. an input Use pull-ups an open-drain on, output. FLTB. operates only as a slave input (master output), doe not perform clock-stretching. Use pull-ups on, FLTB. Figure 4.1: I 2 C Interface Connections Figure 2. I 2 C Interface Connections Figure 2. I 2 C Interface Connections A transmission consists consists of a of a condition sent condition by a master, sent a by 7-bit a slave master, address a 7-bit plus slave one R/W address bit, an acknowledge plus one R/W bit, none bit, an or many acknowledg data bytes each separated by an acknowledge bit, a STOP condition (Figure 4.2, Figure 4.3 Figure 4.4). A bit, transmission none or many consists data bytes of a each separated condition by sent an by acknowledge a master, a bit, 7-bit slave a STOP address condition plus one (Figure R/W bit, 3, Figure an acknowledge 4 Fig bit, 5). Figure none 4.2: or I 2 C many Serial data Interface bytes Timing each Details separated by an acknowledge bit, a STOP condition (Figure 3, Figure 4 Fig 5). t BUF t SU:DAT t SU:STA t HD:STA t SU:STO t BUF thd:dat t SU:STA t HD:STA t SU:STO t SU:DAT t LOW t LOW t HIGH t HD:STA t HIGH t R t F thd:dat t R t F CONDITION REPEATED CONDITION REPEATED CONDITION Page 3 of 15 CONDITION STOP CONDITION CONDITION CONDITION Figure 3. CONDITION I 2 C Serial Interface Timing Details 4.2 Figure I 2 C Bus 3. Timeout I 2 C Serial Interface Timing Details I 2 C Bus Timeout bus timeout feature (register 0x02 bit D7) allows the MSL3040/41/50/60/80/86/87/88 to reset the serial bus interface if a communication Iceases 2 C Bus bus before timeout Timeout a STOP feature condition (register sent. If 0x02 either bit D7) or allows is low the for MSL3040/41/50/60/80/86/87/88 more than 30ms (typical), then the transaction to reset terminates, the serial bus interfa releases the interface waits another condition. a communication bus timeout feature ceases (register before a 0x02 STOP bit D7) allows is the sent. MSL3040/41/50/60/80/86/87/88 If either or is low for to more reset than the 30ms serial (typical), bus interfac the a the communication transaction terminates, ceases before a releases STOP condition the interface is sent. If waits either for another or is low condition. for more than 30ms (typical), the the transaction terminates, releases the interface waits for another condition. I 2 C Bit Transfer STOP IOne 2 C Bit data Transfer bit is transferred during each clock pulse. Ensure is stable while is high. One data bit is transferred during each clock pulse. Ensure Page 3 of 15 is stable while is high. 6

7 4.3 I 2 C Bit Transfer MSL3040/41/50/60/80/86/87/88 Programmers Guid MSL3040/41/50/60/80/86/87/88 Programmers Guide One data bit is transferred during each clock pulse. Ensure is stable while is high. Figure 4.3: I 2 C Bit Transfer Figure 4. I 2 Bit Transfer Figure I 2 4. I C 2 C Bit Transfer STOP Conditions I 2 C STOP Conditions Both remain high when the interface is free. master signals a transmission with a condition b transitioning from high to low while is high. When the master has finished communicating with the slave, it Both remain high when the interface is free. master signals a transmission with a condition by transitioning from I 2 C high to low while STOP is high. Conditions When the master has finished communicating with the slave, it issues a STOP condition by transitioning Both from low to high while remain high is high. when the bus interface is then free. is free. master signals a transmission with a condition by by transitioning from high to low while is high. When the master has finished communicating with the slave, it it Figure issues 4.4: a STOP I 2 C condition STOP by by transitioning Conditions from from low low to high to high while while is high. is high. bus is is then bus is free. then free TRANSMITTER TRANSMITTER RECEIVER RECEIVER CONDITION CONDITION NOT ACKNOWLEDGE BY NOT RECEIVER ACKNOWLEDGE BY RECEIVER ACKNOWLEDGE BY RECEIVER ACKNOWLEDGE BY RECEIVER Figure 5. I 2 C STOP Conditions 4.5 I 2 C Acknowledge Bit Figure 5. I 2 C STOP Conditions acknowledge bit is a clocked 9th bit which the recipient uses to hshake receipt of each 8-bit byte of data. master generates I 2 C Acknowledge Bit the 9th clock pulse, the recipient holds low during the high period of the clock pulse. When the master is transmitting to the slave, I the 2 C slave Acknowledge acknowledge pulls low bit because is a Bit clocked the slave 9th is bit the which recipient. the When recipient the slave uses is to transmitting hshake to the receipt master, of each the master 8-bit pulls byte of data. low because the master generates is the recipient. the 9th clock pulse, the recipient holds low during the high period of the clock pulse. When the acknowledge bit is a clocked 9th bit which the recipient uses to hshake receipt of each 8-bit byte of data. master is transmitting to the slave, the slave pulls low because the slave is the recipient. When the slave is master Figure transmitting 4.5: generates I 2 C to Acknowledge the master, the 9th the clock master pulse, pulls the low recipient because holds the master low is the during recipient. the high period of the clock pulse. When master is transmitting to the slave, the slave pulls low because the slave is the recipient. When the slave is transmitting to the master, the master pulls low because the master is the recipient. Figure 6. I 2 C Acknowledge Figure 6. I 2 C Acknowledge Page 4 of 15 Phase Shifted Dimming Boost Controller Phase Shifted Dimming 7

8 MSL3040/41/50/60/80/86/87/88 Programmers Guide 4.6 I 2 C Slave Address I 2 C Slave Address have a 7-bit long slave address, 0b , followed by an eighth bit, the R/W bit, that combine to make MSL3040/41/50/60/80/86/87/88 MSL3040/41/50/60/80/86/87/88 have 2 separate 8-bit read write addresses have a 7-bit 7-bit (i.e. the long long slave slave slave addresses address, address, are 0b , 0b , 0xA0 for write followed followed operations by by an an eighth eighth 0xA1 bit, bit, for the the read R/W R/W operations). bit, bit, that that R/W combine combine bit is low to to make make for a write 2 separate separate high 8-bit 8-bit for a read read. All MSL3040/41/50/60/80/86/87/88 write addresses (i.e. (i.e. the the slave slave have addresses addresses the same 0xA0/0xA1 are are 0xA0 slave for for write write address; operations operations when using multiple 0xA1 0xA1 drivers for for read read communicating operations). with R/W them bit through is low for their a write serial interfaces, high high for for make a read. read. external All All MSL3040/41/50/60/80/86/87/88 provision to route the serial interface have have to the the appropriate the same same 0xA0/0xA1 driver. slave address; when using multiple drivers communicating with with them them through through their their serial serial interfaces, make external provision to route the serial interface to to the appropriate driver. Figure 4.6: I 2 C Slave Address A7 A7 = 1 MSB MSB A6 A6 = 0 A5 A5 = 1 A4 A4 = 0 A5 A5 =0 =0 A6 A6 = 0 A7 A7 = 0 R / / W A Figure 7. I 2 C Slave Address 4.7 I 2 C Message Format for Writing to the MSL3040/41/50/60/80/86/87/88 I 2 C write Message Format to the MSL3040/41/50/60/80/86/87/88 for Writing to the contains MSL3040/41/50/60/80/86/87/88 the slave address, the R/W bit cleared to 0, at least 1 byte of information. A first write byte to of the information MSL3040/41/50/60/80/86/87/88 is the register address byte. contains register the address slave address, byte is stored the as R/W a register bit cleared pointer, to 0, 0, determines at at least which 1 byte register of of information. the following byte is first written byte into. of information If the MSL3040/41/50/60/80/86/87/88 is the register address detect byte. a STOP register condition address after the byte register stored address as a byte register received, pointer, then it takes no determines further action which beyond register setting the the following register pointer. byte is written into. If the MSL3040/41/50/60/80/86/87/88 detect a STOP condition after the register address byte is received, then it takes no further action beyond setting the register pointer. Figure 4.7: I 2 C Writing a Register Pointer ACKNOWLEDGE FROM ACKNOWLEDGE SLAVE STOP FROM SLAVE A D D0 A SLAVE ADDRESS, WRITE ACCESS SET REGISTER POINTER TO X THE REGISTER POINTER NOW POINTS TO X; A SUBSEQUENT READ ACCESS READS FROM REGISTER ADDRESS X Figure 8. I 2 C Writing a Register Pointer When no STOP condition is detected, the byte transmitted after the register address byte is a data byte, is placed into the register When pointed no to by STOP the register condition address is detected, byte. To simplify the byte writing transmitted to multiple after consecutive the register registers, address the register byte is pointer a data auto-increments byte, is placed during into each following acknowledge period; further data bytes transmitted before a STOP condition fill subsequent registers. the register pointed to by the register address byte. To simplify writing to multiple consecutive registers, the register pointer auto-increments during each following acknowledge period; further data bytes transmitted before a STOP Figure 4.8: I 2 C Writing Two Data Bytes condition fill subsequent registers. ACKNOWLEDGE FROM ACKNOWLEDGE FROM ACKNOWLEDGE FROM ACKNOWLEDGE FROM SLAVE STOP SLAVE SLAVE SLAVE A D D0 A D D0 A D D0 D0 A SLAVE ADDRESS, WRITE ACCESS SET REGISTER POINTER TO X DATA WRITES TO DATA WRITES TO REGISTER X REGISTER X + 1 THE REGISTER POINTER NOW POINTS TO X + 2; A SUBSEQUENT READ ACCESS BEGINS READING FROM REGISTER ADDRESS X + 2 Figure 9. I 2 C Writing Two Data Bytes Page 5 of 15 8

9 MSL3040/41/50/60/80/86/87/88 Programmers Guid MSL3040/41/50/60/80/86/87/88 Programmers Guide I 2 C Message Format for Reading Registers 4.8 Message Format for Reading Registers IRead 2 C Message the registers Format using for one Reading of two techniques. Registers Read the registers using using one one of two of techniques. two techniques. first technique begins the same way as a write, by setting the register address pointer as shown in Figure 8, includ the STOP first technique condition begins begins (note the the same that same way even way as a though as write, a write, by the setting by final setting the objective register the register address is to read address pointer data, as pointer shown the R/W as in shown Figure bit is 4.7, in first Figure including sent 8, as including the a write STOP because condition the STOP address (note condition that pointer even (note byte though that is the being even final though objective written). the is Follow final to read objective data, the Figure the is R/W to read 8 bit transaction is data, first sent the as R/W by a bit write that is because shown first sent in the as Figure address a write 10, pointer because with byte a new is STAR being condition written). Follow the the slave Figure address, 4.7 transaction this time by that with shown the in R/W Figure bit 4.9, set with to 1 a to new indicate condition a read. n, the slave after address, the slave this initiated time the address pointer byte is being written). Follow the Figure 8 transaction by that shown in Figure 10, with a new with the R/W bit set to 1 to indicate a read. n, after the slave initiated acknowledge bit, clock out as many bytes as desired, separated condition by acknowledge the master initiated bit, slave acknowledges. clock address, out as this many time pointer bytes with the auto-increments as desired, R/W bit set during separated to 1 to indicate each master by initiated master a read. acknowledge initiated n, after period. acknowledges. the slave initiated End the transmission pointer with autoincrements not-acknowledge during bit, followed clock each out by master a stop many condition. initiated bytes as acknowledge desired, separated period. by master End the initiated transmission acknowledges. with a not-acknowledge pointer auto- followed by a acknowledge increments stop condition. during each master initiated acknowledge period. End the transmission with a not-acknowledge followed by a Figure stop condition. 4.9: I 2 C Reading Register Data with Preset Register Pointer Figure 10. I 2 C Figure 10. I 2 Reading Register Data with Preset Register Pointer C Reading Register Data with Preset Register Pointer second read read technique technique is illustrated is illustrated in Figure in Figure Set 11. the Set register the register pointer pointer as shown as in shown Figure in 4.6 Figure without 7 sending without a sending STOP condition, a send STOP a repeated condition, send condition a repeated after the second condition acknowledge after the bit, then second send acknowledge the slave address bit, again then send with the the R/W slave bit set address to 1 to again indicate a read. n clock out the data bytes separated by master initiated acknowledge bits. register pointer auto-increments during each with the R/W bit set to 1 to indicate a read. n clock out the data bytes separated by master initiated acknowledge bits. master initiated acknowledge period. End the transmission with a not-acknowledge followed by a stop condition. Use this technique for buses register with multiple pointer masters, auto-increments because the during read sequence each master is performed initiated in one acknowledge continuous transaction. period. End the transmission with a notacknowledge followed by a stop condition. Use this technique for buses with multiple masters, because the read sequence Figure 4.10: is performed I 2 C Reading in Register one continuous Data Using transaction. a Repeated second read technique is illustrated in Figure 11. Set the register pointer as shown in Figure 7 without sending a STOP condition, send a repeated condition after the second acknowledge bit, then send the slave address aga with the R/W bit set to 1 to indicate a read. n clock out the data bytes separated by master initiated acknowledge bi register pointer auto-increments during each master initiated acknowledge period. End the transmission with a not acknowledge followed by a stop condition. Use this technique for buses with multiple masters, because the read sequence is performed in one continuous transaction. ACKNOWLEDGE FROM SLAVE ACKNOWLEDGE FROM SLAVE A D7 ACKNOWLEDGE REPEATED FROM SLAVE ACKNOWLEDGE FROM SLAVE REPEATED ACKNOWLEDGE NOT ACKNOWLEDGE STOP FROM SLAVE FROM MASTER ACKNOWLEDGE NOT ACKNOWLEDGE FROM SLAVE FROM MASTER ACCESS BEGINS READING FROM REGISTER ADDRESS X + 1 SLAVE 0 1ADDRESS, A D7SET. REGISTER..... D0 A SLAVE 1 ADDRESS, 0 1 A4 A3 A2 A1 1 READ A D7 REGISTER D0 A WRITE ACCESS POINTER TO X READ ACCESS ADDRESS X SLAVE ADDRESS, SET REGISTER SLAVE ADDRESS, READ REGISTER THE REGISTER POINTER NOW POINTS TO X + 1; A SUBSEQUENT READ WRITE ACCESS POINTER TO X ACCESS BEGINS READ READING ACCESS FROM REGISTER ADDRESS ADDRESS X + 1 X Figure 11. I 2 C Reading Register Data Using a Repeated THE REGISTER POINTER NOW POINTS TO X + 1; A SUBSEQUENT REA Figure 11. I 2 C Reading Register Data Using a Repeated D0 A A4 A3 A2 A1 1 A D D0 A STO Page 6 of 15 Page 6 of 15 9

10 4.9 Register Map I 2 C slave ID is 0xA0 for read 0xA1 for write. Do not change bits that are not described. ADDRESS AND REGISTER NAME Configuration Registers FUNCTION REGISTER DATA D7 D6 D5 D4 D3 D2 D1 D0 0x00 strenrg LED String Enables stren[7:0] 0x01 sysctrlrg System Control - eoen - - 0x02 fltenrg Fault Detect Enable I 2 CTimeOutEn bstovflten strscen strocen fboocflten 0x03 strfltenrg String Fault Enable fltenstr[7:0] 0x04 scthctrlrg SC Threshold control - - scqualdly scdbncdly - - scthrshlvl[1:0] Power / Fault Status Registers 0x05 fltstsrg Fault Status fltbdrv bstovfltdet strscdet strocdet fboocfltdet 0x06 strocstsrg String Open Circuit Fault Status stroc[7:0] 0x07 strscstsrg String Short Circuit Fault Status strsc[7:0] 0x08 strenstsrg String Enable Status after auto fault hling strensts[7:0] 0x09 bststsrg Boost/Boot-Load Status adpwmen blrecovdone bldone - - bstovflt bstpwrgood bstsftstrtdone Efficiency Optimizer Status 0x0C eodacrg EO DAC Read back eodac[7:0] 0x0D eostsrg EO Status fboocflt - eodacact eocal eoinitcal PWM Control Registers 0x10 pwmctrlrg PWM Control - dcmsrmode phashft phashftpairs intduty intfreq pwmdrct syncpol 0x11 0x12 freqpharg Internal Frequency Phase freqpha [7:0] freqpha[15:8] actonbst OVFlt 0x13 dutycyc[7:0] dutycycrg Internal Duty Cycle 0x14 freqmul[1:0] - - dutycyc[11:8] actonstr SCFlt 0x20 0x00 Reserved Reserved 0x21-0x0 0x22 0x00 Reserved Reserved 0x23-0x0 Power Management Register 0x7F sleeprg Put part to sleep enable power savings sleep slppwrsv Efficiency Optimizer Control Registers (MSL3087 only) 0x84 eoctrl0rg EO Control Register 0 hdrmstep[1:0] acaldly[1:0] stepdly[1:0] isinkconfdly[1:0] 0x85 eoctrl1rg EO Control Register 1 decrstep[1:0] incrstep[1:0] icalpwm acal100 acalen ichkdis actonstr OCFlt - 10

11 4.10 Register Details following sections describe the MSL3040/41/50/60/80/86/87/88 registers. Factory default settings are listed where appropriate. Where default values differ between driver types, the defaults for each are listed. Bits labelled - are reserved; do not change them, defective operation may result. Bits labelled x are not used, so may be written to with any value without adverse effects on operation. String Enable Register 0x00 ADDRESS AND REGISTER NAME DEFAULT D7 D6 D5 D4 D3 D2 D1 D0 0x00 strenrg stren7 stren6 stren5 stren4 stre3 stren2 stren1 stren0 MSL3040/41 0x0F MSL3050 0x1F MSL3060 0x3F MSL3080/86/87/88 0xFF StrEnn: Set String Enable bits to 1 to enable, clear them to 0 to disable the corresponding LED driver strings. Efficiency Optimizer the fault logic ignore disabled outputs System Control Register 0x01 ADDRESS AND REGISTER NAME DEFAULT D7 D6 D5 D4 D3 D2 D1 D0 0x01 sysctrlrg 0x4E x eoen x x actonbst OVFlt actonstr SCFlt actonstr OCFlt x eoen: Efficiency Optimizer Enable; Set to 1 to enable the Efficiency Optimizer to dynamically control the boost regulator output voltage, Clear to 0 to disable control of the boost regulator output voltage. actonbstovflt: Act On Boost Over Voltage Fault; Set to 1 to turn off all LED strings upon detection of a boost over-voltage condition; this fault is non-latching, strings turn on when the fault goes away. Clear to 0 to ignore boost over-voltage condition. This actonbstovflt bit is ignored when bstovflten (bit D3 of 0x02) = 0. actonstrscflt: Act On String Short Circuit Fault; Set to 1 to turn off LED strings that detect an LED short circuit fault, Clear to 0 to leave LED strings on that detect an LED short circuit fault. Set the short circuit threshold voltage with the Short Circuit Threshold bits D0 D1 of register 0x04. Efficiency Optimizer ignores outputs that are turned off by an LED short circuit fault. This actonstrscflt bit is ignored when strscen (bit D2 of 0x02) = 0. actonstrocflt: Act On String Open Circuit Fault; Set to 1 to stop driving LED strings that are open circuit, Clear to 0 to continue driving LED strings that are open circuit. Regardless of the state of this bit, the Efficiency Optimizer disregards strings that are open circuit. When actonstrocflt is low the phase engine does not re-calculate phase shifts when a string open circuit occurs. actonstrocflt bit is ignored when strocen (bit D1 of 0x02) = Fault Enable Register 0x02 ADDRESS AND REGISTER NAME 0x02 fltenrg 0x8F DEFAULT D7 D6 D5 D4 D3 D2 D1 D0 I 2 CTime OutEn x x x bstovflten strscen strocen fboocflten I 2 CTimeOutEn: I 2 C Time Out Enable. Set to 1 to enable I 2 C bus transaction timeout when the bus is stalled beyond 30ms, Clear to 0 to disallow I 2 C bus time out. bstovflten: Boost Over-Voltage Fault Enable; Set to 1 to have a boost over-voltage fault pull FLTB low, Clear to 0 to not pull FLTB low when a boost over-voltage faults occurs. This fault is non-latching. StrSCEn: String Short Circuit Fault Enable; Set to 1 to have LED short circuit faults pull FLTB low, Clear to 0 to have LED short circuit faults not pull FLTB low. strocen: String Open Circuit Fault Enable; Set to 1 to have string open circuit faults pull FLTB low, Clear to 0 to have string open circuit faults not pull FLTB low. When this bit is zero a string open circuit fault occurs, the Efficiency Optimizer attempts to bring the string back in to current regulation by increasing the boost regulator output voltage up to its highest value, where it remains without indicating a fault condition. In this state fictitious LED short circuit faults may occur. fboocflten: Feedback Out Open Circuit Fault Enable; Set to 1 to have feedback open circuit faults pull FLTB low, Clear to 0 to have feedback open circuit faults not pull FLTB low. feedback connection is labelled FBO on the MSL3087, FB on all others. 11

12 4.13 String Fault Enable Register 0x03 ADDRESS AND REGISTER NAME DEFAULT D7 D6 D5 D4 D3 D2 D1 D0 0x03 strfltenrg 0xFF strflten7 strflten6 strflten5 strflten4 strflten3 strflten2 strflten1 strflten0 strfltenn: Individual string fault enable bits. Set to 1 to enable string fault detection, Clear to 0 to disable string fault detection Short Circuit Threshold Control Register 0x04 ADDRESS AND REGISTER NAME DEFAULT D7 D6 D5 D4 D3 D2 D1 D0 0x04 scthctrlrg 0b x x scqualdly scdbncdly - x scthrshlvl[1:0] scqualdly: LED Short Circuit Qualification Delay; Clear to 0 for a 256ms short circuit qualification delay, Set to 1 for a 512ms short circuit qualification delay. An LED short circuit must last for the full qualification delay time to be flagged as a fault. scdbncdly: LED Short Circuit De-bounce Delay; Clear to 0 for a 2µs short circuit de-bounce delay, Set to 1 for a 4µs short circuit debounce delay. scthrshlvl[1:0]: Short Circuit Threshold Setting; 0b00 = 4.9V, 0b01 = 5.8V, 0b10 = 6.8V, 0b11 = 7.6V. scthrshlvl auto-programs when EN is taken high. value scthrshlvl takes is based on the value of the resistor connected from SCTH to GND, R SCTH (Table 2). MSL3088 has no SCTH input; these bits default to 0b10 = 6.8V. Table 4.1: Short Circuit Threshold Resistor (R SCTH) R SCTH scthrshlvl[1:0] Threshold Voltage 1.0kΩ (or GND) 0b00 4.9V 27kΩ 0b01 5.8V 68kΩ 0b10 6.8V 330kΩ (or OPEN) 0b11 7.6V 4.15 Fault Status Register 0x05 ADDRESS AND REGISTER NAME 0x05 fltstsrg DEFAULT D7 D6 D5 D4 D3 D2 D1 D0 Read Only Clear on read fltbdrv x x x bstov FltDet strscdet strocdet fbooc FltDet fltbdrv: FLTB Driver; equals 1 when any fault is detected (any bit D0 through D3 is 1). When fltbdrv = 1, the hardware FLTB output is low. bstovfltdet: Boost Over-Voltage Fault Detected; equals 1 when boost over-voltage fault is detected (non-latching). strscdet: String Short Circuit Fault Detected; sets to 1 when any string short circuit fault is detected. strocdet: String Open Circuit Fault Detected; sets to 1 when any string open circuit fault is detected. fboocfltdet: FB Open Circuit Fault Detected; sets to 1 when FB open circuit fault is detected. Clear faults by reading fault register 0x05 writing 0xFF to registers 0x06 0x07, or by toggling EN low then high. 12

13 4.16 String Open Circuit Status Register 0x06 0x06 strocstsrg Read-only Clear on write stroc7 stroc6 stroc5 stroc4 stroc3 stroc2 stroc1 stroc0 strocn: Each bit sets to 1 to indicate that the driver detected an open circuit fault on the corresponding string; read to determine which strings are faulted. Clear faults by reading fault register 0x05 writing a 1 to the bit showing a fault, or by toggling EN low then high String Short Circuit Status Register 0x07 0x07 strscstsrg Read-only Clear on write strsc7 strsc6 strsc5 strsc4 strsc3 strsc2 strsc1 strsc0 strscn: Each bit sets to 1 to indicate that the driver detected a short circuit fault on the corresponding string; read to determine which strings are faulted. Clear faults by reading fault register 0x05 writing a 1 to the bit showing a fault, or by toggling EN low then high String Enable Status Register 0x08 0x08 strensts Read-only strensts7 strensts6 strensts5 strensts4 strensts3 strensts2 strensts1 strensts0 strenstsn: Each bit sets to 1 to indicate that the corresponding string is turned off due to the enable register 0x00 or due to faults Boost/Boot-Load Status Register 0x09 0x09 bststsrg Read-only - blrecovd one bldone x x bstovflt bstpwr Good bstsftstrt Done blrecovdone: Boot-Load Recovery Complete. Sets to 1 when all trim control registers are ready; signals the boost regulator to begin soft start. bldone: Boot-load complete; sets to 1 after the initial register values are loaded. bstovflt: Boost Over Voltage Fault; sets to 1 when boost controller over-voltage fault is detected (not latching). bstpwrgood: Boost Power Good; sets to 1 when boost output power is in regulation. bstsftstrtdone: Boost Soft Start Done. Sets to 1 when the boost soft-start is complete; drivers are disabled until bstsftstrdone transitions high Efficiency Optimizer DAC Readback Register 0x0C 0x0C eodacrg Read Only eodacrg(7:0 eodacrg[7:0]: Reports the EO DAC setting, which determines EO (FBO on MSL3087, FB on all other drivers) output current at 1.1µA per LSB, which in turn controls the boost regulator output voltage Efficiency Optimizer Status Register 0x0D 0x0D eostsrg Read-only fboocflt - eodacact eocal eoinitcal fboocflt: Feedback Out Open Circuit Fault; equals 1 when the driver detects an open circuit at feedback (FBO on MSL3087, FB on all other drivers). eodacact: Efficiency optimizer DAC active; equals 1 when feedback (FBO on MSL3087, FB on all other drivers) is sourcing current to the boost regulator feedback node to control the boost regulator output voltage. eocal: Efficiency Optimizer Calibration; equals 1 when the EO is calibrating. EO automatically re-calibrates V OUT every 1 second. An EO Calibration will also occur immediately when it detects a loss of string current regulation. eoinitcal: Efficiency Optimizer Initial Calibration; equals 1 when the EO is performing an initial calibration. Initial Calibration takes a maximum of 0.52 seconds. 13

14 4.22 PWM Control Register 0x10 0x10 pwmctrlrg x dcmsrmode phashft phashftpairs intduty intfreq pwmdrct syncpol MSL3040 0x MSL3041 0x MSL50/60/86/87 0x MSL3080 0x MSL3088 0x dcmsrmode: Duty Cycle Measure Mode; determines response to a PWM input of less than 20Hz. When dcmsrmode = 1 the PWM input is 20Hz or greater, the PWM dimming outputs take the duty cycle of the PWM input signal. When dcmsrmode = 1 the PWM input is less than 20Hz the PWM dimming output duty cycle is fixed at 0% when the input is low, is fixed at 100% when the input is high. When dcmsrmode = 0 the PWM input is 20Hz or greater, the PWM dimming signals take the duty cycle of the PWM input signal. When dcmsrmode = 0 the PWM input is less than 20Hz, the PWM dimming output duty cycle is fixed at the last valid measured duty cycle before the input fell to less than 20Hz. This allows a PWM input to set the output duty cycle (with a signal above 20Hz) then cease while the outputs continue PWM dimming of the LED strings. When pwmdrct = 1 phashft = 1, this bit needs to be set to 1. phashft: Phase Shift; Set to 1 to phase shift the string PWM dimming, Clear to 0 for synchronous PWM dimming. Phase shift control is valid regardless of the settings of bits D1, D2 D3 of this register. phashftpairs: Phase Shift in Pairs; Set to 1 to phase shift the string PWM dimming so that adjacent strings operate as pairs, synchronizing STR0 to STR1, STR2 to STR3, STR4 to STR5 STR6 to STR7. Clear to 0 for independent string PWM dimming phase. intduty: Internal Duty Cycle; Set to 1 to use registers 0x13 0x14 to set the PWM dimming duty cycle, Clear to 0 to use the signal at the PWM input to set the duty cycle. pwmdrct (Bit D1) = 1 overrides this bit. See Table 3 below. intfreq: Internal Frequency; Set to 1 to use registers 0x11 0x12 to set the PWM dimming frequency, Clear to 0 to use the signal at the PWM input (SYNC input for MSL3041 MSL3088) to set the PWM dimming frequency. pwmdrct (Bit D1) = 1 overrides this bit. See Table 3 below. pwmdrct: PWM Direct; Set to 1 to use the signal at the PWM input to control both the PWM dimming frequency duty cycle, Clear to 0 to use settings indicated by intduty (bit D2) intfreq (bit D3) to determine PWM dimming frequency duty cycle. See Table 3 below. syncpol: Sync Polarity; Set to 1 to synchronize string PWM dimming to the rising edge of the signal at the SYNC input, Clear to 0 to synchronize to the falling edge. This bit is valid only for the MSL3041 MSL3088, ignored by the other drivers. Table 4.2: Internal/External Frequency Duty Cycle Selection REGISTER BITS MSL3041/50/60/80/86/87 STRING DRIVERS GET MSL3040/88 STRING DRIVERS GET pwmdrct intduty intfreq DUTY CYCLE FREQUENCY DUTY CYCLE FREQUENCY INFORMATION FROM INFORMATION FROM PWM INPUT PWM INPUT PWM INPUT SYNC INPUT PWM INPUT 0x11, 0x12 PWM INPUT 0x11, 0x12* x13, 0x14 PWM INPUT 0x13, 0x14* SYNC INPUT x13, 0x14* 0x11, 0x12* 0x13, 0x14* 0x11, 0x12* 1 x x PWM INPUT PWM INPUT PWM INPUT PWM INPUT *Assure that unused PWM SYNC inputs are held to logic low. x = don t care NOTE: Regardless of the dimming technique used a minimum on-time of 3µs is required. 14

15 4.23 PWM Frequency/Phase Registers 0x11 0x12 0x11 0x00 freqpha[7:0] freqpharg 0x12 0x00 freqpha[15:8] freqpha[15:0]: PWM Frequency or Phase Setting Registers. When internal frequency is selected via register 0x10, the PWM dimming frequency equals 20MHz divided by the decimal value of this 16-bit register pair. When using an external signal to set the PWM dimming frequency (SYNC), this register pair determines the delay time between the edge of the input signal transition the beginning of the first enabled string PWM dimming on-time, where the delay time is 50ns times the decimal value of the lower 12-bits; when phase shifting is enabled, subsequent strings are phase delayed using the first string as the zero-time reference PWM Duty Cycle Registers 0x13 0x14 0x13 0x00 dutycyc[7:0] dutycycrg 0x14 0x00 freqmul[1:0] x x dutycyc[11:8] dutycyc: 12-bit PWM Duty Cycle Registers. When internal duty cycle is selected, using register 0x10, PWM dimming duty cycle is a linear relation where 0x000 = 0% 0xFFF = 100%. A minimum on-time of 3 µs is required. freqmul: SYNC Frequency Multiplier; acts on both internally externally generated PWM frequency. PWM control signal frequency (either applied to PWM or SYNC inputs, or internally generated) is multiplied by the decimal value of these two bits, taken as LSB = 2^0 MSB = 2^1, plus 1 to generate the string PWM dimming frequency. This allows synchronized PWM dimming at multiples of the LCD panel refresh rate. For instance, when freqmul = 0b00 the multiplication factor = 0*(2^1) + 0*(2^0) + 1 = Reserved registers 0x20-0x23 se four registers are reserved should maintain a value of 0x00 for all four bytes Sleep Registers 0x7F 0x7F sleeprg 0x00 Sleep slppwrsv x x - - x x sleep slppwrsv: Sleep Sleep Power Save; use these bits together to enter/exit low power sleep mode. When sleep = slppwrsv = 1 the driver is asleep input current is reduced to less than 1.8mA, when sleep = slppwrsv = 0 the driver operates fully. When asleep, all the registers maintain their states the I 2 C remains active. Table 4 presents low power controls behaviours. Table 4. Low Power Controls Behaviors EXTERNAL INPUT CONTROL BITS BEHAVIOR RECOVERY BOOST EN* sleep slppwrsv LEDS REGULATOR I VIN MAX INITITAL GATE DRIVER RECOVERY CALIBRATION TIME CYCLE SOFT 0 x x OFF OFF <10µA 520ms YES YES 1 0 x ON ON <20mA NA NA NA OFF ON** <10mA 520ms YES NA OFF OFF <1.8mA 520ms YES YES NA = Not Applicable x = Don t care * Taking EN from 0 to 1 returns all register bits to their factory default values. ** V LED goes to V OUT(MAX); this state is available but not recommended. 15

16 4.27 Efficiency Optimizer Control Registers 0x84 0x85* 0x84 eoctrl0rg 0x00 hdrmstep[1:0] acaldly[1:0] stepdly[1:0] isinkconfdly[1:0] 0x85 eoctrl1rg 0x02 decrstep[1:0] incrstep[1:0] icapwm acal100 acalen ichkdis *se registers are available only on the MSL3087 determine how the FBO output controls the external boost regulator. An initial power supply voltage calibration occurs when the EO is started; the EO is started at power-up, when exiting from sleep or when EN is taken high. hdrmstep: Headroom Step. Bits D6 D7 of 0x84 set the number of steps the EO takes when raising the boost regulator output voltage after detecting a current sink error during any calibration cycle; 0b00 = 6 steps, 0b01 = 3 steps, 0b10 = 9 steps 0b11 = 12 steps. Fewer steps improves efficiency, while more steps offers better immunity from power supply transients noise. incrstep, bits D4 D5 of 0x85, controls the FBO current change of each step. acaldly: Auto-Calibration Delay. Bits D4 D5 of 0x84 set the time delay between consecutive EO auto-recalibration cycles; 0b00 = 1s, 0b01 = 0.5s, 0b10 = 2s 0b11 = 4s. stepdly: Step Delay. Bits D2 D3 of 0x84 set the delay time between consecutive boost regulator output voltage corrections; 0b00 = 2ms, 0b01 = 1ms, 0b10 = 4ms 0b11 = 8ms. Set the correction delay to longer than the power supply settling time. isinkconfdly: Current Sink Confirmation Delay. Bits D0 D1 of 0x84 set the current sink error confirmation delay time; 0b00 = 0.5µs, 0b01 = 0.25µs, 0b10 = 1µs, 0b11 = 2µs. current sink error confirmation delay is the time that the current sink error must persist before the EO recognizes it as a current sink error condition. This prevents erroneous current sink error detection due to noise other transients. driver uses a current sync error to determine that LED string voltage is too low needs to be increased to maintain current regulation. decrstep: Decrement Step. Bits D6 D7 control the size of the EO voltage control current changes that happen during Efficiency Optimizer initial calibration; 0b00 = 3 LSBs, 0b01 = 1 LSB, 0b10 = 2 LSBs 0b11 = 4 LSB. Each current change equals the decrstep[1:0] value multiplied by the 1.1µA FBO DAC LSB current value. For example, if decrstep[1:0] = 0b10 then the step setting is 2 LSBs, each current step is 2 * 1.1µA = 2.2µA. change in V LED for each step is equal to the change in EO voltage control current times the value of the top resistor in the boost regulator output voltage divider, R TOP (see datasheet for details). incrstep: Increment Step. Bits D4 D5 of 0x85 control the size of the EO voltage control current correction steps that it takes after a current sink error is detected. Each correction step current size equals the decimal equivalent of incrstep[1:0] plus 1 multiplied by the 1.1µA FBO DAC LSB current value. For example, if incrstep[1:0] = 0b10 then the step setting is 3, each current step is 3 * 1.1µA = 3.3µA. number of correction steps taken is controlled by hdrmstep, bits D6 D7 of 0x84. change in V LED for each step is equal to the change in EO voltage control current times the value of the top resistor in the boost regulator output voltage divider, R TOP (see datasheet for details). icalpwm: Initialize Calibration with PWM. Set to 1 to use PWM dimming during EO initial calibration. Clear to 0 to use 100% duty cycle during EO initial calibration; when initial calibration is complete the driver begins PWM dimming. acal100: Auto Re-Calibration at 100% Duty Cycle. Bit D2 of 0x85; Set to 1 to use 100% duty cycle during auto recalibration. Clear to 0 to use the user controlled PWM dimming during auto recalibration. acalen: Automatic Re-Calibration Enable. Bit D1 of 0x85; Set to 1 to enable automatic EO boost regulator output voltage recalibration, Clear to 0 to not auto-recalibrate after initial calibration is complete. EO automatic recalibration periodically minimizes the boost regulator output voltage after initial calibration to maintain optimal efficiency as the LED string voltage changes with time or temperature. acaldly bits D4 D5 of 0x84 set the delay time between consecutive EO recalibration cycles. Regardless of the acalen setting, the EO always maintains sufficient LED string current sink headroom by raising the boost regulator output voltage should a current regulation error occur. ichkdis: Current Check Disable. Bit D0 of 0x85; Set to 1 to disable current sink error detection for the EO, Clear to 0 to enable current sink error detection. EO uses a current sync error to determine that LED string voltage is too low needs to be increased to maintain current regulation. Use ichkdis as a debugging or testing tool, not for final production code. Clear eoen (bit D6 in register 0x01) to 0 before setting ichkdis to 1. When ichkdis = 1 eoen = 1 the EO output forces the string power supply to its minimum output voltage, possibly causing fictitious string short circuit faults. Setting ichkdis = 1 disables open circuit fault detection of all LED strings. 16

17 MSL3040/41/50/60/80/86/87/88 Programmers Guide Figure Efficiency Optimizer Initial Calibration Cycle Figure 12. Efficiency Optimizer Initial Calibration Cycle Atmel Corporation 2325 Orchard Parkway San Jose, CA USA Tel: (+1)(408) Fax: (+1)(408) Atmel Asia Limited Unit 01-5 & 16, 19F BEA Tower, Millennium City Kwun Tong Road Kwun Tong, Kowloon HONG KONG Tel: (+852) Fax: (+852) Atmel Munich GmbH Business Campus Parkring 4 D Garching b. Munich GERMANY Tel: (+49) Fax: (+49) Atmel Japan 9F, Tonetsu Shinkawa Bldg Shinkawa Chuo-ku, Tokyo JAPAN Tel: (+81)(3) Fax: (+81)(3) Atmel Corporation. All rights reserved. / Rev.: MSL3040/41/50/60/80/86/87/88 Page Programmers 15 of 15 Guide DBIE Atmel, logo combinations thereof, others are registered trademarks or trademarks of Atmel Corporation or its subsidiaries. Other terms product names may be trademarks of others. Disclaimer: information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN THE ATMEL TERMS AND CONDITIONS OF SALES LOCATED ON THE ATMEL WEBSITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DIAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, CONSEQUENTIAL, PUNITIVE, SPECIAL OR INCIDENTAL DAMAGES (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS AND PROFITS, BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF THE USE OR INABILITY TO USE THIS DOCUMENT, EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Atmel makes no representations or warranties with respect to the accuracy or completeness of the contents of this document reserves the right to make changes to specifications products descriptions at any time without notice. Atmel does not make any commitment to update the information contained herein. Unless specifically provided otherwise, Atmel products are not suitable for, shall not be used in, automotive applications. Atmel products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life. 17