Prospects for Solid State Data Storage: Beyond Flash Memory and the Hard Disk Drive
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1 Prospects for Solid State Data Storage: Beyond Flash Memory and the Hard Disk Drive Gian-Luca Bona IBM Research, Almaden Research Center
2 Cost IBM Research Incumbent Semiconductor Memories SRAM NOR FLASH DRAM NAND FLASH Attributes for universal memories: Highest performance Lowest active and standby power Unlimited Read/Write endurance Non-Volatility Compatible to existing technologies Continuously scalable Lowest cost per bit Performance
3 Cost IBM Research Incumbent Semiconductor Memories SRAM NOR FLASH DRAM NAND FLASH SLm SLm-1 m+1 WL n-1 WL n WL n+1 A new class of universal storage device : a fast solid-state, nonvolatile RAM enables compact, robust storage systems with solid state reliability and significantly improved costperformance Performance
4 Non-volatile, universal semiconductor memory SL m SL m+1 SL m-1 WL n-1 WL n WL n+1 Everyone is looking for a dense (cheap) crosspoint memory. It is relatively easy to identify materials that show bistable hysteretic behavior (easily distinguishable, stable on/off states). IBM
5 The Memory Landscape IBM Research 2007 IBM Corporation
6 Emerging Memory Technologies Memory technology remains an active focus area for the industry FLASH Extension FRAM MRAM PCRAM RRAM PCM - SS Electrolyte Polymer/ Organic Mechanical 3D Thyrister Trap Storage Saifun NROM Tower Spansion Infineon Macronix Samsung Toshiba Spansion Macronix NEC Nano-x tal Freescale Matsushita Ramtron Fujitsu STMicro TI Toshiba Infineon Samsung NEC Hitachi Rohm HP Cypress Matsushita Oki Hynix Celis Fujitsu Seiko Epson IBM Infineon Freescale Philips STMicro HP NVE Honeywell Toshiba NEC Sony Fujitsu Renesas Samsung Hynix TSMC Ovonyx BAE Intel STMicro Samsung Elpida IBM Macronix Infineon Hitachi Philips IBM working towards a 16GB part by 2010 IBM Sharp Unity Spansion Samsung Axon Infineon Spansion Samsung TFE MEC Zettacore Roltronics Nanolayer Nantero STMicro Hitachi STMicroelectronics is claiming significant progress in the development of a new type of electronic memory that could eventually replace Flash memory technology Matrix (Sandisk) 3D-ROM Samsung Macronix Infineon T-RAM Sony 4Mb C-RAM (Product) 0.25um 3.3V DURABILITY Nonvolatile HDD Flash SCM PERFORMANCE Low High N/A DRAM 2Mb FRAM (Product) 0.35um 3.3V 4Mb MRAM (Product) 0.18um 3.3V 512Mb PRAM (Prototype) 0.1um 1.8V 2007 IBM Corporation Volatile
7 Critical applications are undergoing a paradigm shift Compute-centric paradigm Data-centric paradigm Solve differential equations Main Focus Analyze petabytes of data CPU / Memory Bottleneck Storage & I/O Computational Fluid Dynamics Finite Element Analysis Multi-body Simulations`` Typical Examples Search and Mining Analyses of social/terrorist networks Sensor network processing Digital media creation/transmission Environmental & economic modeling Thesis: Disks or Flash can t keep up w/data centric applications Proposal: Develop device technology and build a high density array and demonstrate performance and endurance for the data-centric paradigm
8 What are the limitations with disks? Bandwidth Access Time Reliability - Power Disk Performance improves very slowly Gap between processor and disk performance widens rapidly Bandwidth gap can be solved with many parallel disks but need 10,000 disks today, 500,000 disks by 2020 but that s just for a traditional high-end HPC system data intensive problems are much worse Access time gap has no good solution disk access times decrease only 5% per year complex caching or task switching schemes help - sometimes Newest disk generations are less reliable than older ones Data losses occur in even the best enterprise-class storage systems Disk power dissipation is a major factor in data-centric systems
9 HDD Issue: Mean Time to Data Loss Time to data loss in days GB Drive 800GB Drive 3.2TB Drive Number of disk drives in system Assumptions: MTBF 1 Million Hours and RAID5
10 What are the limitations with Flash? Read/Write Access Times Write endurance Block architecture Flash Performance showing no improvement Gap between processor and Flash performance continues to widen Write endurance <10 6 and showing no improvement trends Need >10 9 to cater to frequent writes as data continually flows into the system Tomorrow s hand-held devices will be continuously updated Intel applications characterized by continuous data streams Access time gap has no good solution `
11 Storage Historic Price Trend and Forecast 34nm 4-Layer 1-bit 27nm 4-Layer 2-bit 22nm 4-Layer 2-bit 18nm 4-Layer 3-bit 14nm 4-Layer 3-bit 14nm 4-Layer 4-bit
12 Storage Class Memory Target Specifications Access Time Data Rate (MB/s) Endurance HER (/TB) MTBF (MH) On Power (mw) Standby (mw) Cost ($/GB) CGR ~ ns <5.5 35% Very challenging to achieve in combination
13 SCM Basic Concepts (Phase Change Example) Using a phase transition of a Ge-Sb-Te alloy to store a bit Ge-Sb-Te exists in a stable amorphous and a stable crystalline phase Phases have very different electrical resistances Transition between phases by controlled heating/cooling Write 1 : short (10ns) intense current pulse melts alloy crystal => amorphous Write 0 : longer (50ns) weaker current pulse re-crystalizes alloy => crystalline Read : short weak pulse senses resistance, but doesn t change phase Non-Si based proprietary diode materials being developed for high-on current density (> 10 7 A/cm 2 needed for PCM) and ultra-low OFF current density (< 1 A/cm 2 ). Temperature T melt T cryst PCM Alloy & Diode Current Pulse F X- Address Line Time (ns) Y- Address Line
14 Phase-Change Nano-Bridge Prototype memory device with ultra-thin (3nm) films demonstrated Dec 06 3nm * 20nm 60nm 2 Flash roadmap for 2013 phase-change scales Fast (<100ns SET) Low current (< 100μA RESET) Current scales with area W defined by lithography H by thin-film deposition
15 Processing Cost and F² The bit cell size drives the cost of any memory Cell area is expressed in units of F² where F is the minimum lithographic feature of the densest process layer Half pitch dimension of metallization connecting drain and source for ICs MR sensor width in magnetic recording Cell areas DRAM 8F² 6F² NAND 4F² 2F² SRAM 100F² MRAM 20F² -- 40F² Hard Disk 0.5F² 1F². F F R. Fontana, S. Hetzler Magnetic Memories -- Memory Hierarchy and Processing Perspectives MMM 2005 FB-04
16 Low Cost Requires High Density 3D Lithographic Crosspoint Memory 2D Sub-Lithographic Crosspoint Memory F F s Blocks of Nanoscale Crossbar Arrays (NCA) 4F 2 / (# of Layers) 4F 2 / (# of Nodes) 2 Need Effective Cell Size < 4F 2 (F Lithography Half-Pitch) 2D Better Scaling & Fewer Process Steps, but Requires Interface Between Litho (F) & Sub-Litho (Fs) Viable Method to Manufacture Sub-Lithographic Arrays IBM Research 2007 IBM Corporation
17 Crossbar Memory Fundamentals standard crossbar memory F F Cell size = 4F 2 1-D What if we can put more cells at a crossbar? 2-D Net effect: Density n 2 Cost n 2 4F 2 Memory Cells between CMOS lines /n 4F 2 /n 2 IBM Research 2007 IBM Corporation
18 Micro-Nanoscale Decoder Fop. Fs Absolute Current in Fins 1.0E E E E E-09 > 100X (a) Gate 1 Voltage = -1.2V FIN 1 FIN 2 FIN 3 FIN 4-1.2V -10V WL1 WL2 S IEDM-paper E Gate 2 Voltage (V) WL1 WL2 F 2 Cell Sub lithographic feature is selected by moving depletion across the fine structure S Modulating signal is brought in by lithographically defined lines Fins down to sub 20 nm have been addressed WL1 WL2 IBM Research K. Goplakrishnan et al. IEDM 2005 S 2007 IBM Corporation
19 IBM Almaden Research Center MNAB Concept Demonstrated 100nm Pitch MNAB Devices Fabricated by E-Beam Lithography Obtained Fully Functional Devices Selectivity > 10 5 Gate1 = -2.0V Gate1 = -2.0V IBM Confidential 2007 IBM Corporation
20 Combining Micro-Nano Decoder and ROM Oxide (3-4 nm) 4-fin UMB+ROM test structure FIB x-sem through gated fins (A-A ) Successful integration of UMB with memory element ( 2 terminal oxide antifuse ROM) Verified operation over all bit sequences for 4-fin UMB+ROM IBM Research 2007 IBM Corporation
21 Self Assembly Nanoscale Patterning Techniques Spacers Nanoimprint Lithography (IBM T J Watson Research Center) Frequency doubling 40 nm to 20 nm pitch (IBM) (IBM Almaden) Various nanoscale patterning techniques exist. Sub 20 nm pitch demonstrated. Only regular line / space patterns possible.
22 Paths to ultra-high density memory At the 32nm node in 2013, MLC NAND Flash is projected* to be at if we could density product shrink 4F 2 by 43 Gb/cm 2 32GB from 4F 2 to 2F 2F n 97 Gb/cm 2 64GB n Gb/cm 2 256GB Ln Gb/cm2 ~1 TB (for m=n=4) 4F 2 / n demonstrated (at IEDM 2005) 4F 2 /n 2 * 2006 ITRS Roadmap 4F 2 / Ln 2
23 Value Proposition for SCM in Storage Controllers Significantly improved cost/performance long before SCM competes with DASD on cost Response Time from Simple Cache Model Simple cache model (cube root rule), queuing effects ignored, miss rate starts at 50% Columns in figure 1st business as usual (BAU), DRAM of DASD capacity 2 nd same cost as BAU, but DRAM replaced by SCM, 2% of DASD capacity, perf. ~2x 3 rd Hierarchical storage cost now 2.8x 1 st column, SCM capacity now 20% of DASD, perf. >3.6x Response Time in us us 1385us d SCM (1us) Disk (5ms) and SCM (1us) Disk (5ms) and DRAM (.05us) Controller stack (100us) fabric latency and transfer (25us) Host stack (100us) 763us 227us 4 th cost now 1-10x, SCM only storage used in system. Perf. >12x Performance assessed at application interface to OS. So, I/O stack in host, fabric latency and storage controller microcode processing time and data transfer time are included % 2% 20% 100% % of total storage in cache..2% DRAM (100ns), the rest 1us
24 SCM impact on large HPC storage systems Large file throughput >>10x improvement per TB of file system possible Limited by interconnect and controller bandwidth Limited by file system OS software overheads Good match for check-pointing Bulk storage costs high Small file and metadata access rates Access rate improvement >100 feasible Limited by software stack and controller overhead
25 Magnetic Racetrack Memory Data stored as pattern of domains in long nanowire or racetrack of magnetic material. Data stored magnetically and is nonvolatile. Current pulses move domains along racetrack no moving parts, just the patterns move. Each memory location stores an entire bit pattern (10, 100, 1000 bits?) rather than just a single bit.
26 Magnetic Race-Track Memory Information stored as domain walls in vertical race track Data stored in the third dimension in tall columns of magnetic material Domains moved around track using nanosecond pulses of current 10 to 100 times the storage capacity of conventional solid state memory IBM trench DRAM Magnetic Race Track Memory S. Parkin (IBM), US patents 6,834,005 (2004) & 6,898,132 (2005)
27 Large Magnetic Anisotropy for Single Atoms The energy that is required to change the direction of a single spin was measured. Mn Fe Large single-atom magnetic anisotropy for iron of about 6 mev. About 50x weaker anisotropy for manganese on same surface. Conductivity Voltage [mv] Spin excitation spectroscopy reveals spin energy levels, including their magnetic field dependence. DFT calculations elucidate surface structure and leads to same total spin as experiment. GOAL: engineer very large magnetic anisotropy to demonstrate data storage. A. Heinrich, C. Hirjibehedin, C. Lutz, B. Jones, C.-Y. Lin, B. Melior
28 Storage Class Memory: solid-state non-volatile memory at hard-drive prices Phase-change memory low cost because >1 bit / 4F 2 The Future of Memory? ~2013? Racetrack memory ~2018? a 3-D nano-warehouse for data Atomic memory there s a lot of room at the bottom ~2030? Science & Technology Almaden
29 Innovation and Impact Storage class memory (SCM) New nonvolatile solid state memory with fast access and high throughput Robustness, volumetric density and power significantly better than disks Will revolutionize memory/storage hierarchy >10x throughput, >100x transaction rate potential Applications will be revamped to exploit new technology New applications or significantly extended applications, e.g. Sensor/actuator systems with storage at the network edge Mobile applications, e.g. semiautonomous video gatherers
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