AT91SAM ARM-based Embedded MPU. Application Note. LCD Implementation on SAM9G15/G35/X35 Devices. 1. Scope

Transcription

1 LCD Implementation on SAM9G15/G35/X35 Devices 1. Scope This application note describes how to use and optimize the full featured LCD embedded in Atmel ARM -based SAM9G15, SAM9G35 and SAM9X35 devices. Please note that an example is provided on Atmel web site, in the Software Package of each device. 2. LCD Features Supports 12-, 16-, 18- and 24-bit Output Mode through the Spatial Dithering Unit Supports Asynchronous Output Mode 1, 2, 4, 8 bits per pixel (palletized) 12, 16, 18, 19, 24, 25 and 32 bits per pixel (non palletized) Supports one Base (background) Supports OVR1 Window Supports one High End Overlay (HEO) Window Supports one Hardware Cursor, Free Ranging up to a size limit of 128x128 pixels Little Endian Memory Organization Programmable Timing Engine, with Integer Clock Divider Programmable Polarity for Data, Line Synchro and Frame Synchro Hardware Cursor Fixed Size on the following patterns: 32x32, 64x64 and 128x128 Display Size up to 800 x 600 Color Lookup Table with up to 256 entries and Predefined 8-bit Alpha Programmable Negative and Positive Row Striding for all layers Programmable Negative and Positive Pixel Striding for all Overlay1 and HEO layers High End Overlay supports 4:2:0 Planar Mode and Semiplanar Mode High End Overlay supports 4:2:2 Planar Mode and Packed Memory Mode High End Overlay includes Chroma Upsampling unit and Programmable Scaler Integrates Fully Programmable Color Space Conversion Overlay1 and High End Overlay integrate Rotation Engine: 90, 180, 270 Blender Function Supports Arbitrary 8-bit Alpha value and Chroma Keying AT91SAM ARM-based Embedded MPU

2 3. LCD Controller Block Diagram 32-bit APB Interface Configuration Registers SYSCTRL Unit AHB Bus HCC OVR1 CLUT ROT CLUT LCD_DAT[23:0] LCD_VSYNC 32-bit AHB Master Interface DEAG Unit HEO ROT CSC GAB Unit LTE Unit LCD_HSYNC LCD_PCLK 2DSC CUE LCD_DEN CLUT LCD_PWM Base CLUT LCD_DISP HEO: High End Overlay CUE: Chroma Upsampling Engine CSC: Color Space Conversion 2DSC: Two Dimension Scaler DEAG: DMA Engine Address Generation HCC: Hardware Cursor Channel GAB: Global Alpha Blender LTE: LCD Timing Engine ROT: Hardware Rotation 4. System Considerations 4.1 Clock Scheme The lcdc controller clock can be a division of the system clock or sys clock. 4.2 DMA The LCD controller embeds a DMA for memory movements. It competes with other masters for external memory access. The priority of the LCD controller DMA and other master peripherals can be programmed through the matrix priority registers. 2

3 5. Overview of System Limitations SAM9G15, SAM9G35 and SAM9X35 embed a multi-layer LCD Controller. Four layers are available: a Base layer, which corresponds to the background of the screen an HEO layer, which is a High End YUV-standard layer, used for multimedia data such as video or photo an OVR1 layer, which is an RBG layer an HW Cursor layer, which is used for the hardware cursor Figure 5-1. Usage Example With an 800x480 LCD Display The DMA of each layer accesses the memory thanks to the DMA Engine Address Generator (DEAG). The larger the layer, the deeper the color, the more bandwidth used. 3

4 Figure 5-2. Concurrent Accesses to DDR2 Device Other Masters HCC OVR1 HEO DEAG Unit LCDC Master Interface MATRIX DDRC DDR2 Device Base HEO: High End Overlay OVR1: Overlay1 HCC: Hardware Cursor Channel DEAG: DMA Engine Address Generation Other Masters Golden Rule: the LCD bandwidth should not exceed 60% of the effective DDR2 bandwidth to let the overall system handle other activities. 4

5 6. Quick Analysis 6.1 Definitions The following parameters have to be defined: The Pixel Clock (PC) depends on the Image Resolution (IR) of the largest layer, on the Blanking (BL) and on the Refresh Rate (RR). The Color Depth (CD) is the number of bytes used to define the pixel color. The Bandwidth (BW), for a given IR, is given in Megabytes per second (MB/s) by the formula: PC x CD. When the layer size is smaller than the IR, the amount of data to transfer is smaller, i.e. the DMA Controller performs less accesses. The following tables, which show the bandwidth with different sets of configuration, always have: A base layer IR = 800x480 A PC = MHz 6.2 Maximum Bandwidth The effective DDR2 bandwidth is roughly 300 MB/s. With the DDR2 system, the total amount of data transferred by the LCD should not exceed 180 MB/s. The maximum bandwidth corresponds to the largest CD and the largest size of each layer. Note: The HW Cursor layer is supposed to have no influence. Table 6-1. Configuration for each 800*480 (Base, HEO or OVR1) CD in bits CD in Bytes Maximum BW (MB/s) % DDR2 BW From the first analyses, it makes no sense to use Base+HEO+OVR1 layers at full size (800*480) because, in the end, the user can only see one layer. Thus, it makes no sense for a system as well because the DDR2 usage rises to 3*44% = 132%. For best performances of the overall system, the user should carefully configure each LCD layer. This is the aim of the next section. 5

6 7. LCD Sub-system Configuration This section proposes different sets of configuration, in order to limit the LCD bandwidth consumption. 7.1 Reduce the Size The layer size has the bigger influence on the bandwidth because the user defines a surface. Table 7-1. Configuration for each (Base, HEO or OVR1) with CD=4 (32 bpp) size Maximum BW (MB/s) % DDR2 BW 800* *240 (1) * Note: 1. As shown in the example on Figure 5-1 Table 7-2. Configuration for each (Base, HEO or OVR1) with CD=3 (24 bpp) size Maximum BW (MB/s) % DDR2 BW 800* *240 (1) * Note: 1. As shown in the example on Figure 5-1 Table 7-3. Configuration for each (Base, HEO or OVR1) with CD=2 (16 bpp) size Maximum BW (MB/s) % DDR2 BW 800* *240 (1) * Note: 1. As shown in the example on Figure 5-1 6

7 7.2 Reduce the Color Depth Base The Color Lookup Table (CLUT) mode can be used for the Base layer. Table 7-4. Configuration for the Base in 800*480 Base layer color Maximum BW (MB/s) % DDR2 BW 8-bit CLUT bpp (CD=3) Figure 7-1 shows both possible configurations. Figure bit CLUT (on the left) - 24 bpp (on the right) Other s The CD can be reduced for other layers as well. Table 7-5. Configuration for each (HEO or OVR1) CD Maximum BW (MB/s) % DDR2 BW

8 7.3 Change the Color Space to YUV HEO is dedicated to YUV data. Use Chroma Upsampling Engine (CUE). This block is to be selected when the input image sampling format is YUV (Y CbCr) 4:2:0, which converts to a higher quality 4:4:4 image. 7.4 Horizontal and Vertical Front and Back Porch The LCD FIFO is filling up during horizontal and vertical back porch. Increasing these delays will let more time to the LCD to get data from the memory. Figure 7-2. Horizontal and Vertical Front and Back Porch The user should set these fields carefully, according to the LCD panel documentation. 8

9 8. Configuration Example Retained Figure 8-1. Usage Example with an 800x480 LCD Display Type Size CD Maximum BW (MB/s) % DDR2 BW Base 800* HEO 400* OVR1 600* As a conclusion, this configuration totalizes 25.6% of the DDR2 bandwidth, which is a good trade-off between visual result and overall system capability. 9

10 Revision History Doc. Rev 11114A Comments First issue Change Request Ref. 10

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