Real-Time Systems Versus Cyber-Physical Systems: Where is the Difference?

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1 Real-Time Systems Versus Cyber-Physical Systems: Where is the Difference? Samarjit Chakraborty TU Munich, Germany Joint work with Dip Goswami*, Reinhard Schneider #, Alejandro Masrur $, Anuradha Annaswamy + *TU Eindhoven, # AUDI, $ TU Chemnitz, + Massachusetts Institute of Technology and several collaborators from UPenn, Bosch, Linköping University, ETH Zurich

2 Control Systems Design Equations System identification system model Controller design controller Control system analysis 2

3 Control Systems Implementation Equations System identification system model Controller design controller Control system analysis Software Message scheduling Task mapping & scheduling Task partitioning Code generation Timing & performance analysis Are control objectives satisfied NO 3

4 The Design Flow Controller Design System identification system model Controller design controller Control system analysis Controller Implementation Message scheduling Task mapping & scheduling Task partitioning Code generation Timing & performance analysis Are control objectives satisfied NO 4

5 The Design Flow Controller Design Control theorist Controller Implementation Embedded systems engineer Design assumptions!! Infinite numerical accuracy!! Computing control law takes negligible time!! No delay from sensor to controller!! No delay from controller to actuator!! No jitter!!! Implementation reality!! Fixed-precision arithmetic!! Tasks have non-negligible execution times!! Often large message delays!! Time- and event-triggered communication 5

6 Controller Design The Design Flow These are implementation details Control theorist Not my problem! Controller Implementation Model-level assumptions are not satisfied by implementation Embedded systems engineer 6

7 Controller Design Semantic Gap Semantic gap between model and implementation Controller Implementation Research Questions?!! How should we quantify this gap?!! How should we close this gap? 7

8 Applications Model Current Design Flow! High-level requirements code generation Controller design m 1 m 2 HW/SW architecture Multiple processor units (PUs) connected via a shared bus T 1 T 2 T 3 T 4 Code synthesis & Task partitioning Task mapping Task and Message scheduling 8

9 Applications Model Current Design Flow! High-level requirements HW/SW architecture Multiple processor units (PUs) connected via a shared bus Unreliable hardware soft-errors, aging,! m 1 m 2 T 1 T 2 T 3 T 4 Fixed-precision arithmetic Delay / jitter message loss Controller design Code synthesis & Task partitioning Task mapping Task and Message scheduling 9

10 Current Design Flow! Applications High-level requirements T1 m1 T2 HW/SW architecture Multiple processor units (PUs) connected via a shared bus T3 m2 T4 Fixed-precision arithmetic Model Controller design Code synthesis & Task partitioning Delay / jitter message loss Unreliable hardware soft-errors, aging,! Task Algorithm & Architecture designed separately mapping followed by integration, testing, debugging,! Task and Message scheduling 10

11 Cyber-Physical Systems!! Tight interaction between computational (cyber) and physical systems!! Isolated design of the two systems leads to:!! Higher integration, testing and debugging costs!! Poor resource utilization (e.g., unnecessarily high sampling rates)!! Question:!! Can existing techniques from real-time & embedded systems be directly applied? We know hardware/software co-design!! Answer:!! New techniques are required!! Traditional embedded systems design have focused only on meeting deadlines 11

12 Control Tasks - Characteristics The deadlines are usually not hard for control-related messages DC motor: Speed Objective: A fraction of feedback signals being dropped 33% Drop 25% Drop 0% Drop Controllers can be designed to be robust to drops and deadline-misses Seconds 1 2

13 Control Tasks - Characteristics Sensitivity of control performance depends on the state of the controlled plant Speed h =20ms Disturbance Seconds h =200ms (1)! The computation requirement at the steady state is less, i.e., sampling frequency can be reduced (e.g., event-triggered sampling) (2)! The communication requirements are less at the steady state, (e.g., lower priority can be assigned to the feedback signals) 1 3

14 Bottomline!! Real-time Systems View!! Meeting deadlines is the center of attraction Control performance constraints reduced to satisfaction of real-time constraints!! CPS View!! Deadline takes the back seat!! As a result, the design space becomes bigger!! Resulting design is better, robust, cost-effective! 1 4

15 What about NCS? T 3 T4 Network T 2 m 2 m Controller m 1 Sensor Plant Networked Control Systems T 1! Take network characteristics into account when designing the control laws! Packet drops, delays, jitter! 1 5

16 What about NCS? Answer: ANCS T 3 T4 Network T 2 m 2 m Controller m 1 Plant Sensor Arbitrated Networked Control Systems T 1! ANCS We can design the network! By taking into account control performance constraints! Problem: How to design the network?! Given a network, how to design the controller?! NCS problem! Co-design Problem: How to design the network and the controller together? 1 6

17 First, a simple case 1 7

18 Embedded control systems Physical System Sensors Actuators Continuous-time A/D D/A Real-time applications Multimedia applications! Shared Communication Shared Computation Discrete-time Embedded platform: Control software 1 8

19 Dynamical Systems: DC Motor The time dependence of the various states of dynamical systems is described by a set of difference or differential equations. J = moment of inertia of the rotor b = system damping ratio, K = EMF and Torque constant, R = armature resistance, L = armature inductance, i = armature current, V = input, DC terminal voltage! = output, position of shaft i 1 9

20 System models! Input-output model (Transfer function) suitable for frequency domain analysis! The relation between input u(t) and output y(t) (observed variable e.g., position, temperature)! The analysis is done in frequency domain by taking Laplace transform where s is the complex frequency! State-space model suitable for time domain analysis! Represent the system in terms of a number of internal states

21 Example Computing state-space model (1) System dynamics: (2) Input and output: Output Input (3) States: (4) State-space model: 2 2 1

22 Laplace Transform 2 2

23 Computing transfer function Example (1) System dynamics: (2) Input and output: Output Input (3) Take Laplace transform with zero initial condition: (4) Transfer function: 2 3

24 State-space to Transfer Function State-space model Laplace transform And x(0) = 0 2 4

25 Poles and Zeros! Given transfer function, the system poles are roots of the polynomial D(s) and the system zeros are roots of polynomial N(s)! Example Zeros: -0.2, -1 Poles: 1, 2, 3 2 5

26 Eigenvalues of a Matrix 2 6

27 Eigenvalues of a Matrix 2 7

28 Characteristic equation! Alternatively, system poles can also be computed from the state-space model by computing Characteristic Equation which is given by:! System poles are the roots of Characteristic polynomial! System poles are the eigenvalues of A 2 8

29 Stability There are various notions --! Bounded-Input Bounded-Output (BIBO) stability! Stability in the sense of Lyapunov! Asymptotic stability! Exponential stability!! Our lecture is mainly confined to the following aspects: (1)! x(t), y(t), u(t) <! (all signals are bounded), (2)! y(t) " 0 as t "! (asymptotic stability) 2 9

30 Implications of System Poles on Stability! Consider the following system (discrete model)! Intuition behind the continuous time mo 3 0

31 Stability condition: continuous-time case!!! Stable system All poles should have negative real part Marginally stable system One or multiple poles are on imaginary axis and all other poles have negative real parts Unstable system One or more poles with positive real part. Marginally stable Stable Unstable 3 1

32 Stability! Example Poles at +1, +2, +3 Unstable!! Example Poles at 0, 0 Marginally stable! Example Poles at ±i2 Marginally stable 3 2

33 System dynamics: Summary State-space Transfer function Roots of Poles at +10.9, -3.4 Poles at +10.9, -3.4 Unstable! 3 3

34 Summary How to compute system poles? 1.! Roots of 2.! Eigenvalues of system matrix A 3.! Solution of system characteristics equation 4.! Roots of D(s) for the transfer function!!! Stable system All poles with negative real part Marginally stable system One or multiple poles are on imaginary axis and all other poles have negative real parts Unstable system One or more poles with positive real part. 34

35 Controller Design: Continuous Model! We have a linear system given by the state-space model! For n-dimensional Single-Input-Single-Output (SISO) systems! Objective! u =? 35

36 Controller Design: Continuous Model! Control law r = reference K = feedback gain F = static feedforward gain! How to design K?! How to design F? 36

37 Computing Feedback Gain! Choose the desired closed-loop poles at! Using Ackermann s formula we get! Poles of (A+BK) are at 37

38 Static Feedforward Gain Closed-loop system Taking Laplace transform F should be chosen such that y(t) " r (constant) as t "! i.e., Using final value theorem 38

39 Digital Platform: Sample and Hold Processor clock D/A u(t k ) u(t) x(t) x(t k ) Continuous-time Hold Sampler system A/D Control Algorithm D/A " digital-to-analog converter A/D " analog-to-digital converter! Input u(t) is piecewise constant! Look at the sampling points 39

40 ZOH Sampling x(t) t " Sampling period = h x(t k ) t k t k+1 t k+2 u(t) t " 40

41 Design: Step 1 (Discretization) ZOH periodic sampling with period = h 41

42 Design: Step 2 (Controller Design)!! Given system: Control law: Objectives (i)! Place system poles (ii)! Achieve y " r as t "! (iii) Design K and F 1.! Check controllability of (!,") " must be controllable. # must be invertible. 2.! Apply Ackermann s formula 3.! Feedforward gain 42

43 Step 2! Given! The control input such that closed-loop poles are at! Using Ackermann s formula: 43

44 Continuous Vs Discrete Time Continuous-time ZOH periodic sampled Input: Controllability matrix: Input: Controllability matrix: 44

45 The Real Case Feedback loop T m : measure Loop start u = K*[x1(i);x2(i)] + r*f; xkp1 = phi*[x1(i);x2(i)]+ Gamma*u; T c : compute T a : actuate x1(i+1) = xkp1(1); x2(i+1) = xkp1(2); Loop end T m sensor task T c controller task T a actuator task 45

46 Control Loop Feedback loop Sensor reading $ = sensor-to-actuator delay T m : measure T m T c : compute T c T a : actuate T a h= sampling period Actuation Ideal design assumes: or 46

47 Control Task Triggering!!! In general, T m and T a tasks consume negligible computational time and are time-triggered T c needs finite computation time and is preemptive When multiple tasks are running on a processor, T c can be preempted T m T c T a $ $ $ $ Sensor-to-actuator delay: $ 47

48 Control Task Model: Constant Delay T c preemption wait T m Deadline D c T a T m Sampling period = h 48

49 Design Steps Real-time tasks + control applications Task models Partial redesign Overall response time analysis Stage I Schedulability test +Timing properties Controller design Stage II Design objectives met? No Yes 49

50 Response Time Analysis! Periodic tasks with fixed-priority scheduling! Solution to a fixed point computation 50

51 Controller design steps for D c < h Continuous-time model ZOH sampling with period h and constant sensor-to-actuator delay D c Step I New discrete-time model: Sampled-data model Step II Controller design based on the sampled-data model Objectives (i)! Place system poles (ii)! Achieve y " r as t "! 51

52 Snapshot of One Sampling Period What happens within one sampling period? x(t k ) x(t k+1 ) T c D c t k t k+1 52

53 53

54 54

55 55

56 Sampled-data Model Continuous-time model ZOH sampling with period h and constant sensor-to-actuator delay D c! Sampled-data model End of Step 1 56

57 Augmented System! We define new system states:! With the new definition of states, the state-space becomes where the augmented matrices are defined as follows 57

58 Controller Design for D c < h!! Given system: Control law: Objectives (i)! Place system poles (ii)! Achieve y " r as t "! (iii) Design K and F 1.! Check controllability of " must be controllable. # must be invertible where # is defined as follows 2.! Apply Ackermann s formula 3.! Feedforward gain End of Step II 58

59 Summary: Design for D c < h Continuous-time model Sampled-data model Augmented system Controller gains 59

60 A More Complex Case (involves stability analysis of switched systems) 6 0

61 CPS-Oriented Design Example!! Control over FlexRay!! FlexRay is made up of time-triggered (TT) and eventtriggered (ET) segments!! Conventional design!! Use time-triggered segment for control messages one slot for each control message!! Expensive Challenge: Can we achieve the same control performance with fewer time-triggered slots? 6 1

62 FlexRay Event Vs Time-triggered Asynchronous task Jitter, lost/unused data message x task Synchronous task message task Predictable x 6 2

63 Communication Schedules Time-triggered (TT)!! The temporal behavior is predictable!! The bandwidth utilization is poor!! Availability is limited Event-triggered (ET)!! The temporal behavior is unpredictable!! The bandwidth utilization is better!! Availability is higher Conventional design: Use TT for control-messages Problem: Can we use fewer TT slots but still have good control performance? 6 3

64 Quality of Control vs. System State Transient State Steady State r Settling time t Observations "! The performance of a control application is more sensitive to the applied control input in transient state compared to that in steady-state "! ET communication for the control signals is good enough in the steadystate "! TT communication is better suited for transient state 6 4

65 Mode Switching Scheme Plant in Steady- State M!" TT : ET : Schedule : Schedule : Controller : After S "#! K "#! Plant in Transient Mode Change Protocol Mode Change Request Controller : Plant in Transient M!! x[k]! x[k] > E "# S! " " K! " " Plant in Steady- State After dwell time T! "# 6 5

66 Example!! We consider two distributed control applications communicating via a hybrid communication bus!! We apply state-feedback controller for both, i.e., u[k] =Fx[k] 6 6

67 Performance with TT Communication Control Gains Quality of control C 1 Converges very fast without any oscillation C 2 6 7

68 Performance with ET Communication Control Gains Quality of control C 1 Large oscillations and long settling time C 2 6 8

69 Performance with Switching We have one shared TT communication slot. The control messages are transmitted via ET communication when they are in steady state and switches to TT communication when transient state occurs due to some disturbance Quality of control C 1 Performance is better than that with ET communication but we consume less TT communication slots C 2 6 9

70 Experimental Setup 7 0

71 Experimental Results Purely event-triggered Mixed time-/event-triggered Purely time-triggered 71

72 Controller Design with Signal Drops 7 2

73 Control Law for stable samples Sensor: x[k] x[0] x[1] x[2] x[3] x[4] x[5] $ % " # h! = 1 $ % " # h! = 1 $ % " # h! = 1 $ % " # h! = 1 $ % " # h! = 1 $ % " # h! = 1 Actuator: u[k] -- f(x[0]) f(x[1]) f(x[2]) f(x[3]) f(x[4]) Stable samples: Control Law: Closed-loop Dynamics: 0!"! h u[ k] = Fx[ k! 1] x[ k + 1] = Ax[ k] + BFx[ k! 1] F ischosen s.t. x[ k] " 0 if k "!

74 Control with stable and unstable Samples Sensor: x[k] x[0] x[1] x[2] x[3] x[4] x[5] $ % " # h! = 1 $ % " # h! = 1 $ % " # h! = 1 $ % " # h! = 2 $ % " # h! = 1 $ % " # h! = 1 Actuator: u[k] -- f(x[0]) f(x[1]) f(x[2]) f(x[2]) f(x[4]) Sampling instant: k 0 stable stable stable unstable stable Proposed Control $! Fx[ k * 1] u[ k] = #! ) + 0 if! " ( h ' & Scheme: if % 1, ) + ( h or ' & = 1 or unstable stable samples samples time

75 Asymptotic Stability The distributed control application is asymptotically stable as long as the ratio between number of stable and unstable samples is greater than or equal to certain upper bound, i.e., the condition for guaranteed asymptotic stability is (! is a positive integer) number of stable samples number of unstable samples! µ 1 Therefore, we allow a fraction µ of samples to be unstable or violate the deadlines but still guarantee asymptotic stability!

76 +,-./0" Intuitive Proof "9:"2;-"<9,2.95"1012-="81"431->"9,"2;-":3<2"2;32"2;-"" +,-./0">-<.-31-1"-A-,"8:"2;-.-"81"59<35"8,<.-31-"" 8,"-,-./0"4-<361-"9:"6,12345-"13=B5-1" " 6,12345-"! = 2! = 3 $ % " & = # h!!! =1! = 1! =1!" #" $" %" &" '" (" )" *"!"#$%&'()*+ (

77 Intuitive Proof Illustration "! Does exist for any discrete-time system?!! Yes. Let u assume the closed-loop dynamics at: Stable samples: Unstable samples: As the closed-loop dynamics is stable at the stable samples, What happens if one unstable sample occurs after Resultant Dynamics stable samples? Therefore, and the system is stable 7 7

78 Example: Control over FlexRay ) & ) 0.1& Plant : x[ k + 1] = ' $ x[ k] ' 0.7 $ ' # # # $ + ' $ u[ k] '( # 3.6 # 1.2 # 2.8 $ % '( 0.5$ % Open # loop Poles: [# 1.57, # 1.4, # ], Highly Unstable System Plant Controller : u[ k] = Fx[ k # 1] = [# Design Goal ( stability) : x[ k] " 0 as k "! Sampling Interval : 40ms # # ] x[ k # 1] We have found that the closed-loop system with the above Controller is stable as long as the ratio between the number of stable and unstable samples µ! 52

79 Scheduling: Example 1 Stable Example: We choose a schedule such that µ =! C55"13=B5-1""-DB-.8-,<-">-530"5-11"2;3,"" &!"=1E"8F-FE">-530"8,"2-.=1"9:"13=B5-1"81"#" 7012-="81"12345-"31"" x[ k] " 0 as k "!

80 Scheduling: Example 2 Stable Example: We choose a schedule such that µ = "13=B5-1" G,12345-"13=B5-1" 7012-="81"12345-"31"" x[ k] " 0 as k "! 9:"6,12345-"13=B5-1"

81 Scheduling: Example 3 Unstable Example: We choose a schedule such that µ = "13=B5-1" G,12345-"13=B5-1" 7012-="81"6,12345-"31"" x [ k] "! as k "!

82 Applications Model Current Design Flow! High-level requirements HW/SW architecture Multiple processor units (PUs) connected via a shared bus Unreliable hardware soft-errors, aging,! m 1 m 2 T 1 T 2 T 3 T 4 Fixed-precision arithmetic Delay / jitter message loss Controller design Code synthesis & Task partitioning Task mapping Task and Message scheduling 8 2

83 Open Issues! Integration of control theory, program analysis, embedded systems modeling & analysis! How to synthesize implementation platform & software that minimizes error?! Cross-layer modeling & optimization techniques necessary (interplay between delay & numerical accuracy)! Open issues in hardware/circuit design! dynamically adjust precision during runtime or based on plant state (using reconfigurable computing)! harden hardware components to reduce soft-error rates 8 3

84 Concluding Remarks!! Viewing cyber-physical systems not as traditional real-time systems!! Breaks traditional concepts of abstraction?!! Current practice:!! Specify control laws!! Specify architecture and schedules!! Test and debug (modify architecture and schedule)!! Problem:!! Synthesize the architecture/schedule from control performance constraints!! Large constrained optimization problem 8 4

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