Introduction to Embedded Systems

Transcription

1 Introduction to Embedded Systems Sanjit A. Seshia UC Berkeley EECS 149/249A Fall : E. A. Lee, A. L. Sangiovanni-Vincentelli, S. A. Seshia. All rights reserved. Chapter 9: Memory Architectures Role of Memory in Embedded Systems Traditional roles: Storage and Communication for Programs Communication with Sensors and Actuators Often much more constrained than in general-purpose computing Size, power, reliability, etc. Can be important for programmers to understand these constraints EECS 149/249A, UC Berkeley: 2 1

2 Memory Architecture: Issues Types of memory volatile vs. non-volatile, SRAM vs. DRAM Memory maps Harvard architecture Memory-mapped I/O Memory organization statically allocated stacks heaps (allocation, fragmentation, garbage collection) The memory model of C Memory hierarchies scratchpads, caches, virtual memory) Memory protection segmented spaces These issues loom larger in embedded systems than in general-purpose computing. EECS 149/249A, UC Berkeley: 3 Non-Volatile Memory Preserves contents when power is off EPROM: erasable programmable read only memory Invented by Dov Frohman of Intel in 1971 Erase by exposing the chip to strong UV light EEPROM: electrically erasable programmable read-only memory Invented by George Perlegos at Intel in 1978 Flash memory Invented by Dr. Fujio Masuoka at Toshiba around 1980 Erased a block at a time Limited number of program/erase cycles (~ 100,000) Controllers can get quite complex Disk drives Not as well suited for embedded systems USB Drive Images from the Wikimedia EECS Commons 149/249A, UC Berkeley: 4 2

3 Volatile Memory Loses contents when power is off. SRAM: static random-access memory Fast, deterministic access time But more power hungry and less dense than DRAM Used for caches, scratchpads, and small embedded memories DRAM: dynamic random-access memory Slower than SRAM Access time depends on the sequence of addresses Denser than SRAM (higher capacity) Requires periodic refresh (typically every 64msec) Typically used for main memory Boot loader On power up, transfers data from non-volatile to volatile memory. EECS 149/249A, UC Berkeley: 5 Example: Die of a STM32F103VGT6 ARM Cortex-M3 microcontroller with 1 megabyte flash memory by STMicroelectronics. Image from Wikimedia Commons EECS 149/249A, UC Berkeley: 6 3

4 Memory Map of an ARM Cortex TM -M3 architecture Defines the mapping of addresses to physical memory. Note that this does not define how much physical memory there is! EECS 149/249A, UC Berkeley: 7 Another Example: Atmel AVR The AVR is an 8-bit single chip microcontroller first developed by Atmel in The AVR was one of the first microcontroller families to use on-chip flash memory for program storage. It has a modified Harvard architecture. 1 AVR was conceived by two students at the Norwegian Institute of Technology (NTH) Alf-Egil Bogen and Vegard Wollan. 1 A Harvard architecture uses separate memory spaces for program and data. It originated with the Harvard Mark I relay-based computer (used during World War II), which stored the program on punched tape (24 bits wide) and the data in electro-mechanical counters. EECS 149/249A, UC Berkeley: 8 4

5 A Use of AVR: Arduino Arduino is a family of open-source hardware boards built around either 8-bit AVR processors or 32-bit ARM processors. Example: Atmel AVR Atmega pin DIP on an Arduino Duemilanove board Image from Wikimedia Commons EECS 149/249A, UC Berkeley: 9 Another example use of an AVR processor The irobot Create Command Module Atmel ATMega 168 Microcontroller EECS 149/249A, UC Berkeley: 10 5

6 ATMega 168: An 8-bit microcontroller with 16-bit addresses AVR microcontroller architecture used in irobot command module. Why is it called an 8-bit microcontroller? EECS 149/249A, UC Berkeley: 11 ATMega168 Memory Architecture An 8-bit microcontroller with 16-bit addresses irobot command module has 16K bytes flash memory (14,336 available for the user program. Includes interrupt vectors and boot loader.) 1 k bytes RAM Source: ATmega168 Reference Manual The 8-bit data is why this is called an 8-bit microcontroller. Additional I/O on the command module: Two 8-bit timer/counters One 16-bit timer/counter 6 PWM channels 8-channel, 10-bit ADC One serial UART 2-wire serial interface EECS 149/249A, UC Berkeley: 12 6

7 Questions to test your understanding 1. What is the difference between an 8-bit microcontroller and a 32-bit microcontroller? 2. Why use volatile memory? Why not always use nonvolatile memory? EECS 149/249A, UC Berkeley: 13 Memory Organization for Programs Statically-allocated memory Compiler chooses the address at which to store a variable. Stack Dynamically allocated memory with a Last-in, First-out (LIFO) strategy Heap Dynamically allocated memory EECS 149/249A, UC Berkeley: 14 7

8 Statically-Allocated Memory in C char x; int main(void) { Compiler chooses what address to use for x, and the variable is accessible across procedures. The variable s lifetime is the total duration of the program execution. EECS 149/249A, UC Berkeley: 15 Statically-Allocated Memory with Limited Scope void foo(void) { static char x; Compiler chooses what address to use for x, but the variable is meant to be accessible only in foo(). The variable s lifetime is the total duration of the program execution (values persist across calls to foo()). EECS 149/249A, UC Berkeley: 16 8

9 Variables on the Stack ( automatic variables ) void foo(void) { char x; stack As nested procedures get called, the stack pointer moves to lower memory addresses. When these procedures, return, the pointer moves up. When the procedure is called, x is assigned an address on the stack (by decrementing the stack pointer). When the procedure returns, the memory is freed (by incrementing the stack pointer). The variable persists only for the duration of the call to foo(). EECS 149/249A, UC Berkeley: 17 Question 1 What is meant by the following C code: char x; void foo(void) { EECS 149/249A, UC Berkeley: 18 9

10 Answer 1 What is meant by the following C code: char x; void foo(void) { An 8-bit quantity (hex 0x20) is stored at an address in statically allocated memory in internal RAM determined by the compiler. EECS 149/249A, UC Berkeley: 19 Question 2 What is meant by the following C code: char *x; void foo(void) { EECS 149/249A, UC Berkeley: 20 10

11 Answer 2 What is meant by the following C code: char *x; void foo(void) { An 16-bit quantity (hex 0x0020) is stored at an address in statically allocated memory in internal RAM determined by the compiler. EECS 149/249A, UC Berkeley: 21 Question 3 What is meant by the following C code: char *x, y; void foo(void) { y = *x; EECS 149/249A, UC Berkeley: 22 11

12 Answer 3 What is meant by the following C code: char *x, y; void foo(void) { y = *x; The 8-bit quantity in the I/O register at location 0x20 is loaded into y, which is at a location in Internal SRAM determined by the compiler. EECS 149/249A, UC Berkeley: 23 Question 4 char foo() { char *x, y; y = *x; return y; char z; int main(void) { z = foo(); Where are x, y, z in memory? EECS 149/249A, UC Berkeley: 24 12

13 Answer 4 char foo() { char *x, y; y = *x; return y; char z; int main(void) { z = foo(); x occupies 2 bytes on the stack, y occupies 1 byte on the stack, and z occupies 1 byte in static memory. EECS 149/249A, UC Berkeley: 25 Question 5 What is meant by the following C code: void foo(void) { char *x, y; x = &y; * EECS 149/249A, UC Berkeley: 26 13

14 Answer 5 What is meant by the following C code: void foo(void) { char *x, y; x = &y; * 16 bits for x and 8 bits for y are allocated on the stack, then x is loaded with the address of y, and then y is loaded with the 8-bit quantity 0x20. EECS 149/249A, UC Berkeley: 27 Question 6 What goes into z in the following program: char foo() { char y; uint16_t x; y = *x; return y; char z; int main(void) { z = foo(); EECS 149/249A, UC Berkeley: 28 14

15 Answer 6 What goes into z in the following program: char foo() { char y; uint16_t x; y = *x; return y; char z; int main(void) { z = foo(); z is loaded with the 8-bit quantity in the I/O register at location 0x20. EECS 149/249A, UC Berkeley: 29 Quiz: Find the flaw in this program (begin by thinking about where each variable is allocated) int x = 2; int* foo(int y) { int z; z = y * x; return &z; int main(void) { int* result = foo(10);... EECS 149/249A, UC Berkeley: 30 15

16 Solution: Find the flaw in this program int x = 2; int* foo(int y) { int z; z = y * x; return &z; statically allocated: compiler assigns a memory location. arguments on the stack automatic variables on the stack int main(void) { int* result = foo(10);... program counter, argument 10, and z go on the stack (and possibly more, depending on the compiler). The procedure foo() returns a pointer to a variable on the stack. What if another procedure call (or interrupt) occurs before the returned pointer is de-referenced? EECS 149/249A, UC Berkeley: 31 Watch out for Recursion!! Quiz: What is the Final Value of z? void foo(uint16_t x) { char y; y = *x; if (x > 0x100) { foo(x 1); char z; void main() { z = 0x10; foo(0x04ff); EECS 149/249A, UC Berkeley: 32 16

17 Dynamically-Allocated Memory The Heap An operating system typically offers a way to dynamically allocate memory on a heap. Memory management (malloc() and free()) can lead to many problems with embedded systems: Memory leaks (allocated memory is never freed) Memory fragmentation (allocatable pieces get smaller) Automatic techniques ( garbage collection ) often require stopping everything and reorganizing the allocated memory. This is deadly for real-time programs. EECS 149/249A, UC Berkeley: 33 Other Issues Memory hierarchy Cache: A subset of memory addresses is mapped to SRAM Accessing an address not in SRAM results in cache miss A miss is handled by copying contents of DRAM to SRAM Scratchpad: SRAM and DRAM occupy disjoint regions of memory space Software manages what is stored where Segmentation Logical addresses are mapped to a subset of physical addresses Permissions regulate which tasks can access which memory See your textbook for more details. EECS 149/249A, UC Berkeley: 34 17

18 Memory Hierarchy Memorymapped I/O devices CPU registers Cache or scratch pad Main memory Disk or Flash register address fits within one instruction word SRAM DRAM Here, the cache or scratchpad, main memory, and disk or flash share the same address space. EECS 149/249A, UC Berkeley: 35 Memory Hierarchy CPU registers register address fits within one instruction word Memorymapped I/O devices Cache or scratch pad SRAM Main memory DRAM Disk or Flash Here, each distinct piece of memory hardware has its own segment of the address space. This requires more careful software design, but gives more direct control over timing. EECS 149/249A, UC Berkeley: 36 18

19 Direct-Mapped Cache A set consists of one line Set 0 1 valid bit t tag bits B = 2 b bytes per block Set 1 t bits s bits b bits Tag Set index Block offset m-1 Address 0... If the tag of the address matches the tag of the line, then we have a cache hit. Otherwise, the fetch goes to main memory, updating the line. Set S CACHE EECS 149/249A, UC Berkeley: 37 Set-Associative Cache A set consists of several lines Set 0 1 valid bit t tag bits B = 2 b bytes per block... t bits s bits b bits Tag Set index Block offset m-1 0 Address Tag matching is done using an associative memory or content-addressable memory. Set 1 Set S CACHE EECS 149/249A, UC Berkeley: 38 19

20 Set-Associative Cache A set consists of several lines Set 0 1 valid bit t tag bits B = 2 b bytes per block... t bits s bits b bits Tag Set index Block offset m-1 0 Address A cache miss requires a replacement policy (like LRU or FIFO). Set 1 Set S CACHE EECS 149/249A, UC Berkeley: 39 Your Lab Hardware (2014 & 2015) myrio 1950/1900 (National Instruments) Xilinx Zynq Z-7010 ARM Cortex-A9 MPCore dual core processor Real-time Linux Xilinx Artix-7 FPGA Preconfigured with a 32-bit MicroBlaze microprocessor running without an operating system ( bare metal ). EECS 149/249A, UC Berkeley: 40 20

21 Xilinx Zynq Dual-core ARM processor + FPGA + rich I/O on a single chip. EECS 149/249A, UC Berkeley: 41 Microblaze I/O Architecture Source: Xilinx EECS 149/249A, UC Berkeley: 42 21

22 Microblaze I/O Architecture Source: Xilinx EECS 149/249A, UC Berkeley: 43 0xFFFFFFFF Berkeley Microblaze Personality Memory Map MicroBlaze 50MHz MEMORY BRAM UART0 UART1 ADC Subsystem TIMER Unmapped Area ADC subsystem Unmapped Area Debugger Unmapped Area UARTs Unmapped Area Timer Unmapped Area Interrupt controller 0xC220FFFF 0xC x8440FFFF 0x x8402FFFF 0x x83C0FFFF 0x83C x8180FFFF 0x Debugger Unmapped Area Interrupt controller Memory for Instructions and Data 0x0000FFFF 0x EECS 149/249A, UC Berkeley: 44 22

23 Conclusion Understanding memory architectures is essential to programming embedded systems. EECS 149/249A, UC Berkeley: 45 23