Understanding Frequency Synthesis

Transcription

1 Understanding Frequency Synthesis By Erik Mentze, Sr. Systems Engineer, Cypress Semiconductor Coniguring a hase Locked Loop LL or a given requency synthesis application can be, at the same time, both a quick and easy process as well as a time consuming, tedious, and iterative process. This dual nature in LL system design arises rom the number o loop parameters that need to be appropriately dialed in or a given application. As will be discussed in this article, there are two categories o loop parameters that must be considered: requency synthesis parameters and perormance parameters. The ormer sets up the loop to generate the correct requency while the later dictates the quality o put requency with quality being a term relative to the given application. The interplay between these two categories o parameters is where designers spend the bulk o their time. Ater determining a set o requency synthesis parameters that meet the system needs, we then attempt to dial in the perormance parameters. However, when we reach the end o optimizing the loop, there is always the doubt: did I choose the best possible requency synthesis parameters? erhaps there is a dierent set that will run cleaner and consume less power or have more margin. It is these design choices that this paper will attempt to shed some common sense design principles upon. An Overview o LL Frequency Synthesis At the most undamental level, the goal o any requency synthesizer is, based on a given reerence requency, to generate a desired put requency. That is, solve: κ 1 re where κ is the requency scaling constant, sometimes reerred to as the normalized requency. Any requency synthesizer circuit is simply a mechanism or approximating κ. A LL requency synthesizer approximates κ by inserting divide blocks between the reerence oscillator and the put clock. Then, using a eedback loop with a phase detector to maintain phase coherence between the two dividers, the desired requency is generated. The block diagram or this is shown in Figure 1. This is the general orm o a charge pump integer divide phase locked loop a very common topology used or requency synthesis. Figure 1. Block diagram o a basic integer divide LL. Reerence Oscillator re FD Loop Filter VCO N Three divide blocks are used to approximate the value o κ: the reerence divider, the eedback divider, and the put divider N. It can be readily shown that κ is deined or this type o requency synthesizer as: κ N 2 Combining equations 1 and 2, the relationship between input and put requency is: Understanding Frequency Synthesis age 1 o 8

2 N 3 re It is these,, and N divide values that we reer to as the requency synthesis parameters. These values setup the gross unctionality o the loop and must be chosen to set the desired put requency. One common way o determining these values is to divide the put requency by the reerence requency, and reduce the raction: re N The diiculty in solving equation 4, or any arbitrary reerence and put requency, is that there are three degrees o reedom limited only by the range o divide values,, and N can take on. The most common technique or solving equation 4 is a search algorithms. Such algorithms work by searching the solution space, looking or sets o,, and N values that will result in the desired κ value. They are, in essence, triple nested loops that search all possible,, and N values. Common simpliications are to set N equal to one, equal to one, or both. These simpliications are based on system design needs. Analysis o all three o these simpliications is a subset o the general case shown in igure 1 and represented by equation 4. I both and N are set equal to one, then the maximum resolution o the put requency is limited to the reerence requency, making it possible to synthesize only integer multiples o the reerence. In this case determining the value o is reduced to a simple matter o arithmetic. I just or N is set equal to one, then only a single coniguration exists with respect to a minimum / or N/ ratio or synthesizing the desired put. Determining this ratio is then a matter o raction reduction. The use o all three divide blocks introduces an added layer o generality to the hardware that enables the direct reuse o the LL through programming or many dierent requency synthesis applications. However, this generality also results in a signiicantly more complex problem in determining the values o,, and N to use. Speciically, it results in multiple requency synthesis parameter sets that are valid or a given reerence and put requency, all o which can have drastically dierent perormance characteristics band width, phase margin, jitter, phase noise, power consumption, etc. An additional coniguration that is commonly used in programmable SoCs is to have multiple put dividers. This allows or the synthesis o multiple puts at dierent requencies. Figure 2 illustrates this coniguration. It is important to note that each put is an integer multiple o the VCO requency. This topology emphasizes the importance o selecting the right VCO requency so as to maximize the number o system clocks that can be generated o o the single LL. Figure 2. Block diagram o a basic integer divide LL with multiple put dividers. 4 Reerence Oscillator re FD Loop Filter VCO N1 1 N2 2 N3 3 Understanding Frequency Synthesis age 2 o 8

3 A uick Walk Around the Loop With the basic input-put relationship in hand, we next need to take a walk around the LL and consider the steady-state operating condition. When the loop is in lock, the put o the divider and the divider have matched phase and requency and the put o the FD is tri-stated, leaving the loop ilter voltage unchanged and the VCO requency steady. As the loop ilter voltage changes due to noise, charge pump leakage, and capacitor charge leakage, the VCO requency will drit. The FD observes this drit by comparing the VCO put to the reerence oscillator requency through the and divides respectively and causes the charge pump to either pump up or pump down the loop ilter voltage. Once the correct loop ilter voltage is reached again, the FD put is tri-stated and the loop ilter voltage is let unmodiied. During this normal mode o operation, the FD requency the requency at which the hase-frequency Detector runs plays a central role. The FD requency is set by the reerence oscillator requency divided by the reerence divider: re pd 5 In the steady-state condition, the LL loop dynamics orce the VCO put requency, divided by the divider, to also be equal to the FD requency: VCO pd 6 By re-arranging equations 5 and 6, we can now make a key observation: the reerence requency and the VCO requency must both have the FD requency as a common divisor: re, pd VCO 7 pd Any valid choice o and will result in a FD requency that is a common divisor o both the reerence requency and VCO requency. This allows us to take a undamentally dierent approach to determining the and divide values than the raction reduction method illustrated in equation 4. It is also worth noting that the FD requency will also play a central role in the LL perormance parameters, which we will discuss in more detail later. For now, let s look at selecting the and divide values based on the FD requency. Determining and Values Based on the FD Frequency Since we know that the FD requency must be a common divisor o the reerence requency and VCO requency, let s choose it to be the greatest common divisor. By doing this we will minimize and, and maximize the FD requency: re 8 GCD, re 9 GCD, re The range o valid VCO requencies and N divide values is dictated by the ollowing relationship: min N max 10a and all valid VCO requencies are ound by multiplying the list o N divide values by : Understanding Frequency Synthesis age 3 o 8

4 N 10b Thus, given a reerence requency and desired put requency, we can use equations 8, 9, and 10 to determine all possible sets o requency synthesis parameters sets o, and N. There is only one small problem with equations 8 and 9: the Greatest Common Divisor unction is only deined on the set o integers. We usually want to synthesis real requencies, not integer requencies. This means that we need to make a ew mathematical adjustments to equations 8 and 9 to make them useul in practical applications. This is done by irst recognizing that the reerence requency and put requency are both real numbers, which implies that they can always be represented as ratios o integers: re re, re 11 By multiplying both ractions by their denominators we will transorm them into integers since the product o two integers is always an integer: re re re re 12 re 13 re We then can take the greatest common divisor o the result: GCD, 14 re re This is almost the result we want. It is the GCD o two requencies that are related to our original reerence and VCO requency. We can get back to the original values by dividing the term we used to transorm them: GCD re, re re 15 This result is equal o the greatest common divisor o our original reerence requency and VCO requency. I we deine a unction called the greatest common divisor o rational numbers GCDR as: where GCDR re, GCD θ, θ θ re 16 θ LCM den, den 17 re note that LCM is the Least Common Multiple and den is the denominator part o re and respectively, then we can solve or and using the ollowing equations: Understanding Frequency Synthesis age 4 o 8

5 re 18 GCDR, re 19 GCDR, re By solving these equations or all VCO requencies ound in equation 10, the set o all divide values that will synthesize our desired put requency rom our given reerence requency is ound. This, however, is a lot o symbols; let s now look at an illustrative example. An Illustrative Example For this example, we will synthesize a 50MHz put rom a MHz reerence a common video requency. Assume the VCO has a requency range o 100MHz to 400MHz. First, all possible N divide values are determined using 10: 100MHz 400MHz 2 N 8 50MHz 50MHz Based on this list o N divide values, the corresponding VCO requencies can be solved or and then the and values can be solved or using 18 and 19. For N 2, the ollowing calculations are made: 1. N re θ LCM den 315, den 100 LCM 22, re re GCD θ, 100 θ 22 θ FD GCD, re 315 GCD θ, 100 θ 22 θ FD GCDR, re All results or this example N2 through N8 are shown in table 1. This is the complete set o requency synthesis parameters that are possible given our reerence requency and desired put requency. Table 1. Summary o Example Results Understanding Frequency Synthesis age 5 o 8

6 N Fre F pd [MHz] [MHz] [MHz] [MHz] Choosing an Optimal Coniguration Now that we have conidently ound the set o all possible requency synthesis parameters that meet our needs, we can turn our attention to selecting the perormance parameters. Several common parameters that are optimized in various applications are: power consumption, startup time, settling time, jitter, and phase noise. Table 2 summarizes these parameters, the corresponding key loop parameters, the design equations needed or tradeos, and the how to optimize them. It is important to note the role that FD requency plays in each o these parameters. ower ower is dominated by the VCO requency, charge pump current, and divide block settings. Most VCO architectures require larger tail currents to achieve higher requencies. So as requency increases, so does power consumption. Charge pump current is discharged once or each FD period. When larger charge pump currents are required or loop stability or ast startup / settling time more power is consumed per FD period. Clock dividers dissipate power at each clock edge. Larger clock divide values require more divide cells to transition, consuming more power. Startup Time / Settling Time The startup and settling time or a charge pump LL is dominated by the loop natural requency. This parameter can be thought o as the requency slew rate o the LL. It quantiies how ast the LL can change the put requency. It is proportional to the VCO gain and charge pump current, and inversely proportional to the eedback divide value and loop ilter capacitance. Since the LL put requency is set by the VCO requency, when we want to orce a large step in the put requency either rom zero at startup or rom one setting to another we need to orce a large step in the VCO control voltage. This is accomplished by the charge pump dumping a large amount o charge onto the loop ilter cap. The amount o requency change per volt increase on the loop ilter is set by the VCO gain. The rate at which the loop ilter voltage is updated is set by the FD requency. Jitter Cycle-to-Cycle Cycle-to-Cycle jitter the change in period length rom one period to the next can easily be dominated by the individual blocks o the LL VCO, dividers, reerence oscillator, creating a situation where no loop parameter changes can improve perormance. I you are working with a low noise LL, then loop parameter settings can make a signiicant improvement. Similar to startup time / settling time, the FD requency and VCO gain play a key role. Higher FD requencies mean that the LL loop ilter voltage is rereshed at a higher rate. This prevents the loop ilter voltage rom driting. By using a large loop ilter capacitance, the amount o voltage drit per FD period is minimized. Because the VCO gain dictates how ar the put requency drits per unit voltage drit on the loop ilter, lower VCO gain makes the LL less sensitive to loop ilter voltage drit. hase Noise Optimizing phase noise is highly application dependent, but a ew general observations can be made. hase noise contributed by the reerence oscillator can be suppressed by setting the LL to a lower closed loop bandwidth. hase noise contributed by the VCO can be suppressed by setting the LL to a higher closed loop bandwidth. hase noise divides down proportional to the put divide setting. I the put divider is a low noise divider, then running the VCO at a higher requency and dividing the put requency down will result in a phase noise improvement. Understanding Frequency Synthesis age 6 o 8

7 Table 2. Summary o key LL perormance parameters arameter Key Loop arameters Key Design Equations Optimization ower Startup Time Settling Time Jitter cycle-to-cycle hase Noise VCO requency FD Frequency pd Charge pump Current I chp Values,, N FD Frequency pd Charge ump Current I chp Loop Filter Capacitance C VCO Gain K FD Frequency pd Loop Filter Capacitance C VCO Gain K Closed Loop Bandwidth LL Component hase Noise ω n natural requency K VCO gain Hz/V I chp charge pump current A/rad C L, C S Loop ilter large cap, and loop ilter small cap respectively Hs closed loop transer unction Gs open loop transer unction Es error transer unction N KVCOIC ω n CL + CS re pd KVCOIC ω n CL + CS re pd KVCOIC ω n CL + CS G s H s 1+ G s 1 E s 1+ G s Minimize Minimize I chp Minimize pd Minimize,, N Maximize pd Maximize I chp Minimize C Maximize K Maximize pd Maximize C Minimize K Depends on component noise igures. Use loop bandwidth to suppress reerence noise and VCO noise. Optimizing the Illustrative Example Finally let s apply this general discussion on optimization to the list o LL conigurations that we ound in the above example. ower I low power consumption is the primary design concern we want to minimize VCO requency and divide values. Selecting N3, 21, 220 would be the best choice. This operates the VCO at one o the lower requencies, lower and values, and has a reasonable FD requency. Startup / Settling Time I startup / settling time is the primary concern, then rom table 1 it is clear that the N7, 9, 220 is the most desirable. It has an FD o more than two times any other coniguration, resulting in a higher reresh rate on the loop ilter voltage. Jitter I low jitter is the primary concern, then N7, 9, 220 is again the most desirable. It has an FD o more than two times any other coniguration, resulting in a higher reresh rate on the loop ilter voltage and the lowest jitter o all the Understanding Frequency Synthesis age 7 o 8

8 possible conigurations. hase Noise Optimizing phase noise is highly application dependent and depends on speciic reerence oscillator and VCO noise perormance. The one design choice we can make based on our coniguration list is to choose a high VCO requency that is divided down. N7, 9, 220 is probably the best because its FD requency is so much higher than N8, 63, I the loop has high jitter, then the phase noise loor will rise signiicantly, swamping any improvement the put divider is giving us. Conclusion Coniguring a LL or system applications can be an arduous task with lots o iteration. By irst solving or all requency synthesis parameters that meet our needs, we can then make well ounded design choices that maximize lexibility and minimize cost. Cypress Semiconductor 198 Champion Court San Jose, CA hone: Fax: Cypress Semiconductor Corporation, The inormation contained herein is subject to change with notice. Cypress Semiconductor Corporation assumes no responsibility or the use o any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used or medical, lie support, lie saving, critical control or saety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products or use as critical components in lie-support systems where a malunction or ailure may reasonably be expected to result in signiicant injury to the user. The inclusion o Cypress products in lie-support systems application implies that the manuacturer assumes all risk o such use and in doing so indemniies Cypress against all charges. SoC Designer, rogrammable System-on-Chip, and SoC Express are trademarks and SoC is a registered trademark o Cypress Semiconductor Corp. All other trademarks or registered trademarks reerenced herein are property o the respective corporations. This Source Code sotware and/or irmware is owned by Cypress Semiconductor Corporation Cypress and is protected by and subject to worldwide patent protection United States and oreign, United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transerable license to copy, use, modiy, create derivative works o, and compile the Cypress Source Code and derivative works or the sole purpose o creating custom sotware and or irmware in support o licensee product to be used only in conjunction with a Cypress integrated circuit as speciied in the applicable agreement. Any reproduction, modiication, translation, compilation, or representation o this Source Code except as speciied above is prohibited with the express written permission o Cypress. Disclaimer: CYRESS MAKES NO WARRANTY OF ANY KIND, EXRESS OR IMLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A ARTICULAR UROSE. Cypress reserves the right to make changes with urther notice to the materials described herein. Cypress does not assume any liability arising o the application or use o any product or circuit described herein. Cypress does not authorize its products or use as critical components in lie-support systems where a malunction or ailure may reasonably be expected to result in signiicant injury to the user. The inclusion o Cypress product in a lie-support systems application implies that the manuacturer assumes all risk o such use and in doing so indemniies Cypress against all charges. Use may be limited by and subject to the applicable Cypress sotware license agreement. Understanding Frequency Synthesis age 8 o 8