Ultraprecision Operational Amplifier OP177

Transcription

1 a FEATURES Ultralow Offset Voltage: T A = +25 C: 10 V max 55 C T A +125 C: 20 V max Outstanding Offset Voltage Drift: 0.1 V/ C max Excellent Open-Loop Gain and Gain Linearity: 12 V/ V typ CMRR: 130 db min PSRR: 120 db min Low Supply Current: 2.0 ma max Fits Industry Standard Precision Op Amp Sockets (OP07/OP77) Epoxy Mini-DIP (P Suffix) 8-Pin Hermetic DIP (Z-Suffix) 8-Pin SO (S-Suffix) Ultraprecision Operational Amplifier OP177 PIN CONNECTIONS OP177BRC/883 LCC (RC Suffix) NC = NO CONNECT NC = NO CONNECT GENERAL DESCRIPTION The OP177 features the highest precision performance of any op amp currently available. Offset voltage of the OP177 is only 10 µv max at room temperature and 20 µv max over the full military temperature range of 55 C to +125 C. The ultralow V OS of the OP177, combines with its exceptional offset voltage drift (TCV OS ) of 0.1 µv/ C max, to eliminate the need for external V OS adjustment and increases system accuracy over temperature. The OP177 s open-loop gain of 12 V/µV is maintained over the full ±10 V output range. CMRR of 130 db min, PSRR of 120 db min, and maximum supply current of 2 ma are just a few examples of the excellent performance of this operational amplifier. The OP177 s combination of outstanding specifications insure accurate performance in high closed-loop gain applications. This low noise bipolar input op amp is also a cost effective alternative to chopper-stabilized amplifiers. The OP177 provides chopper-type performance without the usual problems of high noise, low frequency chopper spikes, large physical size, limited common-mode input voltage range, and bulky external storage capacitors. The OP177 is offered in both the 55 C to +125 C military, and the 40 C to +85 C extended industrial temperature ranges. This product is available in 8-pin ceramic and epoxy DIPs, as well as the space saving 8-pin Small-Outline (SO) and the Leadless Chip Carrier (LCC) packages. REV. B Figure 1. Simplified Schematic Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Analog Devices, Inc., 1995 One Technology Way, P.O. Box 9106, Norwood, MA , U.S.A. Tel: 617/ Fax: 617/

2 OP177 SPECIFICATIONS ELECTRICAL CHARACTERISTICS V S = 15 V, T A = +25 C, unless otherwise noted) OP177A OP177B Parameter Symbol Conditions Min Typ Max Min Typ Max Units Input Offset Voltage V OS µv Long-Term Input Offset Voltage Stability V OS /Time (Note 1) µv/mo Input Offset Current I OS na Input Bias Current I B na Input Noise Voltage e n f o = 1 Hz to 100 Hz nv rms Input Noise Current i n f o = 1 Hz to 100 Hz pa rms Input Resistance Differential-Mode R IN (Note 3) MΩ Input Resistance Common-Mode R INCM GΩ Input Voltage Range IVR (Note 4) ± 13 ±14 ±13 ±14 V Common-Mode Rejection Ratio CMRR V CM = ±13 V db Power Supply Rejection Ratio PSRR V S = ±3 V to ± 18 V db Large Signal Voltage Gain A VO R L 2 kω, V O = ±10 V V/mV Output Voltage Swing V O R L 10 kω ±13.5 ±14.0 ±13.5 ±14.0 V R L 2 kω ±12.5 ±13.0 ±12.5 ±13.0 V R L 1 kω ±12.0 ±12.5 ±12.0 ±12.5 V Slew Rate SR R L 2 kω V/µs Closed-Loop Bandwidth BW A VCL = MHz Open-Loop Output Resistance R O Ω Power Consumption P D V S = ±15 V, No Load mw V S = ±3 V, No Load mw Supply Current I SY V S = ±15 V, No Load ma Offset Adjustment Range Rp = 20 kω ±3 ±3 mv NOTES 1 Long-Term Input Offset Voltage Stability refers to the averaged trend line of V OS vs. Time over extended periods after the first 30 days of operation. Excluding the initial hour of operation, changes in V OS during the first 30 operating days are typically less than 2.0 µv. 2 Sample tested. 3 Guaranteed by design. 4 Guaranteed by CMRR test condition. 5 To insure high open-loop gain throughout the ±10 V output range, A VO is tested at 10 V V O 0 V, 0 V V O +10 V, and 10 V V O +10 V. Specifications subject to change without notice. ELECTRICAL CHARACTERISTICS OP177A OP177B Parameter Symbol Conditions Min Typ Max Min Typ Max Units Input Offset Voltage V OS µv Average Input Offset Voltage Drift TCV OS (Note 1) µv/ C Input Offset Current I OS na Average Input Offset Current Drift TCI OS (Note 2) pa/ C Input Bias Current I B na Average Input Bias Current Drift TCI B (Note 2) pa/ C Input Voltage Range IVR (Note 3) ± 13 ±13.5 ±13 ±13.5 V Common-Mode Rejection Ratio CMRR V CM = ±13 V db Power Supply Rejection Ratio PSRR V S = ±3 V to ± 18 V db Large-Signal Voltage Gain A VO R L 2 kω, V O = ±10 V V/mV Output Voltage Swing V O R L 2 kω ±12 ±13.0 ±12 ±13.0 V Power Consumption P D V S = ±15 V, No Load mw Supply Current I SY V S = ±15 V, No Load ma NOTES 1 TCV OS is 100% tested. 2 Guaranteed by endpoint limits. 3 Guaranteed by CMRR test condition. 4 To insure high open-loop gain throughout the ± 10 V output range, A VO is tested at 10 V V O 0 V, 0 V V O +10 V, and 10 V V O +10 V. Specifications subject to change without notice. (@ V S = 15 V, 55 C T A +125 C, unless otherwise noted) 2 REV. B

3 ELECTRICAL CHARACTERISTICS V S = 15 V, T A = +25 C, unless otherwise noted) OP177 OP177E OP177F OP177G Parameter Symbol Conditions Min Typ Max Min Typ Max Min Typ Max Units Input Offset Voltage V OS µv Long-Term Input Offset Voltage Stability V OS /Time (Note 1) µv/mo Input Offset Current I OS na Input Bias Current I B na Input Noise Voltage e n f o = 1 Hz to 100 Hz nv rms Input Noise Current i n f o = 1 Hz to 100 Hz pa rms Input Resistance Differential-Mode R IN (Note 3) MΩ Input Resistance Common-Mode R INCM GΩ Input Voltage Range IVR (Note 4) ±13 ±14 ± 13 ± 14 ± 13 ± 14 V Common-Mode Rejection Ratio CMRR V CM = ±13 V db Power Supply Rejection Ratio PSRR V S = ±3 V to ±18 V db Large Signal R L 2 kω, Voltage Gain A VO V O = ±10 V V/mV Output Voltage Swing V O R L 10 kω ±13.5 ±14.0 ± 13.5 ± 14.0 ± 13.5 ± 14.0 V R L 2 kω ±12.5 ±13.0 ± 12.5 ± 13.0 ± 12.5 ± 13.0 V R L 1 kω ±12.0 ±12.5 ± 12.0 ± 12.5 ± 12.0 ± 12.5 V Slew Rate SR R L 2 kω V/µs Closed-Loop Bandwidth BW A VCL = MHz Open-Loop Output Resistance R O Ω Power Consumption P D V S = ±15 V, No Load mw V S = ±3 V, No Load mw Supply Current I SY V S = ±15 V, No Load ma Offset Adjustment Range R P = 20 kω ±3 ±3 ±3 mv NOTES 1 Long-Term Input Offset Voltage Stability refers to the averaged trend line of V OS vs. time over extended periods after the first 30 days of operation. Excluding the initial hour of operation, changes in V OS during the first 30 operating days are typically less than 2.0 µv. 2 Sample tested. 3 Guaranteed by design. 4 Guaranteed by CMRR test condition. 5 To insure high open-loop gain throughout the ±10 V output range, A VO is tested at 10 V V O 0 V, 0 V V O +10 V, and 10 V V O +10 V. Specifications subject to change without notice. REV. B 3

4 OP177 SPECIFICATIONS ELECTRICAL CHARACTERISTICS OP177E OP177F OP177G Parameter Symbol Conditions Min Typ Max Min Typ Max Min Typ Max Units Input Offset Voltage V OS µv Average Input Offset Voltage Drift TCV OS (Note 1) µv/ C Input Offset Current I OS na Average Input Offset Current Drift TCI OS (Note 2) pa/ C Input Bias Current I B ±6.0 na Average Input Bias Current Drift TCI B (Note 2) pa/ C Input Voltage Range IVR (Note 3) ±13 ±13.5 ±13 ±13.5 ±13.0 ±13.5 V Common-Mode Rejection Ratio CMRR V CM = ±13 V db Power Supply Rejection Ratio PSRR V S = ±3 V to ±18 V db Large-Signal Voltage Gain A VO R L 2 kω, V O = ±10 V V/mV Output Voltage Swing V O R L 2 kω ±12 ±13.0 ±12 ±13.0 ±12.0 ±13.0 V Power Consumption P D V S = ±15 V, No Load mw Supply Current I SY V S = ±15 V, No Load ma NOTES 1 OP177E: TCV OS is 100% tested. 2 Guaranteed by endpoint limits. 3 Guaranteed by CMRR test condition. 4 To insure high open-loop gain throughout the ± 10 V output range, A VO is tested at 10 V V O 0 V, 0 V V O +10 V, and 10 V V O +10 V. Specifications subject to change without notice. (@ V S = 15 V, 40 C T A +85 C, unless otherwise noted) Figure 2. Typical Offset Voltage Test Circuit Figure 3. Optional Offset Nulling Circuit 4 REV. B

5 OP177 Figure 4. Burn-In Circuit ABSOLUTE MAXIMUM RATINGS Supply Voltage ±22 V Internal Power Dissipation mw Differential Input Voltage ±30 V Input Voltage ±22 V Output Short-Circuit Duration Indefinite Storage Temperature Range Z and RC Packages C to +150 C S, P Package C to +125 C Operating Temperature Range OP177A, OP177B C to +125 C OP177E, OP177F, OP177G C to +85 C Lead Temperature Range (Soldering, 60 sec) C DICE Junction Temperature (T J ) C to +150 C Package Type JA 2 JC Units 8-Pin Hermetic DIP (Z) C/W 8-Pin Plastic DIP (P) C/W 20-Contact LCC (RC) C/W 8-Pin SO (S) C/W ORDERING GUIDE Temperature Package Package Model Range Description Option OP177AZ 55 C to +125 C 8-Pin Cerdip Q-8 OP177BZ 55 C to +125 C 8-Pin Cerdip Q-8 OP177EZ 40 C to +85 C 8-Pin Cerdip Q-8 OP177FZ 40 C to +85 C 8-Pin Cerdip Q-8 OP177GZ 40 C to +85 C 8-Pin Cerdip Q-8 OP177FP 40 C to +85 C 8-Pin Plastic DIP N-8 OP177GP 40 C to +85 C 8-Pin Plastic DIP N-8 OP177BRC/ C to +125 C 20-Pin LCC E-20A OP177FS 40 C to +85 C 8-Pin SO SO-8 OP177GS 40 C to +85 C 8-Pin SO SO-8 NOTES 1 For supply voltages less than ± 22 V, the absolute maximum input voltage is equal to the supply voltage. 2 θ JA is specified for worst case mounting conditions, i.e., θ JA is specified for device in socket for cerdip, P-DIP, and LCC packages; θ JA is specified for device soldered to printed circuit board for SO package. REV. B 5

6 OP177 Typical Performance Characteristics Figure 5. Gain Linearity (Input Voltage vs. Output Voltage) Figure 6. Power Consumption vs. Power Supply Figure 7. Warm-Up V OS Drift (Normalized) Z Package Figure 8. Offset Voltage Change Due to Thermal Shock Figure 9. Open-Loop Gain vs. Temperature Figure 10. Open-Loop Gain vs. Power Supply Voltage Figure 11. Input Bias Current vs. Temperature Figure 12. Input Offset Current vs. Temperature Figure 13. Closed-Loop Response for Various Gain Configurations

7 OP177 Figure 14. Open-Loop Frequency Response Figure 15. CMRR vs. Frequency Figure 16. PSRR vs. Frequency Figure 17. Total Input Noise Voltage vs. Frequency Figure 18. Input Wideband Noise vs. Bandwidth (0.1 Hz to Frequency Indicated) Figure 19. Maximum Output Swing vs. Frequency Figure 20. Maximum Output Voltage vs. Load Resistance Figure 21. Output Short Circuit Current vs. Time REV. B 7

8 OP177 APPLICATIONS INFORMATION Gain Linearity The actual open-loop gain of most monolithic op amps varies at different output voltages. This nonlinearity causes errors in high closed-loop gain circuits. It is important to know that the manufacturer s A VO specification is only a part of the solution, since all automated testers use endpoint testing and, therefore, only show the average gain. For example, Figure 22 shows a typical precision op amp with a respectable open-loop gain of 650 V/mV. However, the gain is not constant through the output voltage range, causing nonlinear errors. An ideal op amp would show a horizontal scope trace. THERMOCOUPLE AMPLIFIER WITH COLD-JUNCTION COMPENSATION An example of a precision circuit is a thermocouple amplifier that must amplify very low level signals accurately without introducing linearity and offset errors to the circuit. In this circuit, an S-type thermocouple, which has a Seebeck coefficient of 10.3 µv/ C, produces 10.3 mv of output voltage at a temperature of 1,000 C. The amplifier gain is set at Thus, it will produce an output voltage of V. Extended temperature ranges to beyond 1,500 C can be accomplished by reducing the amplifier gain. The circuit uses a low-cost diode to sense the temperature at the terminating junctions and in turn compensates for any ambient temperature change. The OP177, with its high open-loop gain, plus low offset voltage and drift combines to yield a very precision temperature sensing circuit. Circuit values for other thermocouple types are shown in Table I. Table I. Thermo- Seebeck couple Type Coefficient R1 R2 R7 R9 Figure 22. Typical Precision Op Amp K 39.2 µv/ C 110 Ω 5.76 kω 102 kω 269 kω J 50.2 µv/ C 100 Ω 4.02 kω 80.6 kω 200 kω S 10.3 µv/ C 100 Ω 20.5 kω 392 kω 1.07 MΩ Figure 23. OP177 s Output Gain Linearity Trace Figure 25. Thermocouple Amplifier with Cold Junction Compensation Figure 24. Open-Loop Gain Linearity Test Circuit Figure 23 shows the OP177 s output gain linearity trace with its truly impressive average A VO of V/mV. The output trace is virtually horizontal at all points, assuring extremely high gain accuracy. PMI also performs additional testing to insure consistent high open-loop gain at various output voltages. Figure 24 is a simple open-loop gain test circuit for your own evaluation. PRECISION HIGH GAIN DIFFERENTIAL AMPLIFIER The high gain, gain linearity, CMRR, and low TCV OS of the OP177 make it possible to obtain performance not previously available in single stage, very high-gain amplifier applications. See Figure 26. For best CMR, R1 R3 must equal. In this example, with a R2 R4 10 mv differential signal, the maximum errors are as listed in Table II.

9 OP177 ISOLATING LARGE CAPACITIVE LOADS The circuit in Figure 27 reduces maximum slew-rate but allows driving capacitive loads of any size without instability. Because the 100 Ω resistor is inside the feedback loop, its effect on output impedance is reduced to insignificance by the high openloop gain of the OP177. Figure 26. Precision High Gain Differential Amplifier Table II. High Gain Differential Amp Performance Type Amount Common-Mode Voltage 0.1%/V Gain Linearity, Worst Case 0.02% TCV OS %/ C TCI OS 0.008%/ C Figure 27. Isolating Capacitive Loads Figure 28. Bilateral Current Source Figure 29. Precision Absolute Value Amplifier

10 OP177 BILATERAL CURRENT SOURCE The current sources shown in Figure 28 will supply both positive and negative current into a grounded load. R4 R5 Note that Z = R2 +1 O R5+ R4 R3 R2 R1 and that for Z O to be infinite, PRECISION ABSOLUTE VALUE AMPLIFIER The high gain and low TCV OS assure accurate operation with inputs from microvolts to volts. In this circuit, the signal always appears as a common-mode signal to the op amps. The OP177E CMRR of 140 db assures errors of less than 1 ppm. See Figure 29. R5+ R4 R2 must = R3 R1 Figure 30. Precision Positive Peak Detector PRECISION POSITIVE PEAK DETECTOR In Figure 30, the C H must be of polystyrene, Teflon*, or polyethylene to minimize dielectric absorption and leakage. The droop rate is determined by the size of C H and the bias current of the OP41. PRECISION THRESHOLD DETECTOR/AMPLIFIER In Figure 32, when V IN < V TH, amplifier output swings negative, reverse biasing diode D 1. V OUT = V TH if R L =. When V IN V TH, the loop closes, ( ) 1+ R F V OUT =V TH + V IN V TH R S C C is selected to smooth the response of the loop. *Teflon is a registered trademark of the Dupont Company. Figure 31. Precision Threshold Detector/Amplifier 10 REV. B

11 OP177 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 8-Pin Cerdip (Q-8) 8-Pin SO (SO-08) (0.13) MIN (1.4) MAX PIN (7.87) (5.59) PIN (4.00) (3.80) (6.20) (5.80) (5.08) MAX (5.08) (3.18) (0.58) (0.36) (10.29) MAX (2.54) BSC (1.78) (0.76) (1.52) (0.38) (3.81) MIN SEATING PLANE (8.13) (7.37) (0.38) (0.20) (0.25) (0.10) (5.00) (4.80) (1.27) BSC (0.49) (0.35) (1.75) (1.35) (0.25) (0.19) (0.50) (0.25) x (1.27) (0.41) 8-Pin Plastic DIP (N-8) 20-Pin LCC (E-20A) PIN (5.33) MAX (4.06) (2.93) (10.92) (8.84) (7.11) (6.10) (1.52) (0.38) (3.30) MIN (8.25) (7.62) (0.381) (0.204) (4.95) (2.93) (9.09) (8.69) SQ TOP VIEW (2.54) (1.63) (9.09) MAX SQ (2.24) (1.37) (2.41) (1.90) (0.28) (0.18) R TYP (1.91) REF (5.08) BSC (1.91) REF (1.40) (1.14) BOTTOM VIEW (3.81) BSC (2.54) BSC (0.38) MIN (0.71) (0.56) (1.27) BSC 45 TYP (0.558) (0.356) (2.54) BSC (1.77) (1.15) SEATING PLANE REV. B 11

12 PRINTED IN U.S.A. C /95 12