Poster Paper Proc. of Int. Conf. on Advances in Electrical & Electronics 2011

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1 A Comparative Exploration of Architecture of Single Data Rate and Double Data Rate SDRAM for an Efficient Implementation Dr. Anu Gupta 1, Vaibhav Gogte 2, Gaurav Jain 2, Shivani Bathla 3 1 Associate Professor, Electrical and Electronics Engineering Group, BITS-Pilani anug@bits-pilani.ac.in 2 B.E.(Hons.) Electrical and Electronics Engineering, BITS-Pilani {vaibhavgog@gmail.com, gaurav133jain@gmail.com} 3 B.E.(Hons.) Electronics and Instrumentation Engineering, BITS-Pilani {shivani1401@gmail.com} Abstract Strong PC and server demands for increased memory bandwidth have forced leading semiconductor makers worldwide to develop high-performance dynamic random access memory (DRAM) chip technologies. Double Data Rate (DDR) SDRAMs have been prevalent in the PC memory market in recent years because of their performance advantage for all memory systems. These advantages are based on a synchronous I/O interface and dual edge clock based data bus with improved internal architecture that enables faster data throughput rates. The overview and comparison of various SDRAM memory interfaces have been discussed in this paper. This paper presents the detailed architecture of various SDRAMs and explains the increase in the throughput rate along with the technological advancements in the memory design. Keywords VLSI, SDRAM, SDR, DDR 1, DDR2, DDR3 DOI: 03.EES I. INTRODUCTION A computer s memory is a temporary storage area for data that need to be available for programs to run efficiently. The speed of system memory is a major determining factor for computing performance. The faster the memory can provide data, the more work the processor can perform. Increased data throughput translates directly into better system performance. The most common form of memory installed today is Synchronous Dynamic Random Access Memory (SDRAM). SDRAM is DRAM that has a synchronous interface; it waits for a clock signal before responding to control inputs. The clock is used to drive an internal finite state machine that pipelines incoming instructions. This allows the chip to have a more complex pattern of operation than an asynchronous DRAM, which does not have a synchronized interface. SDRAM has passed through various generations, starting from original SDR SDRAM to DDR1, DDR2, DDR3 and DDR4 expected to be released in As the bandwidth requirement increases, Double Data Rate (DDR) interface is becoming very commonly used in many types of memories, such as, DDR I/II/III DRAM, RLDRAM I/II, QDR 1/11/II+ SRAM etc. SDRAM started with a memory speed of 66 MHz (PC66) has progressed to 100MHz 179 (PC100) and then to 133MHz (PC133). These memory devices are rapidly developing, with high density, high memory bandwidth and low device cost. Design and manufacturing breakthroughs in accurate signal management and Electromagnetic Interference (EMI) control mechanisms are compulsory on the motherboard and memory module. Hence, memory improvement is not solely a matter of consideration for DRAM designers, but a coordinated industry wide effort from the CPU architects, chipset and DRAM designers to the motherboard and memory module manufacturers. This paper presents for the first time, the detailed architecture of various SDRAMs down to the MOSFET level and explains how a memory operates in a system and compares their operational efficiency. II. SDR SDRAM Simply known as SDRAM, single data rate SDRAM can accept one command and transfer one word of data per clock cycle. The SDR memory data interface is a fully synchronous design where the data is only captured on the positive clock edge. The internal bus is the same width as the external data bus and data latches into the internal memory array sequentially as it passes through the I/O buffers. This section explains the detailed architecture of a 16*16 SDR SDRAM. As can be seen from the figure1, SDR SDRAM consists of a data control circuitry, CLK, 5-address input bus, 8-input data bus and a matrix of 16*16 DRAM cells (32B memory). A. Data Control Circuitry Fig.1 Block Diagram of SDR This block of the architecture is responsible for decoding the address signals and mapping them onto a particular

2 DRAM cell on which the operation (either read or write) is to be performed. It consists of two registers namely Data Register and Address Register which are use for latching the data and address. In this block, RS, WS, Data and Address signals are all initially latched at the positive edge of clock cycle. With the help of row and column decoders, address is decoded so that it can be mapped to a particular DRAM cell from a pool of 16*16 cells. The internal bus is the same width as the external data bus and data latches into the internal memory array sequentially as it passes through the I/O buffers. Fig.2 SDR SDRAM III. DDR1 SDRAM Double data rate memory provides source-synchronous data capture at a rate of twice the clock frequency. Therefore, a DDR266 device with a clock frequency of 133 MHz has a peak data transfer rate of 266 Mb/s. This is accomplished by utilizing a 2n-prefetch architecture where the internal data bus is twice the width of the external data bus and data capture occurs twice per clock cycle. In addition, some minor changes to the SDR interface timing are made in hindsight, and the supply voltage is reduced from 3.3 to 2.5 V. As a result, DDR SDRAM is not backwards compatible with SDR SDRAM. The DDR memory data is a true source-synchronous design, where the data is captured twice per clock cycle with a bidirectional data strobe. This architecture employs a 2nprefetch architecture, where the internal data bus is twice the width of the external bus. The DDR command bus consists of a clock enable, row and column addresses and a write enable. The DDR memory utilizes a differential pair for the system clock and therefore will have both a true clock (CLK) and complementary clock (CLK#) signal. Commands are enabled on the positive edges of clock, while data occurs on both positive and negative edges of the clock. A. Data Strobe Signal Fig.4 CLK and PC Since DDR SDRAM performs data input/output at twice the frequency of the external clock, the valid data window is narrower than for SDR SDRAM. If the wiring length between the memory and the controller is different, the time required for data to reach the receiver is different. DDR SDRAM employs a data strobe signal (DQS) to notify the receiver of the data transfer timing. DQS is a bidirectional strobe signal and functions as the basic operating clock for DQ during read/write operations. In the read cycle, DDR SDRAM drives the data strobe signal (DQS), which is in synchronization with the clock (CLK). The receiver captures the data (DQ) using DQS as a timing reference. The operation of DQS in the read and write cycle is as shown in the fig. Fig.5 Data Strobe Signal in READ Cycle Fig.6 Data Strobe Signal in WRITE Cycle B. Data Control Circuitry Data control circuitry and memory array blocks in DDR1 are almost same as compared to SDR the only difference being the voltage levels on which they work and the size of memory array (128B). Fig.3 Block Diagram of DDR1 C. Write Prefetch Two sets of n-bit data is latched in two registers, one at the positive edge and the other at the negative edge of the DQS signal given using positive and negative edge triggered DFF respectively as shown in Figure 7. The data is latched into a 2n-bit register and is further sent to the DRAM cell 180

3 array in the next clock edge. The 2-n bits data is then made available to the pool of memory cells where it is written on specific block as selected by data control circuitry. D. Read Prefetch Fig.7 Simplified Diagram of 2n-Prefetch Write 2n-bit of data read from the output of memory cells is made available to read prefetch. Similar to write prefetch, data is transferred to the output pins at both edges of clock using positive and negative edge triggered DFF. The 2n-bit data is divided into two sets of n-bits each and is further sent to a multiplexer having least significant bit of address as the select line. As data is read from consecutive memory locations, output is from even bank in first half cycle (when address LSB is 0) and from odd bank in next half cycle (when address LSB is 1). DQS signal indicates the validity of data at output. IV. DDR2 SDRAM DDR2 SDRAM functions much like DDR SDRAM a source-synchronous data strobe is used and data is transferred on both the leading and trailing clock edges. However, DDR2 SDRAM has a 4n-prefetch architecture where the internal data cycle time is one-fourth of the external clock rate and the internal data bus width is four times the size of the external data bus width. A. Write Prefetch Two clocks both having half the frequency of the external high frequency clock are generated. As indicated in Fig 10, one clock is in phase with external clock while other leads the previous clock by bytes of data are multiplexed using the two clock signals as shown in the figure thus accepting it at every edge of external clock cycle. Speed in DDR2 is thus doubled. Fig.10 CLK, CLK by 2 and Shifted CLK by 2 Internal clock and the phase shifted clock acts as the two select lines of 1:4 demux which demultiplexes 4-bytes of data in two cycles of external high speed clock. Data is accepted serially and then sent to the DRAM cell array after latching it at positive edge of INT_CLK. Fig.8 Simplified Diagram of 2n-Prefetch Read B. Read Prefetch Fig.11 Write Prefetch of DDR2 SDRAM Data is multiplexed to output by similar method as used in write prefetch. A set of registers accepts 4-bytes of data parallel. This data is then multiplexed using the same set of clock signals as in write prefetch circuit. Fig.9 DDR1 Memory 181

4 VI. SIMULATION RESULTS Fig.12 Read Prefetch of DDR2 SDRAM V. DDR3 SDRAM DDR3 s 8-burst prefetch buffer doubles the data rate provided by DDR2. To accomplish this doubling of data rate, the read and write prefetch circuitry are modified. Two clocks are generated using external clock one halving half the frequency of the external and the other having one-fourth the frequency of the external. A. Data Control Circuitry This block is same in logic as that of DDR2. B. Write Prefetch 8 bytes of data are multiplexed using the three signals: the clock signal, clock signal divided by 2 and the clock signal divided by 4. Simulations have been performed on each of the memory circuits and results have been obtained as shown below. The internal frequency of 0.5 MHz on which all the memories work is kept same for comparison. A. DDR1 SDRAM The circuit has been simulated at 0.5 MHz clock frequency as shown in the fig Data input is 0 which is written on memory cell at 4us as indicated by WS signal. The same data is read using RS signal at 6us. Data Out, which was 1 initially due to precharge, falls to 0. Thus 2 bytes of data are read/ written in a period of 2us. Fig.15.1 CLK Fig.15.2 WS Fig.13 CLK, CLK by 2 and CLK by 4 When [s2 s1 s0] form combination [1 1 1] data0 is latched, next combination [1 1 0] corresponds to data1 and hence forth. Hence, for each combination of [s2 s1 s0] the data is latched in the 8 registers which are then given to the memory array. C. Read Prefetch The combinations formed by [s2 s1 s0 ] form the order [111], [110], [101], [100], [011], [010], [001], [000] at which the circuitry gives data0, data1, data2, data3, data4, data5, data6 and data7 respectively. Fig.15.3 RS Fig.14 Read Prefetch of DDR3 182 B. DDR2 SDRAM Fig.15.4 Final Data Out The circuit has been simulated at 1 MHz clock frequency. The clocks of frequency half of the external input frequency i.e. 0.5 MHz are generated. Data input is 0 which is written on memory cell at 2 us as indicated by WS signal in Fig The same data is read using RS signal at 4 us in fig Data-out which was initially 1 due to precharge falls to 0 Four data

5 bytes are written/read in DDR2 in a period of 2us as compared to two bytes in DDR1 in the same time. Fig.17.2 CLK by 2 Fig.16.1 CLK Fig.17.3 CLK by 4 Fig.16.2 WS Fig.16.3 RS Fig.17.4 PC C. DDR3 SDRAM Fig.16.4 Data Out of DRAM Cell The circuit has been simulated at 2 MHz clock frequency. The clocks of frequency half and one-fourth of the external input frequency are generated as in fig 17.2 and 17.3 i.e. 1 MHz and 0.5 MHz respectively. Data input is 0 which is written on memory cell 2us by WS signal. The same data is read using RS signal at 4us. Data Out which was 1 initially due to precharge falls to 0. Eight data bytes are transferred in DDR3 in a period of 2us as compared to two bytes in DDR1 and four bytes in DDR2 in same time. Fig.17.1 CLK Fig.17.5 Final Data Out VII. CONCLUSIONS The architectures of all the SDRAMs were designed using EDA (Cadence) Tools and the simulation results were compared. It is observed from the various architectures that the complexity of design and number of components used increases generation by generation. SDR doesn t include any prefetch circuitry and it accepts data only at the positive edge of the clock. Whereas prefetch circuits used in DDR generations enables them to use both the edges of the clock for read/write operation on the memory array, thus making them more efficient and faster in terms of data retrieval. Prefetch circuitry is the most important block of DDR generation since any changes in its architecture greatly affects the speed and performance of the memory. It can be seen from the simulation results obtained that speed gets doubled every generation. Though, the external clock frequency gets doubled every generation, the internal blocks of all the SDRAM work at the same frequency (Table I). The 183

6 main trade-off with DDR generations as compared to SDR is mainly the increase in the hardware used and increase in power dissipation. TABLE I FEATURE COMPARISON OF VARIOUS MEMORIES ACKNOWLEDGMENT We are very grateful to BITS, Pilani for providing us with the labs and facilities to work on this project without which this work wouldn t have been of any value. REFERENCES [1] 256Mb Double data rate memory Features, Micron Technology Inc., Boise, Idaho, USA, [2] 512Mb Double data rate memory Features, Micron Technology Inc., Boise, Idaho, USA, [3] General DDR SDRAM Functionality, Micron Technology, Boise, Idaho, USA, [4] DDR2 Offers New Features and Functionality, Micron Technology, Boise, Idaho, USA, [5] Design Guide for two DDR UDIMM Systems, Micron Technology, Boise, Idaho, USA, [6] 2GB (X64,DR) 204-Pin DDR3 SDRAM SODIMM Features, Micron Technology, Boise, Idaho, USA, 2008 [7] Implementing double data rate I/O signalling in cyclone devices, Altera Corporation, San Jose, California, U.S., May 2008 [8] DDR and DDR2 SDRAM Controller Compiler User Guide, Altera Technology, San Jose, California, U.S., March [9] DDR2 SDRAM Technology, Elpida Memory, Japan, Aug [10] How to use DDR SDRAM, Elpida Memory, Japan, April 2002 [11] New Features of DDR3 SDRAM, Elpida Memory, Japan, March [12] 2GB Unbuffered DDR3 SDRAM DIMM, Elpida Memory, Japan, December [13] Mohammad Tisani, How to Debug and Design DDR Module, Pericom Semiconductor Corporation, San Jose, California, Aug 2003 [14] HYB25D256[800/160]B T(L)-[5/5A] 256 MBit Double Data Rate SDRAM, Infineon Technologies, Neubiberg, Germany, Jan [15] Chen Shuang-yan, Wang Dong-hui, Shan Rui and Hou Chaohuan, An Innovative Design of the DDR/DDR2 SDRAM Compatible Controller, in Sixth International Conference on ASIC Proceedings, 2005, pp [16] World DRAM market overview, VIA Technology Forum, VTF [17] Adrian B. Cosoroaba, Double Data Rate Synchronous Dram s in High Performance Applications, in Wescon Conference Proceedings, 1997, pp [18] Sung-Mo Kang and Yusuf Leblebici, Semiconductor Memories in CMOS Digital Integrated Circuits: Analysis and Design, 3rd edition, New Delhi: Tata Mc-Graw Hills, [19] Jan Rabaey and Anantha Chandrakasan, Designing Memory and Array Structures in Digital Integrated Circuits, 2 nd Edition, New Delhi: Prentice-Hall, [20] Designing high- density DDR2 Memory, Micron Technology, Boise, Idaho, USA, [21] DDR2 (Point-to-Point) Features and Functionality, Micron Technology, Boise, Idaho, USA,