Introduction to Embedded System Design using Zynq

Transcription

1 Introduction to Embedded System Design using Zynq Zynq 14.2 Version This material exempt per Department of Commerce license exception TSU

2 Objectives After completing this module, you will be able to: Define a Zynq All Programmable SoC (AP SoC) processor component Enumerate the key aspects of the Zynq AP SoC processing system Describe the embedded design flow Explain the purpose of the MHS file Recognize the use of the System Assembly view in XPS Indicate how the hardware design is linked to the software development environment EDK Overview 11-2

3 Outline Embedded Processor Component Overview of EDK Embedded System Development Flow XPS Hardware Platform SDK Software Platform Summary EDK Overview 11-3

4 Embedded Design Architecture in Zynq Embedded design in Zynq is based on: Processor and peripherals Dual ARM Cortex -A9 processors of Zynq-7000 AP SoC AXI interconnect AXI component peripherals Reset, clocking, debug ports Software platform for processing system Standalone or other (e.g. Linux) OS C language support Processor services C drivers for hardware User application Interrupt service routines (optional) EDK Overview 11-4

5 Zynq AP SoC PS and PL Block Diagram EDK Overview 11-5

6 The PS and the PL The Zynq-7000 AP SoC architecture consists of two major sections PS: Processing system Dual ARM Cortex-A9 processor based Multiple peripherals Hard silicon core PL: Programmable logic Uses the same 7 series programmable logic Artix -based devices: Z-7010 and Z-7020 (high-range I/O banks only) Kintex -based devices: Z-7030 and Z-7045 (mix of high-range and high-performance I/O banks) EDK Overview 11-6

7 The PS and the PL FPGA Comparison Table Spartan-6 Artix-7 Kintex-7 Virtex-7 Kintex UltraScale Virtex UltraScale Logic Cells 147, , , 760 1,954,560 1,160,880 4,407,480 BlockRAM 4.8Mb 13Mb 34Mb 68Mb 76Mb 115Mb DSP Slices ,920 3,600 5,520 2,880 DSP Performance 140GMACs 930GMACs 2,845GMACs 5,335GMACs 8,180 GMACs 4,268 GMACs (symmetric FIR) Transceiver Count Transceiver Speed 3.2 Gb/s 6.6 Gb/s 12.5 Gb/s Gb/s 16.3 Gb/s Gb/s Total Transceiver Bandwidth (full duplex) Memory Interface (DDR3) PCI Express Interface Analog Mixed Signal (AMS)/XADC 50 Gb/s 211 Gb/s 800 Gb/s 2,784 Gb/s 2,086 Gb/s 5,101 Gb/s 800 1,066 1,866 1,866 2,400 2,400 x1 Gen1 x4 Gen2 x8 Gen2 x8 Gen3 x8 Gen3 x8 Gen3 - XADC XADC XADC System Monitor Configuration AES Yes Yes Yes Yes Yes Yes System Monitor I/O Pins , ,456 I/O Voltage 1.2V - 3.3V 1.2V - 3.3V 1.2V - 3.3V 1.2V - 3.3V V V Please refer to the device data sheets for the latest product information. EDK Overview 11-7

8 The PS and the PL Spartan FPGA Families Automotive-grade XA Artix-7 FPGA Automotive-grade XA Spartan-6 FPGA Automotive-grade XA Spartan-3A FPGA Automotive-grade XA Spartan-3A DSP FPGA Automotive-grade XA Spartan-3E FPGA Spartan-3 FPGA Spartan-3A FPGA Spartan-3AN FPGA Spartan-3A DSP FPGA Spartan-3E FPGA Artix and Kintex FPGA Families Defense-grade Artix-7Q FPGA Defense-grade Kintex-7Q FPGA EasyPath FPGA Families EasyPath-7 FPGA EasyPath-6 FPGA EasyPath- FPGA Virtex FPGA Families Virtex-6 FPGA Virtex-5 FPGA Virtex-4 FPGA Defense-grade Virtex-7Q FPGA Defense-grade Virtex-6Q FPGA Defense-grade Virtex-5Q FPGA Defense-grade Virtex-4Q FPGA Space-grade Virtex-5QV FPGA Space-grade Virtex-4QV FPGA EDK Overview 11-8

9 PS Components The Zynq AP SoC processing system consists of the following blocks Application processing unit (APU) I/O peripherals (IOP) Multiplexed I/O (MIO), extended multiplexed I/O (EMIO) Memory interfaces PS interconnect DMA Timers Public and private General interrupt controller (GIC) On-chip memory (OCM): ROM and RAM Debug controller: CoreSight EDK Overview 11-9

10 Zynq Architecture Built-in Peripherals Two USB 2.0 OTG/Device/Host Two Tri- Mode GigE (10/100/1000) Two SD/SDIO interfaces Memory, I/O and combo cards Two CAN 2.0Bs, SPIs, I2Cs, UARTs Four GPIO 32bit Blocks 54 available through MIO; other available through EMIO Multiplexed Input/Output (MIO) Multiplexed pinout of peripheral and static memories Extended MIO Maps PS peripheral ports to the PL EDK Overview 11-10

12 Embedded Development Kit and PlanAhead What is the Embedded Development Kit (EDK)? The Embedded Development Kit is the Xilinx tool suite for designing both hardware and software Processing system component of a larger design run The kit includes all the tools, documentation, and IP that are required for designing systems with the Zynq-7000 AP SoC hard core and/or Xilinx MicroBlaze soft core processor Xilinx Platform Studio (XPS) is the embedded hardware development environment SDK Eclipse-based software design environment Enables the integration of hardware and software components PlanAhead is the overall project manager and is used for developing non-embedded hardware and instantiating embedded systems PlanAhead flow is recommended for developing embedded system using Zynq EDK Overview 11-12

13 EDK Components Xilinx Platform Studio (XPS) Design environment for processing system Xilinx Microprocessor Project (XMP) file Microprocessor Hardware Specification (MHS) file Platform, software, and peripheral simulation ChipScope Pro logic analyzer integration Software Development Kit (SDK) Project workspace Hardware platform definition Board Support Package (BSP) Software application Software debugging EDK Overview 11-13

14 Embedded System Tools: Hardware Xilinx Platform Studio Xilinx Platform Studio (XPS) is a graphical Integrated Design Environment (IDE) that incorporates all the embedded system tools for creation of hardware and software and supports verification flow Hardware and software development tools Base System Builder (BSB) wizard and PS Configuration wizard Start MicroBlaze processor based system development with BSB Start Zynq based system development with PS Configuration Hardware netlist generation tool: PlatGen Simulation model generation tool: SimGen Create or Import Peripheral wizard Xilinx Microprocessor Debugger (XMD) Hardware debugging using ChipScope Pro analyzer cores EDK Overview 11-14

15 Embedded System Tools: Software Eclipse IDE-based Software Development Kit (SDK) Board support package creation : LibGen GNU software development tools C/C++ compiler for the MicroBlaze and ARM Cortex-A9 processors (gcc) Debugger for the MicroBlaze and ARM Cortex-A9 processors (gdb) Instruction Set Simulator (ISS) Board support packages (BSPs) Stand-alone BSP Free basic device drivers and utilities from Xilinx NOT an RTOS EDK Overview 11-15

16 XPS System Assembly View Four Tabs Zynq Configure various blocks Bus Interface Connect peripheral to bus Ports Connect peripheral specific ports Addresses View/generate addresses EDK Overview 11-16

17 XPS Zynq Device Processing System View A: Navigator B: IP Catalog C: Zynq Processing System View D: Console C B A D EDK Overview 11-17

18 XPS System Assembly View Bus Interface Tab A: Project Information Area B: Connectivity Panel C: Legend A B C EDK Overview 11-18

19 XPS System Assembly View Ports Tab Instance Name column Connected Port column Connect to another internal port Make external Predefined net_gnd, net_vcc Leave it unconnected Optionally, Net column Direction column Bus Width column EDK Overview 11-19

20 XMP File The XMP file is the project support file for XPS Takes on the name of the project: <project>.xmp In labs, we use system.xmp as a name Contains and controls Files that make up the XPS project; that is, the MHS file Tools settings GUI settings The XMP file is typically the embedded source file that contains the XPS component in Project Navigator or the PlanAhead software The file type that identifies the embedded processor component source Alternative to using system_stub.vhd/v EDK Overview 11-20

21 MHS File Hardware specification file of the processing system Main source file of the processing system Component instances are from IP Catalog Shows component instances and their connectivity Stored as a text file Named after the project, <project>.mhs Fully defines the embedded system hardware Does not include tool setting options (these are part of the XMP file) The System Assembly View is the IDE that builds the MHS file Hand editing is also allowed XPS will not open a project whose XPS file has an error Usually happens when hand editing mistakes are made and the file is saved May require fixing error in a text editor as XPS will not open a project whose MHS file has an error EDK Overview 11-21

23 Embedded System Design Flow for Zynq-7000 AP SoC EDK Overview 11-23

24 Embedded System Design using PlanAhead Create a new PlanAhead tool project, or open an existing project Add/Create a new embedded source from the PlanAhead tool environment Use(Invoke) XPS to construct(modify) the hardware portion of the embedded design [optional] Run PlatGen (Hardware > Generate Netlist) building HDL instantiation and netlist files Close XPS and return to the PlanAhead tool Create(Update) top level HDL model Synthesize any non-embedded components and implement within the PlanAhead tool Export the bitstream, processor hardware description, and launch SDK Create a new software board support package and application projects in the SDK Compile the software with the GNU cross-compiler in SDK [optional] Download the programmable logic s completed bitstream using impact Use SDK to download the program (the ELF file) EDK Overview 11-24

25 Embedded System Design using PlanAhead 1. Launch PlanAhead 3. Configure PS settings 4. Add IP (exit XPS, back to PlanAhead) XPS 2. Add Embedded Source (launch XPS) 5. Add Top-Level HDL 6. Add Constraints file 7. Generate Bitstream =>.bit 8. Export hardware to SDK 9. Specify hardware built from PlanAhead and XPS 10. Add Software Project & Build =>.elf PlanAhead SDK 11. Program bitstream &.elf into Zynq Optional step ZedBoard EDK Overview 11-25

26 Launching a New XPS Project from the PlanAhead Software (1) Launching XPS processor projects from the PlanAhead tool(recommended) Easy to integrate a processing system with other programmable logic Access to more Xilinx point tools Easy software integration To add an XPS project In the Flow Navigator, select Add Sources > Add or Create Embedded Sources > Create Subdesign Enter the module name (e.g. system) and click OK Opens XPS allowing you to add PS EDK Overview 11-26

27 Configuring Hardware in XPS (2) After the XPS tool is open Select Zynq tab and configure application specific interfaces Configure PS components if needed Optionally, use IP Catalog to add PL peripherals Run Design Run Checker (DRC) Optionally, run Hardware > Generate Netlist to verify system assembly correctness Exit XPS The processing system can be placed anywhere in the design hierarchy EDK Overview 11-27

28 Extending Hardware in the PlanAhead Software (3) Optionally, add other hdl files to the design Optionally, add user constraint files to connect non-ps pins Create a top level HDL model Optionally generate bitstream EDK Overview 11-28

29 Exporting to SDK (4) Software development is performed with the Xilinx Software Development Kit tool (SDK) Export can be done from XPS (only if or the PlanAhead software An XML description of the hardware is imported in the SDK tool The hardware platform is built on this description Only one hardware platform for an SDK project The SDK tool will then associate user software projects to hardware EDK Overview 11-29

30 Build Software Application (5) Create hardware platform Automatically performed when SDK tool is launched from the PlanAhead or XPS tools Create software platform System software, board support package LibGen program Create software application Create linker script Build project compile, assemble, link output file <app_project>.elf EDK Overview 11-30

31 Configuring FPGA and Downloading Application Download the bitstream Only if PL is used Input file <top_name>.bit The Xilinx impact tool downloads the bitstream to the target The impact tool is accessible from all tools XPS Only if the processor system is created using XPS, i.e. non-planahead flow SDK For a processor system created either using PlanAhead flow or non-planahead flow PlanAhead Requires that the download cable is connected EDK Overview 11-31

33 PS Configuration Wizard Provides a graphical view of the PS to configure ARM cores I/O peripherals DDR controller Memory systems PS CW output consists of a hardware description of the PS tightly coupled with XPS I/O partitioning between dedicated PS pins and programmable logic I/O by pin planning Zynq-7000 AP SoC PS is configured via a set of memory-mapped configuration registers EDK Overview 11-33

34 Clocking Wizard Click the Clock Generation block Clock Wizard dialog box opens Input frequency can be set All IOP clock frequencies can be set Clock to PL is disabled if PS clocking is present EDK Overview 11-34

35 Accessing Project Files The Platform tab in the Project view allows access to the files that make up the processor project Most important file is the MHS Many of the option files are only used for isolated, non-ise tool, XPS flows The Project Options show the current settings EDK Overview 11-35

36 Processing System Component Management Adding cores, editing core parameters, and making bus and port connections through the System Assembly view (SAV) 1. Select the IP Catalog tab to add peripherals Select a core, then right-click and select Add IP, or drag into SAV, or double-click it to add 2. In SAV, select an instance and right-click to view core features and parameters 3. Change the embedded system topology with SAV tabs Zynq Bus interface Ports Peripheral base addresses and size 4. Select Configure IP to configure the instance EDK Overview 11-36

37 Project Options: General Tab XPS supports project options settings via the General and Design Flow tabs Default settings are typically used Set/change target device Architecture Device size Package Speed grade Peripheral repository directory Provide path to custom IP not present in the current project directory structure EDK Overview 11-37

38 Project Options: Design Flow Tab Design Flow tab Tool options Language for component wrappers Auto testbench template generation Simulation model generation mode EDK Overview 11-38

40 Software Development Kit (SDK) Full-featured software design environment Separate tool from the PlanAhead tool, Project Navigator, and XPS Based on popular Eclipse open-source IDE Used for software applications only; hardware design and modifications are done in XPS Well-integrated environment for seamless debugging of embedded targets Sophisticated software design environment with many options and features with support for Multiple processors Multiple software platforms Multiple software applications Superior C/C++ code editor and error navigator EDK Overview 11-40

41 SDK Workbench Views 1. C/C++ project outline displays the elements of a project with file decorators (icons) for easy identification 2. C/C++ editor for integrated software creation 3. Code outline displays elements of the software file under development with file decorators (icons) for easy identification 4. Problems, Console, Properties views list output information associated with the software development flow EDK Overview 11-41

42 Software Management Settings Software is managed in three major areas Compiler/Linker Options Application program Software Platform Settings Board support package Linker Script Generation Assigning software to memory resources Covered in more detail later EDK Overview 11-42

44 Summary The Embedded Development Kit (EDK) includes all the tools, documentation, and IP necessary for building embedded systems The Software Development Kit (SDK) is a comprehensive software development environment for software applications An embedded processing system component is built with IP provided in the XPS IP Catalog. Designers can also add their own custom IP to this catalog The MHS file defines the configuration of the embedded processing system component The designer graphically builds the MHS file using the System Assembly View in XPS The PS Configuration wizard permits access to several configurable features of PS EDK Overview 11-44