COSC 6385 Computer Architecture. - Pipelining (II)

Transcription

1 COSC 6385 Computer Archtecture - Ppelnng (II) Sprng 2011 Performance evaluaton of ppelnes (I) General Speedup Formula: Tme Speedup = Tme = IC IC ClockCycle ClockClycle CPI CPI For a fxed applcaton lets assume that IC = IC ClockCycle Speedup= ClockClycle CPI CPI If we assume addtonally that the CPU has the same frequency,.e. ClockCycle = ClockCycle CPI Speedup = CPI

2 Performance evaluaton of ppelnes (II) If lookng at ndvdual classes of nstructons wth f = Tme Speedup overall = Tme IC IC total ClockClycle = 1 = n ClockClycle n = 1 IC CPI IC CPI If IC total does not change, you can also use the average Instructon executon tme (AvIETme) Tme Speedup overall = Tme ClockClycle = 1 = n ClockClycle n = 1 f f CPI CPI Comparng and non- executon An deal ppelne produces one result per clock cycle Ideal CPI = 1 Tme usng the average nstructon executon tme (AvIETme) Tme = no Tme Speedup = Tme non_ ppelne_ stages non_ AvIETme Speedup= AvIETme CPI non_ = CPI = no non_ ppelne_ stages ClockCycle ClockCycle non_

3 Comparng and non executon (II) Realstc CPI = Ideal CPI + Ppelne stall cycles per nstructon Thus: Speedup= AvIETme AvIETme non_ CPI non_ ClockCycle = 1+ PpelneStallCyclesPerInstr ClockCycle non_ If ClockCycle s constant: CPInon_ Speedup= 1 + PpelneStallCyclesPerInstr Example I (A) Gven an non- processor: 1 ns clock cycle tme 4 Cycles for ALU operatons 4 cycles for branches 5 cycles for memory operatons (B) Gven also a processor 1.2 ns clock cycle tme Both (A) and (B) have 40% ALU operatons 40% branches 20% memory operatons What s the speedup of (B) over (A) due to ppelnng?

4 For machne (A): AvIETme ( A) Example I = ClockCycle A n = 1 f CPI = 1 ns ( ) = 4. 4ns For machne (B): assumng deal CPI (= 1) AvIETme ( B) = ClockCycle B n = 1 f CPI = 1.2ns ( ) = 1. 2ns Thus Speedup= AvIETme AvIETme ( A) ( B) 4.4ns = 1.2ns = 3.7 Exceptons Instructon executon order s nterrupted E.g. I/O devce request Invokng an OS servce from an applcaton Tracng executon Breakpont or FP arthmetc anomaly (e.g. overflow) Page fault Msalgned memory access Memory protecton volaton Hardware malfuncton

5 Classfcaton of Exceptons Problems wth ppelnng: Dfferent stages of the ppelne can rase exceptons leadng to a dfferent order of exceptons compared to the un case Classes of exceptons 1. Synchronous vs. Asynchronous: 2. User requested vs. Coerced 3. User maskable vs. user non-maskable 4. Wthn vs. between nstructons 5. Resume vs. termnate Exceptons Most problematc: exceptons rased wthn nstructons, where the nstructon must be resumed Another program must be nvoked to save the state of the program Ppelnes capable of handlng exceptons are called restartable Ppelne stage IF ID EX MEM WB Possble exceptons Page fault on Instructon fetch; msalgned memory access; memory protecton volaton Undefned or llegal opcode Arthmetc excepton Page fault on data fetch; msalgned memory access; memory protecton volaton Non

6 Exceptons Snce an excepton can not be rased when t occurs Status vector assocated wth nstructon shows excepton Status vector carred along wth nstructon Wrtng of data values dsabled f status vector s set In WB status vector checked and excepton handled => Excepton of nstructon handled before excepton of nstructon +1 => Snce no data values are wrtten back, regster fle not changed -> nstructon can be repeated Mult-cycle nstructons Floatng pont nstructons can take many cycles to complete Often mplemented by multple executons of the EX stage Not all nstructons wll take the same amount of cycles to fnsh! Latency: number of ntervenng cycles between an nstructon that produces a result and nstructon that uses the result Usually: depth of the EX stage -1 Intaton nterval: Number of cycles that must elapse between ssung two operatons of a gven type Mult-cycle nstructons/ppelnes ncrease the probablty for occurrng WAW and RAW hazards

7 Example for a mult-cycle ppelne unt EX FP/ multply unt M1 M2 M3 M4 M5 M6 M7 IF ID FP/ add unt A1 A2 A3 A4 MEM WB FP/ dvson (non ) DIV Functonal unt Latency Intaton nterval ALU 0 1 Data memory 1 1 FP add 3 1 FP multply 6 1 FP dvde Instructon level parallelsm Explot parallelsm between ndependent nstructons Lmted by data dependences Lmted by branches Example: for (=0; <n; ++ ) { c[] = a[] + b[]; } Each teraton of the loop s ndependent Explotaton of that fact s not trval because of regster reuse!

8 Instructon level parallelsm Data dependences: True dependences: nstructon produces a result requred by nstructon +k, k>0 (RAW) sharng a regster or a memory locaton Name dependences: usage of the same regster or memory locaton wthout data flow Antdependence: nstructon +k wrtes a regster/memory locaton read by nstructon (WAR) No problem f not reorderng nstructons Output dependence: nstructon and nstructon +k wrte the same regster/memory locaton (WAW) No problem f not reorderng nstructons Control dependences: determnes orderng of an nstructon wth respect to a branch Dynamc schedulng Up-to-now Instructons are ssued n program order If an nstructon s stalled n the ppelne, no later nstructon can proceed DIV.D F0, F2, F4 ADD.D F10, F0, F8 SUB.D F12, F8, F14 In order to allow out-of-order executon, the ID stage s splt nto two parts: Instructon ssue: decode nstructon and check for structural hazards Read operands: Read operands f no data hazard

9 Dynamc schedulng Out-of-order executon ntroduces the possblty of WAR and WAW hazards DIV.D F0, F2, F4 DIV.D F0, F2, F4 ADD.D F10, F0, F8 SUB.D F8, F8, F14 SUB.D F8, F8, F14 ADD.D F10, F0, F8 Out-of-order executon only mproves performance f Multple nstructons can be executed at once Multple functonal unts are avalable All nstructons pass through the ssue stage n order Instructons can be bypassed n the read-operand stage Algorthms allowng nstructons to execute out-of-order Scoreboardng Tomasulo s approach Scoreboardng Frst mplemented n the CDC6600 Assumpton for the followng sldes: 2 multplers 1 adder 1 dvder 1 nteger unt Each nstructon goes through the scoreboard Scoreboard determnes when an nstructon can execute Scoreboard montors usage of executon unts Scoreboard montors when a result can be wrtten to the destnaton regster

10 Scoreboardng (II) 4 steps of Scoreboardng (replaces ID, EX and WB) 1. Issue: f functonal unt s free and no other actve nstructon has the same destnaton regster 2. Read operands: Scoreboard montors the avalablty of operands. An operand s avalable f no earler, actve nstructon s gong to wrte t. 3. Executon 4. Wrte result: f Executon done, Scoreboard checks for WAR hazards and stalls the nstructon of necessary. Scoreboardng (II) Scoreboard data structures: : whch of the four steps the nstructon s n : status of a functonal unt. Busy: ndcates whether unt s busy or not Op: operaton to be performed F: Destnaton regster number Fj, Fk: Source regster number Qj, Qk: Functonal unts producng source regsters Fj, Fk Rj, Rk: Flags ndcatng whether Fj, Fk are ready. Set to NO after operands are read. : whch functonal unt wll wrte whch regster

11 Scoreboardng example L.D F6, 34(R2) L.D F2, 45(R3) MUL.D F0, F2, F4 SUB.D F8, F6, F2 DIV.D F10, F0, F6 Followng sldes are based on a lecture by Jelena Mrkovc, Unversty of Delaware Assumpton: ADD and SUB take 2 clock cycles MULT takes 10 clock cycle DIV takes 40 clock cycles Tme=1 Issue frst load L.D F6, 34(R2) L.D F2, 45(R3) MUL.D F0, F2, F4 SUB.D F8, F6, F2 DIV.D F10, F0, F6 Yes Load F6 R2 Yes Mult1 Add Dvde

12 Tme=2 frst load read operands; second load can not ssue (structural hazard) L.D F6, 34(R2) L.D F2, 45(R3) MUL.D F0, F2, F4 SUB.D F8, F6, F2 DIV.D F10, F0, F6 Yes Load F6 R2 No Mult1 Add Dvde Tme=3 frst load completes exec; second load can not ssue (SH) L.D F6, 34(R2) L.D F2, 45(R3) MUL.D F0, F2, F4 SUB.D F8, F6, F2 DIV.D F10, F0, F6 Yes Load F6 R2 No Mult1 Add Dvde

13 Tme=4 frst load wrtes result; second load can not ssue (SH) L.D F2, 45(R3) MUL.D F0, F2, F4 SUB.D F8, F6, F2 DIV.D F10, F0, F6 Mult1 Add Dvde Tme=5 Second load s ssued L.D F2, 45(R3) MUL.D F0, F2, F4 SUB.D F8, F6, F2 DIV.D F10, F0, F6 Yes Load F2 R3 Yes Mult1 Add Dvde

14 Tme=6 Second load reads operands; Mult s ssued L.D F2, 45(R3) MUL.D F0, F2, F4 SUB.D F8, F6, F2 DIV.D F10, F0, F6 Yes Load F2 R3 No Mult1 Yes Mult F0 F2 F4 No Yes Add Dvde Mult1 Tme=7 Second load completes exec; Mult s stalled watng for F2; Sub s ssued L.D F2, 45(R3) MUL.D F0, F2, F4 SUB.D F8, F6, F2 DIV.D F10, F0, F6 Yes Load F2 R3 No Mult1 Yes Mult F0 F2 F4 No Yes Add Yes Sub F8 F6 F2 Yes No Dvde Mult1 Add

15 Tme=8 Second load wrtes result; Mult and Sub stalled (F2); Dv s ssued MUL.D F0, F2, F4 SUB.D F8, F6, F2 Mult1 Yes Mult F0 F2 F4 Yes Yes Add Yes Sub F8 F6 F2 Yes Yes Dvde Yes Dv F10 F0 F6 Mult1 No Yes Mult1 Add Dv Tme=9 Mult and Sub read operands; Dv stalled watng for (F0); Add not ssued (SH) MUL.D F0, F2, F4 SUB.D F8, F6, F2 Mult1 Yes Mult F0 F2 F4 No No Add Yes Sub F8 F6 F2 No No Dvde Yes Dv F10 F0 F6 Mult1 No Yes Mult1 Add Dv

16 Tme=10 Mult executng (1 out of 10 cycles); Sub executng (1 out of 2 cycles); Dv stalled (F0); MUL.D F0, F2, F4 SUB.D F8, F6, F2 Mult1 Yes Mult F0 F2 F4 No No Add Yes Sub F8 F6 F2 No No Dvde Yes Dv F10 F0 F6 Mult1 No Yes Mult1 Add Dv Tme=11 Mult executng (2/10); Sub completes executon; Dv stalled (F0); MUL.D F0, F2, F4 SUB.D F8, F6, F2 Mult1 Yes Mult F0 F2 F4 No No Add Yes Sub F8 F6 F2 No No Dvde Yes Dv F10 F0 F6 Mult1 No Yes Mult1 Add Dv

17 Tme=12 Mult executng (3/10); Sub wrtes result; Dv stalled (F0); MUL.D F0, F2, F4 Mult1 Yes Mult F0 F2 F4 No No Add Dvde Yes Dv F10 F0 F6 Mult1 No Yes Mult1 Dv Tme=13 Mult executng (4/10); Dv stalled (F0); Add ssued MUL.D F0, F2, F4 Mult1 Yes Mult F0 F2 F4 No No Add Yes Add F6 F8 F2 Yes Yes Dvde Yes Dv F10 F0 F6 Mult1 No Yes Mult1 Add Dv

18 Tme=14 Mult executng (5/10); Dv stalled (F0); Add reads operands MUL.D F0, F2, F4 Mult1 Yes Mult F0 F2 F4 No No Add Yes Add F6 F8 F2 No No Dvde Yes Dv F10 F0 F6 Mult1 No Yes Mult1 Add Dv Tme=15 Mult executng (6/10); Dv stalled (F0); Add executes (1 of 2 cycles) MUL.D F0, F2, F4 Mult1 Yes Mult F0 F2 F4 No No Add Yes Add F6 F8 F2 No No Dvde Yes Dv F10 F0 F6 Mult1 No Yes Mult1 Add Dv

19 Tme=16 Mult executng (7/10 cycles); Dv stalled (F0); Add completes exec MUL.D F0, F2, F4 Mult1 Yes Mult F0 F2 F4 No No Add Yes Add F6 F8 F2 No No Dvde Yes Dv F10 F0 F6 Mult1 No Yes Mult1 Add Dv Tme=17 Mult executng (8/10); Dv stalled (F0); Add stalled (WAR hazard on F6) MUL.D F0, F2, F4 Mult1 Yes Mult F0 F2 F4 No No Add Yes Add F6 F8 F2 No No Dvde Yes Dv F10 F0 F6 Mult1 No Yes Mult1 Add Dv

20 Tme=19 Mult completes exec; Dv stalled (F0); Add stalled (WAR hazard on F6) MUL.D F0, F2, F4 Mult1 Yes Mult F0 F2 F4 No No Add Yes Add F6 F8 F2 No No Dvde Yes Dv F10 F0 F6 Mult1 No Yes Mult1 Add Dv Tme=20 Mult wrtes result; Dv stalled (F0); Add stalled (WAR hazard on F6) MUL.D F0, F2, F4 Mult1 Add Yes Add F6 F8 F2 No No Dvde Yes Dv F10 F0 F6 Yes Yes Add Dv

21 Tme=21 Dv reads operands; Add stalled (WAR hazard on F6) MUL.D F0, F2, F4 Mult1 Add Yes Add F6 F8 F2 No No Dvde Yes Dv F10 F0 F6 No No Add Dv Tme=22 Dv executes (1/40); Add wrtes result MUL.D F0, F2, F4 Mult1 Add Dvde Yes Dv F10 F0 F6 No No Dv

22 Tme=61 Dv completes executon MUL.D F0, F2, F4 Mult1 Add Dvde Yes Dv F10 F0 F6 No No Dv Tme=62 Dv wrtes result MUL.D F0, F2, F4 Mult1 Add Dvde

23 Scoreboardng (IV) Performance of scoreboardng depends on The amount of parallelsm avalable among nstructons Number of scoreboard entres Number and type of functonal unts Presence of antdependeces and output dependences