# Caches (cont d) Topics. Example. Reading Assignment and Sample Problems. Calculating Average Access Time

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1 Caches (cont d) Reading Assignment and Sample Problems Read Chapter 7, Section 7. Chapter 7, problems 7.19, 7.20, 7.21 These may show up on some upcoming quiz CS 333 Fall 2006 Topics Hit and Miss ratios Cache mapping functions (+ pros, cons) Direct-mapped (Fully) Associative-mapped Block-Set Associative (n-way Set Associative) Cache Operations Placement strategy Replacement strategy Read and write policy Review of Terminology Block aka line, minimum unit of information Hit data is found in upper level Hit rate fraction of memory accesses that are found in upper level Hit time time to access the upper level time to determine if it s a hit + time to access data Miss Miss rate - (1 hit rate) fraction not found in upper level Miss penalty Time to replace a block in upper level with corresponding block in lower level + time to deliver block to the processor Calculating Average Access Time t a = average access time h= hit rate, m = miss rate t h = hit time, t m = miss time t a = (h * t h ) + (m * t m ) Hit rate = number of hits / total number of accesses Miss rate = 1 hit rate Speedup = Time without cache / Time with caches Example A direct mapped cache has an access time of 2 ns and takes 40 ns to service a cache miss. Without the cache, main memory access time was 0 ns. Running benchmarks on designs both with and without caches shows 80% speedup. What is the approximate hit ratio of the cache?

2 Cache Operations Direct-Mapped Caches Placement strategy Where to place an incoming block in the cache Replacement strategy Which block to replace on cache miss Read and write policies How to handle reads and writes on cache hits and misses Cache Mapping Function Direct-mapped Cache CPU Word Cache Block Main memory Address Mapping function Has to be implemented in hardware. Why? 26 cache blocks 8 bytes Direct-mapped Cache Operation Direct-Mapped Example Direct-mapped ) Byte-able Offset fields of the 32-bit? 19 8

3 What is the Number of Bits to Implement? Num_entries * (Tag bits + Valid Bit + Data bits) 2 8 * ( ) 70, KB Direct-Mapped Caches Pros Less hardware Simple block replacement Cons Restrictive in block placement Frequently referenced blocks that map to same index will thrash (lower performance) Fully Associative-Mapped Caches (Fully) Associative Mapped Caches Any block from main memory can map to any location in the cache Fully Associative Example Fully Associative Cache Operation All locations searched simultaneously Tag 8 bytes

4 Fully Associative Example Fully-associative ) Byte-able Offset fields of the 32-bit? What is the Number of Bits Required to Implement? Num_entries * (Tag bits + Match bit + Valid Bit + Data bits) 2 8 entries * ( bits) 72,960 bits 8.91 KB 27 0 Compare to Direct-mapped: 8.62 KB 2304 more bits Fully Associative Caches Pros Flexible placement Any main memory block can go anywhere in the cache Cons Large tag memory Need to search entire tag memory lots of hardware What s a good replacement policy? (more later) Block-Set Associative Caches Block-Set Associative Caches Example: 2-way Set Associative Shares properties with direct-mapped and fully associative More than one block can occupy the same index location in the cache Group/ Index byte offset

5 2-way Set Associative Example 2-way set associative ) Byte-able Offset fields of the 32-bit? 20 7 How Many Bits to Implement? Num_entries * ( (num_ways*tag bits) + (num_ways * valid bits) + (num_ways * match bit) + (num_ways*data bits)) 2 7 * ((2*20) + (2*1) + (2*1) + (2*26)) 71,168 bits 8.68 KB 4-way Set Associative Example 4-way set associative ) Byte-able Offset fields of the 32-bit? 21 6 How Many Bits to Implement? Num_entries * ( (num_ways*tag bits) + (num_ways * valid bits) + (num_ways * match bit) + (num_ways*data bits)) 2 6 * ((4*21) + (4*1) + (4*1) + (4*26)) 71,424 bits 8.72 KB Summary For same amount of data storage Direct-mapped smaller tags, smaller implementation area than associative counterparts Fully-associative larger tags, larger total implementation area than direct-mapped counterpart Read and Write Policies

6 Write Policies on Cache Hit Write-through Update both cache and main memory on a write Advantageous when: Few writes Disadvantageous: Many writes (takes time) Write-back Write to cache only. Update main memory when block is replaced (needs dirty bit per cache block) Read Miss Policies Read block in from main memory. Two approaches: Forward desired word first (faster, but more hardware needed) Delay until entire block has been moved to cache Write Miss Policies Write allocate Bring block to cache from memory, then update Write-no allocate Only update main memory (don t bring into cache) Block Replacement Strategies Write through caches usually use write-no allocate Write-back caches usually use write allocate Block Replacement Policies If the cache is full Least recently used (LRU) Uses counters Random replacement

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