An SP-based Programming Model for Consumer Electronics Streaming Applications

Transcription

1 C P S A L SP@CE An SP-based Programming Model for Consumer Electronics Streaming Applications Ana Lucia Varbanescu, Maik Nijhuis, Arturo Gonzalez-Escribano Herbert Bos, Henk Sips, Henri Bal

2 Outline Motivation Platform trends Application shift The model and the framework Experiments & Results Conclusions & Future work

3 Platform trends: multi-cores State of the art mostly prototypes heterogeneous programmable cores original memory hierarchies complex interconnections (network-on-chip) Mainstream? iff they become programmable Trend more cores, more memory, more interconnections

4 Application shift: user-interaction More irregular parallelism Machine independent Highly interactive and responsive Multimedia streaming More and more data bound, less compute bound

5 the model Is it the time for a new programming model? Not really ready for one-size fits all A new programming model that: Addresses consumer electronics requirements Deals with (multimedia) streaming applications It is based on SP(C) Uses a data-flow like model of computation

6 CE application requirements Consumer Electronics (CE): user interaction + multi-cores Dynamic re-configurability Event awareness & handling awareness -> reactive application handling -> timely manner Performance predictability soft real-time requirements -> user satisfaction

7 Streaming applications Streams Infinite data flows Active window Filters Components processing the streams Data flow: synchronous Application iteration = one end-to-end processing Control flow: asynchronous the application is reactive to internal/external conditions

8 Programming model: SPC SPC = Series-Parallel Contention Composition: series-parallel Synchronization: mutual exclusion by contention Offers: Ease of reasoning and programming Unbounded algorithmic task and data parallelism Dynamic process-to-resource mapping Analyzability and performance prediction

9 SPC: synchronization language process main{ process1; process2; par { if (cond) then X else Y par(i=1,n) P(i) }; process3;} D E B C A X if D 1 2 Y 3 P0 par P1 Pn E A B C

10 SPC: Contention Application process1; par (i=1..3){ process2(i); process3(i) }; process4 P1 P0 P2 Resources process1 -> P0; process2(i)-> P1; process3(i)-> P1; process4 -> P2;

11 the framework Front-End SPC-XML Hinch PAM-SoC HW Platform Machine model

12 A application Event Manager Events queue Filter/Component Control flow Data flow (stream) Not allowed Application iteration

13 Front-end Data flow: draw the graph of components reconfigure graph Control flow: Internal: component language (C) Border: synchronous => fixed data rate External: FSM event manager Event Manager (external) Border control Internal control

14 SPC-XML XML based language easy to process, easy to extend Optimizations & reductions Generates C-code Performance prediction code Gonzalez-Escribano et. al.: SPC-XML: A structured representation for nested-parallel programming languages. Volume 3648., Springer-Verlag (2005)

15 Hinch Run-time system Executes the C-code SPC-XML generates Component-based Input/output ports, for either Streams or Events Recursive grouping => application Auto load balancing: job queue Nijhuis, M., Bos, H., Bal, H.: Supporting reconfigurable parallel multimedia applications In: Euro-Par 06 (distinguished paper),

16 Hinch Model of computation: dataflow CPUs continuously fetch jobs from job queue (job == one component invocation) Scheduling dependencies are used to add jobs to queue

17 PAM-SoC Performance prediction tool Analyzes the performance code SPC-XML generates Based on PAMELA Extended for MPSoC s/ce s Generates feedback for application tuning application model Hardware params machine model Varbanescu, A.L., van Gemund, A., Sips, H.: PAM-SoC: A toolchain for predicting MPSoC performance. Euro-Par 06,

18 PAM-SoC toolchain Application conversion MemBE application model MemBE Simulator Source code Automatic application modeling PAMELA application model Memory behaviour statistics Hardware latencies Manual machine modeling PAMELA machine model PAMELA Compiler Symbolic cost model PAMELA Evaluator

19 Experiments platform: Wasabi Processing 1-9 TM processors, 1 ARM Special Function Units Memory L1 each TM L2 shared, banked HW cache coherency Off-chip memory Programming: C/C++, on ecos Note: Experiments have been run on CAKEsim, the Wasabi cycle-accurate simulator

20 P-i-P application Non-SP Main Input Blend Y PiP Input Downscale Y Downscale UV Blend UV Output SP Main input Blend Y PiP input Downscale Y Downscale UV Blend UV Output

21 Motion JPEG application Functionality Application graph

22 JPiP: Motion JPEG + P-i-P Combined Motion JPEG and P-i-P Reused components : MJPEG, PiP One SP synchronization point added

23 JPiP performance MJ-P-i-P speed-up Overhead speedup ideal speedup PiP-0 PiP-1 PiP-2 PiP-3 MJPEG JPiP-0 JPiP-1 JPiP-2 JPiP-3 cycles x Non-SP@CE SP@CE - sequential SP@CE - 2 nodes nodes PiP-0 PiP-1 PiP-2 PiP-3 Application MJPEG

24 Related work Streaming models TStreams Space-Time Memory Languages StreamIT Brook System-C/Kernel-C Models of computation Data flow Kahn process networks

25 Conclusions Requirements for CE streaming applications programming model Induces (more) structured programming SP Offers low overhead, predictability, (re)usability Streams, reconfiguration, events framework Full design-to-implementation path Includes performance prediction path

26 Future work Short term Port on more diverse platforms NUMA machine IBM s CELL BE Medium and long term Enhance the optimization/ reduction engine Improve the performance prediction GUI for the front-end

27 Thank you! Questions? Suggestions? Remarks? Complaints? Lunch? There's an old story about the person who wished his computer was as easy to use as his telephone. That wish has come true, since I no longer know how to use my telephone. (Bjarne Stroustrup) A.L.Varbanescu@tudelft.nl avarban@us.ibm.com