UConn UTC Workshop on Advanced Systems Engineering Research and Curriculum Development

Transcription

1 Multicore Software for Safety Critical Applications Omer Khan Assistant Professor of Electrical and Computer Engineering University of Connecticut (860) Workshop on Research and Curriculum Development Opportunities 2013 October 1 st, 2013 Student Union Rooms 304 b/c, UConn Storrs Campus, Storrs, CT

2 Multicore is the System Performance per Watt Ease of Programmability? Shared memory abstraction Tilera 1. Integration 2. Specialization Whatever s Inside a single chip! AMD 2

3 What makes parallel programming hard? pthreads race conditions atomicity violations deadlock order violations Insanity: Doing the same thing over and over again and expecting different results

4 Multicore software for safety critical applications Our focus: How to overcome the grand challenge of debugging multithreaded software? Our approach: Design software for performance and power efficiency Utilize new tools and ISA extensions for deterministic test and debug Deterministic? 4

5 Immediate solution for debugging multithreaded software Sequential Safe (Serial-Equivalent) Concurrency One option is to use Grace [OOPSLA 09] for programs employing fork-join parallelism (such as OpenMP) Turns threads into processes and leverages virtual memory protection Imposes a sequential commit protocol Gives programmer appearance of deterministic, sequential execution while exploiting parallelism 5

6 Immediate solution for debugging multithreaded software deterministic Deterministic Multithreading One option is to use DTHREADS [SOSP 12] to eliminate the non-determinism Eliminate Heisenburgs by ensuring that executions of the same program with the same inputs always yield the same results Simplify debugging of concurrent programs, and simplify testing overhead and enable resiliency Converts multithreaded applications into multiple processes, with private, copy-on-write mappings to shared memory Tracks writes and deterministically orders updates by each thread 6

7 Next-gen solution for debugging multithreaded software Intel s Transactional Synchronization Extensions (TSX) HLE: Hardware Lock Elision XACQUIRE/XRELEASE Software uses legacy compatible hints to identify critical section Hardware support to execute transactionally without acquiring lock Abort causes re-execution without elision Hardware manages all architectural state RTM: Restricted Transactional Memory XBEGIN/XEND Similar to HLE but flexible interface for software to do lock elision Abort transfers control to target specified by XBEGIN operand Abort information returned in a general purpose register (EAX) XTEST and XABORT Additional instructions Intel s Haswell multicore processors bring transactional memory to the mainstream from mobile to server market 7

8 Summary Multicores have the potential to give tremendous performance, power and cost benefits This research will evaluate the following software development questions: Can we write safe, testable multithreaded software for safety critical applications? Can we achieve the 3Ps with multicores? i.e., performance, power, programmability 8