Dual-port Capabilities

Transcription

1 Replacement of a RAM with Atmel FreeRAM in VHDL FreeRAM Features Atmel s AT0K family of FPGAs includes distributed blocks of RAM throughout the device. These blocks are called FreeRAM. Atmel s FreeRAM is a versatile component. It can be configured to four different types: Single-port RAM: Asynchronous or Synchronous D[3:0] A[:0] RAMS Dual-port RAM: Asynchronous or Synchronous DIN[3:0] DOUT[3:0] AIN[:0] AOUT[:0] RAMD D[3:0] A[:0] RAMSSYNC DIN[3:0] DOUT[3:0] AIN[:0] AOUT[:0] RAMDSYNC The routing resources connecting the RAM are optimized for each mode. For example, the routing nets needed to route the DOUT signals on the dual-port RAM is not used on the single-port RAMs. These unused resources can be used for other routing schemes for another area in the design. Architectural Differences Atmel has dedicated RAM blocks inside their FPGAs. Within every x core cell sector, there is a FreeRAM cell that can be used as 32 x dual-port RAM. This frees up the core cells to be used for logic. RAMs do not have any separate RAM and must use its CLB to generate them. For example, a FIFO design is created that requires the use of a 128 x dualport RAM. This design would require 128 CLBs alone just for the RAM; logic would increase that number. If this same design was developed using Atmel s FreeRAM, the RAM would fit into an AT0K05, but the core cells would be unused, allowing additional logic to fit into a small device. Dual-port Capabilities Dual-port RAM capability is truly achieved in the Atmel architecture. RAMs use only one signal (WE) for this write and output enable. Simultaneous read and write is not possible. By asserting WE high, the RAM can only perform a write operation; disabling WE performs a read operation. Atmel RAM implements separate signals for the write and output enables as well as the data input and output. This allows simultaneous read and write operations. Modifying VHDL Codes to Implement Atmel RAM Figure 1 shows how a RAM is implemented in VHDL. Figure 2 shows how that same design is converted to implement Atmel RAM. It is very important to remember that the polarity for the write enable in the Atmel RAM is active low. For designs where the write signals were active high, an inverter is necessary to correct the polarity. Replacement of a RAM with Atmel FreeRAM in VHDL Application Note Rev. 19A 02/00 1

2 During synthesis, the front-end tool will generate a black box for the RAM component. Creation of the RAM block will be generated by the Macro Generator in the IDS software. The RAM will be stored inside a user-defined library. When the design netlist is imported to IDS, the black box definition calls the RAM definition within the user library. The design can be placed and routed after successful import. Replacing RAM Components in VHDL It is possible to convert a design using RAM into the Atmel architecture without modifying the rest of the original VHDL code. A new file needs to be created. Inside this file is the entity and architecture declaration of the RAM. Under the architecture block section, an Atmel component is called and port mapped to simulate the RAM. Figures 3, and 5 show how to implement an Atmel RAM underneath the RAM. Synthesis of the design follows the same procedure previously mentioned. Importing Design into Figaro Prior to importing the.edif netlist, the RAM must be generated and stored within a user-defined library. This is achieved by using the Macro Generator tool integrated with the software. After generating the RAM, the macro will be called during the.edif import. 2 FPGAs

3 FPGAs Figure 1. Sample VHDL File Implementing RAM entity example is port ( clk : in std_logic; wr : in std_logic; data_a : out std_logic_vector(31 downto 0); data_b : in std_logic_vector(15 downto 0) ); end example; architecture arch of example is component dprx port( DPO : out std_logic_vector(15 downto 0); SPO : out std_logic_vector(15 downto 0); DI : in std_logic_vector(15 downto 0); A : in std_logic_vector(3 downto 0); DPRA : in std_logic_vector(3 downto 0); WR_ : in std_logic; WR_EN : in std_logic ); end component; DI[15:0] A[3:0] DPRA[3:0] WR_EN WR_ SPO[15:0] DPO[15:0] DPRX signal ptra : std_logic_vector(3 downto 0); signal ptrb : std_logic_vector( downto 0); signal nullnode : std_logic_vector(15 downto 0); signal wrblo signal wrbhi : std_logic; : std_logic; begin wrblo <= wr and NOT ptrb(0); wrbhi <= wr and ptrb(0); RAMLO : dprx port map ( A => ptrb( downto 1), SPO => nullnode, DI => data_b, WR_EN => wrblo, WR_ => clk, DPO => data_a (15 downto 0), DPRA => ptra ); RAMHI : dprx port map ( A => ptrb( downto 1), SPO => nullnode, DI => data_b, WR_EN => wrbhi, WR_ => clk, DPO => data_a (31 downto ), DPRA => ptra ); end arch; Note: SPO is never used in the design. The user must create the dummy signal nullnode and connect it to the component so synthesis will not complain. 3

4 Figure 2. Sample VHDL File Implementing Atmel RAM entity example is port ( clk : in std_logic; wr : in std_logic; data_a : out std_logic_vector(31 downto 0); data_b : in std_logic_vector(15 downto 0) ); end example; architecture arch of example is component ramx port( dout : out std_logic_vector(15 downto 0); din : in std_logic_vector(15 downto 0); ain : in std_logic_vector(3 downto 0); aout : in std_logic_vector(3 downto 0); clk : in std_logic; wen : in std_logic; oen : in std_logic ); end component; signal ptra : std_logic_vector(3 downto 0); signal ptrb : std_logic_vector( downto 0); signal oe : std_logic; signal wrblo : std_logic; signal wrbhi : std_logic; DIN[15:0] DOUT[15:0] AIN[3:0] AOUT[3:0] RAMX begin oe <= 0 ; wrblo <= not (wr and not ptrb(0)); wrbhi <= not (wr and ptrb(0)); RAMLO : ramx port map ( dout => data_a (15 downto 0), din => data_b, ain => ptrb( downto 1), aout => ptra, clk => clk, wen => wrblo, oen => oe ); RAMHI : ramx port map ( dout => data_a (31 downto ), din => data_b, ain => ptrb( downto 1), aout => ptra, clk => clk, wen => wrbhi, oen => oe ); END arch; Notes: 1. This component will be created using the Macro Generator in IDS. For this example, the following information will be entered: Section: Memory, RAM Dual-port Address Width: Width: Ram Type: Synchronous Macro Name: RAMx 2. A RAM uses one signal to control the write and output enables of a RAM. Atmel has separate ports for these controllers. The simplest solution is to always assert the output enable. A RAM can only perform a write or read, but not both. It s assumed that the data coming out of DOUT will only be sampled when the write enable is disabled. The original design assumes that the write enable is active high. Atmel RAM defines its write enable to be active low. Therefore, inverters are needed to correct the signal interface. FPGAs

5 FPGAs Figure 3. A RAM with Buried Atmel Component Example 1 LIBRARY ieee; USE ieee.std_logic_1.all; ENTITY ram32x IS PORT ( D : in std_logic_vector(3 downto 0); A : in std_logic_vector( downto 0); WE : in std_logic; O : out std_logic_vector(3 downto 0) ); END ram32x; ARCHITECTURE replace OF ram32x IS D3 D2 D1 D0 A A3 A2 A1 A0 5 DIN[3:0] AIN[:0] AOUT[:0] DOUT[3:0] O3 O2 O1 O0 COMPONENT dpr32x PORT ( WE ATMEL RAMD DIN : in std_logic_vector(3 downto 0); AIN : in std_logic_vector( downto 0); XILINX RAM32X AOUT : in std_logic_vector( downto 0); : in std_logic; : in std_logic; DOUT : out std_logic_vector(3 downto 0) ); END COMPONENT; BEGIN U1 : dpr32x PORT MAP ( DIN => D, AIN => A, AOUT => A, => NOT WE, => WE, DOUT => O ); END replace; Notes: 1. This is an asynchronous 32 x dual-port RAM with single-port addressing. 2. This component will be created using the Macro Generator in IDS. For example, the following information will be entered: Section: Memory, RAM Dual-port Address Width: 5 Width: RAM Type: Synchronous 5

6 Figure. A RAM with Buried Atmel Component Example 2 LIBRARY ieee; USE ieee.std_logic_1.all; ENTITY ram32xs IS PORT ( D : in std_logic_vector(3 downto 0); A : in std_logic_vector( downto 0); WE : in std_logic; W : in std_logic; O : out std_logic_vector(3 downto 0) ); END ram32xs; D3 D2 D1 D0 A A3 A2 A1 A0 5 DIN[3:0] AIN[:0] AOUT[:0] DOUT[3:0] O3 O2 O1 O0 ARCHITECTURE replace OF ram32xs IS WE COMPONENT sdpr32x PORT ( W ATMEL RAMDSYNC DIN : in std_logic_vector(3 downto 0); AIN : in std_logic_vector( downto 0); XILINX RAM32XS AOUT : in std_logic_vector( downto 0); : in std_logic; : in std_logic; : in std_logic; DOUT : out std_logic_vector(3 downto 0) ); END COMPONENT; BEGIN U1 : sdpr32x PORT MAP ( DIN => D, AIN => A, AOUT => A, => W, => NOT WE, => WE, DOUT => O ); END replace; Note: This component will be created using the Macro Generator in IDS. For this example, the following information will be entered: Section: Memory, RAM Dual-port Address Width: 5 Width: Ram Type: Synchronous 6 FPGAs

7 FPGAs Figure 5. A RAM with Buried Atmel Component Example 3 LIBRARY ieee; USE ieee.std_logic_1.all; ENTITY ramxd IS PORT ( D : in std_logic_vector(3 downto 0); A : in std_logic_vector(3 downto 0); DPRA : in std_logic_vector(3 downto 0); WE : in std_logic; W : in std_logic; SPO : out std_logic_vector(3 downto 0); DPO : out std_logic_vector(3 downto 0) ); END ramxd; ARCHITECTURE replace OF ramxd IS D3 D2 D1 D0 A3 A2 A1 A0 DPRA3 COMPONENT sdprx PORT ( DPRA2 DIN : in std_logic_vector(3 downto 0); DPRA1 AIN : in std_logic_vector(3 downto 0); DPRA0 AOUT : in std_logic_vector(3 downto 0); : in std_logic; WE : in std_logic; W : in std_logic; DOUT : out std_logic_vector(3 downto 0) ); END COMPONENT; DIN[3:0] AIN[3:0] AOUT[3:0] DOUT[3:0] ATMEL RAMDSYNC DIN[3:0] DOUT[3:0] AIN[3:0] AOUT[3:0] ATMEL RAMDSYNC XILINX RAMXD SPO3 SPO2 SPO1 SPO0 DPO3 DPO2 DPO1 DPO0 SIGNAL OE : std_logic; BEGIN OE <= 0 ; SPO : sdprx PORT MAP ( DIN => D, AIN => A, AOUT => A, => W, => NOT WE, => OE, DOUT => SPO ); DPO : sdprx PORT MAP ( DIN => D, AIN => A, AOUT => DPRA, => W, => NOT WE, => WE, DOUT => DPO ); END replace; 7

8 Atmel Headquarters Corporate Headquarters 2325 Orchard Parkway San Jose, CA TEL (08) FAX (08) Europe Atmel U.K., Ltd. Coliseum Business Centre Riverside Way Camberley, Surrey GU15 3YL England TEL () FAX () Asia Atmel Asia, Ltd. Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimhatsui East Kowloon Hong Kong TEL (852) FAX (852) Japan Atmel Japan K.K. 9F, Tonetsu Shinkawa Bldg Shinkawa Chuo-ku, Tokyo Japan TEL (81) FAX (81) Atmel Operations Atmel Colorado Springs 1150 E. Cheyenne Mtn. Blvd. Colorado Springs, CO TEL (719) FAX (719) Atmel Rousset Zone Industrielle Rousset Cedex France TEL (33) FAX (33) Fax-on-Demand North America: 1-(800) International: 1-(08) Web Site BBS 1-(08) Atmel Corporation Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company s standard warranty which is detailed in Atmel s Terms and Conditions located on the Company s web site. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel s products are not authorized for use as critical components in life support devices or systems. Marks bearing and/or are registered trademarks and trademarks of Atmel Corporation. Terms and product names in this document may be trademarks of others. Printed on recycled paper. 19A 02/00/xM