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1 Microprocesseurs 32 bits intel - AMD ( ) Pentium II, III, 4, Celeron ATHLON, ATHLON XP novembre 03 Microprocesseurs 32 bits Intel - AMD ; J. Weiss 1 Évolution des processeurs Pentium et Athlon Pentium Pro Pentium II (Klamath) Pentium II (Deschutes) Pentium III (Katamai) Pentium III (Coppermine) Athlon K7 Pentium 4 (Williamette) Athlon K7 (Thunderbird) Pentium III (Tualatin) Athlon XP (Palomino) Pentium 4 (NorthWood) Athlon XP (Thoroughbred) Athlon XP (Barton) novembre 03 Microprocesseurs 32 bits Intel - AMD ; J. Weiss 2

2 Pentium Pro ~1995 Horloge : MHz Front Side Bus : MHz Cache L1 : 8KB instruction, 8KB data Cache L2 : KB On-Chip. Technologie : 0,35 µm. 5,5 millions de transistors The first Intel CPU based on the P6 Microarchitecture. The CPU is contains a onchip L2 cache in the packaging running at core clock-speed. The CPU is intended for high end servers/workstations. novembre 03 Microprocesseurs 32 bits Intel - AMD ; J. Weiss 3 Pentium II ~1997 Horloge : MHz Front Side Bus : MHz Cache L2 : 512KB half-speed. Technologie : 0,35 µm Klamath ( MHz). 0,25 µm Deschutes ( MHz). 7,5 millions de transistors Due to the difficulty in manufacturing the Pentium Pro with on-chip L2 cache, Pentium II moved the L2 cache to an external cache reside in the Slot 1 package. L1 Cache is doubled, and added the MMX instructions. 100 MHz front side bus is introduced after 350 MHz models. novembre 03 Microprocesseurs 32 bits Intel - AMD ; J. Weiss 4

3 Pentium III (Katmai) ~1999 Horloge : MHz Front Side Bus : MHz Cache L2 : 512KB half-speed. Technologie : 0,25 µm. 9,5 millions de transistors Same as Pentium II with added new SSE SIMD instructions. The B model introduces 133 MHz front side bus. novembre 03 Microprocesseurs 32 bits Intel - AMD ; J. Weiss 5 Pentium III (Coppermine) ~1999 Horloge : MHz Front Side Bus : MHz Cache L2 : 256KB full-speed on die. 28 millions de transistors Major improvements from the original Pentium III, the L2 cache is now fully integrated onto the CPU die, and the L2 datapath, Associative, and Latency are also improved. The later model also use revert back to the more conventional FC-PGA socket model from Slot 1. novembre 03 Microprocesseurs 32 bits Intel - AMD ; J. Weiss 6

4 Pentium III (Tualatin) ~2001 Horloge : MHz Front Side Bus : 133 MHz Cache L2 : KB half-speed. 28 millions de transistors (256K L2) 46 millions de transistors (512K L2) Final revision on P6 architecture, with added data prefetch unit and higher clock speed. L2 also available in 512 KB version. This is the first Intel CPU that uses 0.13 micron copper-interconnect. novembre 03 Microprocesseurs 32 bits Intel - AMD ; J. Weiss 7 Celeron (Covington) ~1997 Horloge : MHz Front Side Bus : 66 MHz Cache L2 : -. Technologie : 0,35 µm. 7,5 millions de transistors A tripped down version of the Klamath Pentium II with no L2 cache on the Slot 1 module. Unsatisfactory performance. novembre 03 Microprocesseurs 32 bits Intel - AMD ; J. Weiss 8

5 Celeron (Mendocino) ~1998 Horloge : MHz Front Side Bus : 66 MHz Cache L2 : 128KB full-speed on die. Technologie : 0,25 µm. 19 millions de transistors Similar to Pentium II Deschutes but with integrated on-die 128 KB cache. Also available in Socket 370 package. novembre 03 Microprocesseurs 32 bits Intel - AMD ; J. Weiss 9 Celeron (Coppermine128) ~2000 Horloge : MHz Front Side Bus : MHz Cache L2 : 128KB full-speed on die. 28 millions de transistors A stripped down version of Pentium III Coppermine, the Coppermine128 core is physically identical to Coppermine Pentium III except half of the L2 cache is disabled and the front side bus is restricted to 66 MHz and 100mhz after 800 MHz models. novembre 03 Microprocesseurs 32 bits Intel - AMD ; J. Weiss 10

6 Celeron (Tualatin) ~2001 Horloge : MHz Front Side Bus : 100 MHz Cache L2 : 256KB full-speed on die. 28 millions de transistors Essentially the same as the Tualatin Pentium III with only 100 MHz front side bus. novembre 03 Microprocesseurs 32 bits Intel - AMD ; J. Weiss 11 Pentium 4 (Willamette) ~2000 Horloge : MHz Front Side Bus : 100 MHz QDR Cache L1 : 12KµOps instruction, 8KB data Cache L2 : 256KB full-speed on die. 42 millions de transistors The first CPU core with the new Netburst(P68) architecture. Because of the fact that it is still manufactured using the older 0.18 micron technology. The die of this CPU is extremely large. novembre 03 Microprocesseurs 32 bits Intel - AMD ; J. Weiss 12

7 Pentium 4 (Northwood) ~2002 Horloge : MHz Front Side Bus : MHz QDR Cache L1 : 12KµOps instruction, 8KB data Cache L2 : 512KB full-speed on die. 55 millions de transistors The second CPU based on the Netburst architecture. The processor is now manufactured using copper 0.13 micron technology. The L2 cache has been double in size to 512KB. However, the die size is still smaller than the Willamette. novembre 03 Microprocesseurs 32 bits Intel - AMD ; J. Weiss 13 Athlon K7 (Pluto, Orion) ~1999, 2000 Horloge : MHz Front Side Bus : 100 MHz DDR Cache L2 : 512KB externe. Technologie : 0,25 µm (Pluto). 0,18 µm (Orion). 22 millions de transistors The first processor based on the K7 architecture. The L2 cache is located on the external module similar to PII/III(katami) and runs at 1/2,3/5, 1/3 of the core clock speed. novembre 03 Microprocesseurs 32 bits Intel - AMD ; J. Weiss 14

8 Athlon K7 (Thunderbird) ~2000 Horloge : MHz Front Side Bus : MHz DDR Cache L2 : 256KB on die. 37 millions de transistors Similar to the improvement Intel made with the coppermine core, the thunderbird integrates the L2 cache into the processor die and running at full core clock speed. The thunderbirds produced in Dresden fab are also the first x86 CPU to use the copperinterconnect. novembre 03 Microprocesseurs 32 bits Intel - AMD ; J. Weiss 15 Athlon XP (Palomino) ~2001 Horloge : 1333(1500+) 1666(2100+) MHz Front Side Bus : 133 MHz DDR Cache L2 : 256KB on die. 37,5 millions de transistors The Palomino core is mainly a reworked Thunderbird core to reduce power consumption with added thermal diode. The core also incorporated the SSE instructions, increased TLB, and a data prefetch unit. Externally, the CPU is packaged using the OPGA array (ie. Plastic) instead of Ceramic. novembre 03 Microprocesseurs 32 bits Intel - AMD ; J. Weiss 16

9 Athlon XP (Thoroughbred) ~2002 Horloge : 1466(1700+) 2100(2800+) MHz Front Side Bus : MHz DDR Cache L2 : 256KB on die. 37,5 millions de transistors Simply a die shrunk of the Palomino core to 0.13 micron. All the functionalities remains unchanged. novembre 03 Microprocesseurs 32 bits Intel - AMD ; J. Weiss 17 Athlon XP (Barton) ~2003 Horloge : MHz Front Side Bus : 166 MHz DDR Cache L2 : 512KB on die. 54,3 millions de transistors Same as Thoroughbred core Athlon XP with an increase L2 cache to 512KB. novembre 03 Microprocesseurs 32 bits Intel - AMD ; J. Weiss 18

Procesadores de Intel Pentium 4

Procesador Procesadores de Intel Pentium 4 Nombre núcleo Reloj GHz FSB MHz edition 3,4G Prescott 3,4 800 90nm 2x1MB Socket 775 edition 3,4G Prescott 3,4 800 90nm 2x1MB Socket 478 edition 3,2G Prescott