Countering Counterfeits of Electronic Components by Insertion of Anti-Counterfeit Technologies into IC Packages

Size: px

Start display at page:

Download "Countering Counterfeits of Electronic Components by Insertion of Anti-Counterfeit Technologies into IC Packages"

Dominick Nichols
7 years ago
Views:

1 Countering Counterfeits of Electronic Components by Insertion of Anti-Counterfeit Technologies into IC Packages Stephanie Pesseguier, STMicroelectronics, Corporate Security

Checking Resistance & Industrialization No impact on electrical parameters, functional behavior, visual aspect and A/T lifetime in line with

2 Inserting an A/C Technology into IC Packages cannot be done without a thorough qualification methodology based on specific requirements: Feasibility Technology appearance: visual acceptance Detection certainty & reliability Potential for industrialization Reliability & Failure Checking Resistance & Industrialization No impact on electrical parameters, functional behavior, visual aspect and A/T lifetime in line with component one No reliability degradation Resistance against attacks: tampering, copy & imitation, alteration Impact on industrialization (process, yield, time)

3 Methodology in a V cycle Requirements Testing Performance Requirements* & feasibility study 1 st level reliability plan 2 nd level reliability & resistance plan Phase 0/1 Phase 2 Phase 3 Feasibility Tests JEDEC reliability Tests (Die & Package) Tests in volume Applicative Tests (Package & application boards) Implementation within * Technology, standalone reader, on-line Automatic reader requirements

Feasibility Tests JEDEC reliability Tests (Die & Package) Tests in volume Applicative Tests (Package

4 Feasibility phase (1/2) Objective: to demonstrate the possible adaptation of the technology into the existing SC production process: Insertion steps trials (molding, pre-curing, post-curing, after laser marking ) to find the most appropriate one Different deposit methods (printing, tampon, plasma torch, laser..) to determine the best adherence and final aspect

pre-curing, post-curing, after laser marking ) to find the most appropriate one Different

5 Feasibility phase (2/2) Component visual aspect and signal intensity/detection at the end of the assembly process Reading correctness & stability: results must be reliable & repeatable

6 Reliability & Failure Checking (1/2) Objectives: to check the A/T lifetime and no induced failure in the device specification through aggressive conditions tests (temperature, humidity, pressure, ): 1 st -level(package level, tests in volume): Assembly in volume: check at each assembly step signal& visual aspect JEDEC standards (stress conditions exposition): up to 260 C (SRT), 100% humidity and 2 bars pressure (ACT), 1000 hours (THBT) o A/C signal and electrical parameters measurement at each test step o Functional tests & Visual Acceptance checking all along the tests cycles

step signal& visual aspect JEDEC standards (stress conditions exposition): up to 260 C (SRT), 100% humidity and 2 bars pressure (ACT), 1000 hours

7 Reliability & Failure Checking (2/2) 2 nd level (board level): Dedicated applicative board design JEDEC standards: mechanical and thermal shocks/stresses: drop test, temperature test, vibration test, Electrical test: daisy chain if available on the product Visual acceptance checking at each test step A/T diffusion measurement Other efficiency tests: adherence (tape test), tests on dedicated boards (side effect check)

Electrical test: daisy chain if available on the product Visual acceptance checking at each test step

8 Resistance (1/2) Objective: to test the technology and authentication tool robustness and resistance against attacks (in line with AFNOR ISO12931 standard), in particular: Resistance against tampering Top surface tampering Resistance against copy & imitation Image analysis

line with AFNOR ISO12931 standard), in particular: Resistance

9 Resistance (2/2) Resistance against alteration Marking alteration Side channel resistance Communication interception (reader) Reverse engineering, simulation and emulation (reader)

10 Industrialization & Technology selection Some industrialization points to consider: New equipment to insert or existing one to adapt On-line automatic reading in production (100% sampling) Efforts estimation (yield impact, additional costs*, fab process, cycle time.) * taggant/technology, tagging equipment, handheld reader, on-line automatic reader The choice of a specific technology depends on: The results of the qualification methodology to determine whether it fits the SC Industry requirements The package size and associated product cost The assembly production line configuration The additional equipment costs It s then a trade-off between technology features and associated costs

) * taggant/technology, tagging equipment, handheld reader, on-line automatic reader The choice of a specific technology depends on: The results of the qualification

Introduction. Development of the AQEC Standard

Introduction. Development of the AQEC Standard Texas Instruments Incorporated Post Office Box 84 Sherman, Texas 75090 6412 Highway 75 South Sherman, Texas 75090 (903) 868-7111 Implementation of Aerospace Qualified Electronic Component Requirements