Reliability Test plan development for electronic components
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1 Reliability Test plan development for electronic components Kees Revenberg Co-founder/MD Reliability Electronics & Automation May 30 th 2013 Croesezaal, Jaarbeurs Utrecht MASER Engineering 1
2 Outline Introduction Test plan development Environments and applications Test methods and standards Execution and data processing Examples Summary MASER Engineering 2
3 Introduction Independent Test & Diagnostics of Microelectronics Services cover component to module & small system level Large IDM, Fabless Semi, Design Centers, OEM and R&D Founded in 1993, ISO-9001 certified by Lloyds Register First RvA ISO accreditation on electronics test (L388) 1750m² central lab & offices at Kennispark Enschede 41 employees with gen/tech/bsc*/msc*/phd* (*=>60%) 4 representing agencies covering Western Europe and Israel MASER Engineering 3
4 Introduction Electronic component penetration ongoing Highly complex product to manufacture Millions/week of devices at sub 100nm precision 100+ devices per system at 100k+/week Strict manufacturing process control Big impact of application environment Unknown customer handling activity Good pro-active test planning is key to success or failure MASER Engineering 4
5 Test plan development Product description Manufacturing Flow and Supply Chain Application Environments and Mission FME(C)A and design robustness analysis Design for tests implementation Test program preparation Organization and Responsibilities Test plan description Customer feedback / approval Test execution h/w and s/w preparation MASER Engineering 5
6 Test plan development Product description Detailed functional description DC/AC parametric specification Package Outline Drawing + pin list Manufacturing Flow and Supply Chain Detailed description of manufacturing process Detailed description of materials and suppliers SPC program definition for process control Definition of quality gates and control MASER Engineering 6
7 Test plan development Application Environments and Mission Definition of worse case End User environment Definition of product mission and expected life FME(C)A and design robustness analysis Product split in all essential blocks and assembly steps List of potential hazards and/or failure modes Consequences of malfunction with grade Prime test methods to show or stress the hazards List of necessary tools and techniques HALT sequence preparation MASER Engineering 7
8 Test plan development Design for tests implementation On chip / On board features for with JTAG/SPI test Support electronics for stress test status monitoring Health monitoring during stress test and operation Test program preparation Organization and Responsibilities Test plan description Standard vs. Custom stress tests Customer feedback / approval Test execution h/w and s/w preparation MASER Engineering 8
9 Environments and applications Application environments has big impact User skills can destroy a product Certain applications may result in life threatening situations Health: pacemaker / narcosis equipment Automotive: airbag / steering control Aerospace: motor control / fly-by-wire There is an uncertainty in the final product application environment and expected life MASER Engineering 9
10 Test methods and standards Detailed description of method and tools Intra lab exchange of results ISO accreditation for test labs ISO IEC MILSTD883/750/202 JEDEC / J-STD JIS EN NEN AEC-Q100/101/200 IPC600/610 Customer based Application based Other MASER Engineering
11 JEDEC test standards Joint Electron Devices Engineering Council Founded in 1958 Part of Electronic Industries Alliance 1999 independent organization JEDEC Solid State Technology Association MASER Engineering
12 JEDEC test standards Detailed test method description Better focus on micro-electronics World Wide acceptance in industry Good correlation with accredited labs Methods and programs defined Joint standards with ESDA and IPC MASER Engineering
13 JEDEC standard JESD47I (07/12) Stress test driven qualification of IC s Required stress test Pass/Fail criteria acc. LTPD table Qualification and Re-qualification after change Device specific tests ESD Latch Up Parametric Device qualification requirements Hermetic package requirement MASER Engineering
14 JEDEC standard JESD47I (07/12) MASER Engineering
15 AEC test standards AEC-Q100-Q101-Q200 Automotive Industry driven 1995 Q100 version A issued Free on J1879 Handbook for Robustness Validation of Semiconductor Devices in Automotive Applications Joint SAE-ZVEI-JSAE-AEC plan Info on AEC-Q100 founders, left to right: Earl Fisher (FORD) Gerald Servais (Delco/GM) Jerry Jennings (Chrysler) Robert Knoell (FORD) MASER Engineering
16 AEC Q100 test standards MASER Engineering
17 AEC Q100 test standards MASER Engineering
18 AEC Q100 test standards Test Group A: Chip + Package related stress THB HAST; PC UHAST; PreConditioning stress prior to GpA tests Power Temperature Cycling for multiple hot/cold starts, linear K-ramp Test Group B: Chip accelerated life test + Safe Launch Functional reliability in an accelerated test environment Due to new operational temperatures temperatures go up to +175 C Test Group C: Assembly related tests Lot by Lot selection for destructive mechanical properties Test Group D: Wafer process related tests Metal and Via structure EM stress Gate Oxide stability TDDB Diffusion / Parametric drift HCI stress MASER Engineering
19 AEC Q100 test standards Test Group E1: Electrical parametric tests Statistical review of DC and AC parameters Test Group E2: Electrical parametric tests ESD/LU phenomena protection circuitry, strong relation to JEDEC/ESDA Dedicated test for CMOS under lightning strike effects FIGL test Test Group F: Design process related tests Review of statistical device data Test Group G: Hermetic package tests Drop, Shock and Vibration stress tests Seal test and Internal Water Vapour Content MASER Engineering
20 J1879 Robustness Validation J1879 Matrix Subsystem Material Failure Mechanism Failure Cause Failure Mode Detection Mode Char. of Degradation Affecting Ops Cond. Required Test structure Mitigation Technique Stress Method Stress Method standard Acceleration Model Acc. Model standard ref. The vertical axis is a list of wide range of potential defects and material behavior: a knowledge based listing, increasing in time MASER Engineering
21 Execution and data processing Representative samples Sample size Fixture / Stress test setup utilities Internal facilities vs External facilities ISO requirements Result reporting Statistics Failure Analysis MASER Engineering
22 Examples MASER Engineering
23 Examples Power Temperature Cycling JEDEC JESD22-A105C 1000 cycles -40 C to +85 C, 6.25K/min, operational, power on/off 1000 cycles -40 C to +125 C, 5.5K/min, operational, power on/off Single chamber, fast cycling system, easy cabling feedthrough MASER Engineering
24 Examples ElectroThermally Induced Parasitic Gate Leakage test AEC-Q100 testmethod 006 High Voltage arcing field during board assembly 12kV inducing 400V at device HV Power on at +155 C Fast decline to +100 C and HV power off MASER Engineering
25 Summary Good device and process knowledge is essential for a successful test plan FMEA and application review can help to optimize the test plan Use of standard test methods makes intra lab execution valuable Good DfX can bring great saving in costs A good test plan is the basis for profit MASER Engineering
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