Application Note. 8-bit Microcontrollers. AVR495: AC Induction Motor Control Using the Constant V/f Principle and a Space-vector PWM Algorithm

Transcription

1 AVR495: AC Induction Motor Control Uing the Contant V/f Principle and a Space-vector PWM Algorithm Feature Cot-effective and energy efficient -phae induction motor drive Interrupt driven Low memory and computing requirement 8-bit Microcontroller 1. Introduction In a previou application note [AVR494], the implementation on an AT9PWM of an induction motor peed control loop uing the contant Volt per Hertz principle and a natural pule-width modulation (PWM) technique wa decribed. A more ophiticated approach uing a pace vector PWM intead of the natural PWM technique i known to provide lower energy conumption and improved tranient repone. The aim of thi application note i to how that thi approach, though more computationally intenive, can alo be implemented on an AT9PWM. 2. AT9PWM Key Feature The control algorithm have been implemented on the AT9PWM, a low-cot lowpower ingle-chip microcontroller, achieving up to 16 MIPS and uitable for the control of DC-DC buck-boot converter, permanent magnet ynchronou machine, threephae induction motor and bruhle DC motor. Thi device integrate: 8-bit AVR advanced RISC architecture microcontroller (core imilar to the ATmega 88) 8K Byte of In-Sytem-Programmable Flah memory 512 Byte of tatic RAM to tore variable and lookup table dedicated to the application program 512 byte of EEPROM to tore configuration data and look-up table one 8-bit timer and one 16-bit timer 6 PWM channel optimized for Half-Bridge Power Control an 11-channel 1-bit ADC and a 1-bit DAC on-chip comparator a programmable watchdog timer with an internal ocillator

2 . Theory of Operation.1 Principle of the Space-Vector Modulation Figure -1. Typical tructure of an inverter-fed induction motor. Figure -1.how the typical tructure of a three-phae induction motor connected to a VSI (Voltage Source Inverter). Since the motor i conidered a a balanced load with an unconnected neutral, V n = V a + V b + V c, V ( ) / an = Va Vn = V V, V = V V = ( V V ) / ab ca bn b n bc ab and Vcn = Vc Vn = ( Vca Vbc ) /. Since the upper power witche can only be On or Off, and ince the lower one are uppoed to alway be in the oppoed tate (the dead-time of the inverter leg are neglected), there are only eight poible witching tate, a hown on Figure -2. Six of them lead to non-zero phae voltage, and two interchangeable tate lead to zero phae voltage. When mapped in a 2D-frame fixed to the tator uing a Concordia tranformation [1,2], the ix non-zero phae voltage form the vertice of a hexagon. (See Figure -.) Vα V β = 1 1/ 2 / 2 1/ 2 / 2 V V V an bn cn Figure -2. Poible witching configuration of a -phae inverter 2

3 A hown on Figure -., the angle between two ucceive non-zero voltage i alway 6 degree. j( k 1) In complex form, thee non-zero phae voltage can be written a Vk = E e, with k = 1..6 and V V. Table -1. how the line-to-line and line-to-neutral voltage in each of the 8 poible configuration of the = V7 = inverter. Figure -. Repreentation of the eight poible witching configuration in the Concordia reference frame Table -1. Switching configuration and output voltage of a -phae inverter S a+ S b+ S c+ S i V ab V bc V ca V an V bn V cn V α V β V i S V 1 S 1 -E E -E/ -E/ +2E/ -E/2 E 2 V 5 1 S 2 -E E -E/ +2E/ -E/ -E/2 E 2 V 1 1 S -E E -2E/ -E/ -E/ -E V 4 1 S 4 E -E +2E/ -E/ -E/ E V S 5 E -E E/ -2E/ E/ E/2 E 2 V S 6 E -E E/ E/ -2E/ E/2 E 2 V S 7 V 7

4 Table -2. Expreion of the duty cycle in each ector In the Concordia frame, any tator voltage V = Vα + jvβ = Vm co( θ ) + jvm in( θ ) located inide thi hexagon belong to one of the ix ector, and can be expreed a a linear combination of the two non-zero phae voltage which delimit thi ector: V = d V + d k k k+1 Vk +1. Equating d V + d to in each ector lead to the expreion of the duty +1 V V co( θ ) + jv in( θ ) k k k k+1 m m cycle hown in Table -2. Since the inverter cannot intantaneouly generate V, the pacevector PWM principle conit in producing a T -periodic voltage whoe average value equal V,by generating V k during T = d T and V during. Since, thee k k k + T 1 k + = 1 d k + T d k d k +1 voltage mut be completed over the witching period T by V and/or V7. Several olution are poible [,4], and the one which minimize the total harmonic ditorion of the tator current 1 dk dk + 1 conit in applying V and V T = T7 = T 7 during the ame duration 2. V i equally applied at the beginning and at the end of the witching period, wherea V 7 i applied at the middle. A an illutration, the upper ide of Figure -4. how the waveform obtained in ector 1. 4

5 .2 Efficient Implementation of the SV-PWM Table -2. eem to how that the duty cycle have different expreion in each ector. A thorough tudy of thee expreion how that ince in( x) = in( x), all thee duty cycle can be 2V written in a unified way a = m 2V dk in( θ ) and 1 = m dk + in( θ ), with θ = θ and θ = θ ( k E 1). Since thee expreion no longer depend on the ector number, they can be denoted a d and d. Since i alway between and, computing and require a a b θ d d a b ine table for angle inide thi interval only. Thi greatly reduce the amount of memory required to tore thi ine table. The AT9PWM provide the power tage controller (PSC) to generate the witching waveform computed from the Space Vector algorythm. The counter will count from zero to a value correponding to one half of the witching period (a hown on the lower ide of Fig. 4), and then count down to zero. The value that mut be tored in the three compare regiter are given in Table -. E Figure -4. Inverter witch waveform and correponding compare regiter value 5

6 Table -. Compare Regiter Value v Sector Number. Sector Determination Algorithm To determine the ector which a given tator voltage V belong to, ome algorithm have been propoed in the literature which generally require many arithmetic operation and are baed on the coordinate of V in the Concordia plane or in the a-b-c phae pace. When thi voltage i deduced from a V/f control principle, it modulu V m i computed by the V/f law recalled in the previou application note, and it phae θ i deduced from ω by a dicrete-time integrator. To implement thi ector determination algorithm efficiently, we manage θ and k intead of θ in a dedicated integrator hown on Fig. 6. The ector number k i the output of a modulo ix counter activated each time θ exceed, and θ i confined to lie between and (ee Fig. 7). Figure -5. Sector determination algorithm 6

7 Figure -6. Sector determination The reulting dataflow diagram, hown on Fig. 8, can be ued to build a peed control loop (Figure -8.), in which the difference between the deired peed and the meaured peed feed a PI controller that determine the tator voltage frequency. To decreae the complexity of the controller, the input of the V/f law and of the pace vector PWM algorithm i the abolute value of the tator voltage frequency. If the output of the PI controller i a negative number, two of the witching variable driving the power tranitor of the inverter are interchanged. Figure -7. Space Vector PWM data flow diagram 7

8 Figure -8. Block diagram of the complete control ytem. 4. Hardware Decription (ATAVRMC2) Thi application i available on the ATAVRMC2 evaluation board. Thi board provide a way to tart and experiment aynchronou motor control. ATAVRMC2 main feature: AT9PWM microcontroller 11-2VAC motor drive Intelligent Power Module (2V / 4W board ized) ISP & Emulator interface RS22 interface Iolated I/O for enor -1V input for command or enor 5. Software Decription All algorithm have been written in the C language uing IAR' embedded workbench and AVR Studio a development tool. For the pace vector PWM algorithm, a table of the rounded 2k 127 in( ) value of for k between and 8 i ued. The length of thi table (81 byte) i a 48 better trade-off between the ize of the available internal memory and the quantification of the rotor haft peed. For bi-directional peed control, the value tored in two of the comparator are interchanged when the output of the PI regulator i a negative number (ee Figure -8.). 5.1 Project Decription The oftware i available in the attached project on the Atmel web Site. The project to ue i Project_Vector. The Project_Natural correpond to the AVR494. 8

9 Table 5-1. Lit of File ued in the Project_Vector.IAR project. File main_pace_vector_pwm.c pace_vector_pwm2.c controlvf.c mc_control.c read_acquiitionadc.c init.c pc_initialiation2.c adc.c dac.c Decription main upper level of the application ector and theta determination Compute a contant V/F ratio regulation loop (PI) return the ADC reult CPU initialization (IO port, timer) PSC initialization ADC function DAC function 5.2 Experimentation Figure 5-1. how the peed repone and the tator voltage obtained with the microcontroller for peed reference tep between +7 and -7 rpm. Thee experimental reult were obtained with a 75 W induction machine. Thi figure how that the deired peed i reached after a 1.2 long tranient, and that when the tator frequency ω obtained at the output of the PI regulator near zero, the tator voltage magnitude i equal to the boot voltage. Thee figure alo confirm that tranient obtained with a a pace vector PWM i moother but alo longer. Figure 5-1. Meaured peed (in rpm) and line-to-neutral tator voltage (in Volt) obtained with the microcontroller during peed reference tep (a) peed [rpm] tator voltage [V] tator voltage [V] (b) (c) time [] 6. Reource Code Size : byte RAM Size : 217 byte 9

10 CPU Load : 8MHz 7. Reference 1. Atmel AVR494, AC Induction Motor Control Uing the contant V/f Principle and a Natural PWM Algorithm. 2. W. Leonhard, Control of electrical drive, 2 nd Ed, Springer, F.A. Toliyat, S.G. Campbell, DSP-baed electromechanical motion control, CRC Pre, Y.Y. Tzou, H.J. Hu, FPGA realiation of pace-vector PWM control IC for three-phae PWM inverter, IEEE Tranaction on Power Electronic, Vol 12, No 6, pp 95-96, K. Zhou, D. Wang, Relation between pace-vector modulation and three-phae carrier-baed PWM, IEEE Tranaction on Indutrial Electronic, Vol. 49, No. 1, pp , February 22. 1

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