DDR Validation Tool User Guide

Transcription

1 DDR Validation Tool User Guide Document Number: QCVSDDRVUG Rev 4.2, 03/2015

2 2 Freescale Semiconductor, Inc.

3 Contents Section number Title Page Chapter 1 DDR Validation Tool 1.1 Installing DDR Validation Tool Using DDR Validation Tool Creating QorIQ Configuration project Starting DDR Validation Tool Target connection setup Remote configuration setup Running DDR Validation tool Test scenarios Configure tests parameters View and interpret DDR Validation results Restore DDR configuration to default Reporting validation tests Read from SPD Customize Validation code DDR Validation Scenarios Read and write data bus margin Licensing Frequently asked questions (FAQ) Freescale Semiconductor, Inc. 3

4 4 Freescale Semiconductor, Inc.

5 Chapter 1 DDR Validation Tool This document introduces the DDR validation (DDRv) tool and describes how to read from target, validate, and optimize a DDR configuration on Freescale QorIQ devices. The document describes the details of how to go from DDR specifications up to an optimized DDR configuration using different validation methods. The DDRv tool is a software component of the QorIQ Configuration and Validation Suite (QCVS) product. Its purpose is to validate a DDR configuration or read from a memory dump or target. The validation process is performed in stages, by gradually refinement of an initial DDR configuration up to an optimized settings. Each validation step is responsible with the verification and optimization of specific DDR parameters. The outcome of a validation stage represents the input of the next one, thus gradually refining the DDR settings. You can intervene in the validation stages and decide whether to include or skip a stage depending on which DDR settings are important to optimize. DDRv is built as a multitier software comprised of an Eclipse based UI, a validation service which can be used from a remote location and a target connection layer. The Eclipse user interface enables you to configure, control, and monitor the DDR validation process as well as view and interpret the results. The validation service allows to run DDR validation on a target whether directly accessible through a target probe or indirectly through a remote PC. The connectivity layer facilitates the communication with the target using Common Debug Development Environment (CDDE). CDDE is a software package working on the top of CodeWarrior Connection Server (CCS) which enables target operation via Python scripting. CDDE and CCS packages are bundled into the QCVS layout. They are also distributed with CodeWarrior for Power Architectures and ARM v7 products. This chapter explains: Installing DDR Validation Tool Using DDR Validation Tool DDR Validation Scenarios Freescale Semiconductor, Inc. 5

6 Installing DDR Validation Tool Licensing Frequently asked questions (FAQ) 1.1 Installing DDR Validation Tool You can install the DDRv tool using the Eclipse Updater. The DDRv tool is a licensebased, without a valid license file you will be able to install the DDRv tool, but will not be able to use the tool. For details on installation of DDRv tool, see DDRv_Installation_Guide.pdf file and for licensing, see Licensing section. 1.2 Using DDR Validation Tool The DDRv tool is a software component installed on top of the QCS tool. The configuration of DDR component is refined by validating it using a step by step approach. Creating QorIQ Configuration project Starting DDR Validation Tool Target connection setup Remote configuration setup Running DDR Validation tool Creating QorIQ Configuration project Perform the following steps to create a QorIQ Configuration project: 1. Launch QCVS. 2. Select File > New > QorIQ Configuration Project. The New QorIQ Configuration Project wizard appears. 3. Enter the project name and click Next. The Devices page appears. 4. Select the required processor and also choose a silicon revision and click Next. The Toolset selection page appears. 6 Freescale Semiconductor, Inc.

7 Chapter 1 DDR Validation Tool Figure 1-1. Toolset selection page 5. Select DDR Memory Controller Configuration option from the Components list and click Next. The DDR Configuration page appears. Freescale Semiconductor, Inc. 7

8 Using DDR Validation Tool Figure 1-2. DDR Configuration page 6. There are several options to configure a DDR component: Auto configuration - it is the default DDR setting. Some important elements such as Data Rate, CAS Latency can be modified from the wizard page. Import from memory file - several memory dump formats are supported. Other settings of the dump content such as endianness are configurable. Read from SPD - allow reading of vendor tested DDR parameters from the DIMM attached EEPROM. This is applicable only in case DIMMs are used. For more details, see Read from SPD section. 8 Freescale Semiconductor, Inc.

9 7. In case DIMMs are used, the best approach is to select Read from SPD option. SPD contains vendor tested DDR parameter ranges from which one can choose from. Once read, they are displayed and you can choose from the available values. Reading from SPD connection to target, user input is required for probe type and connection id and then click the READ SPD link. NOTE Not all parameters read from SPD are displayed on wizard. In case, a valid DDRv license is not found, the Read from SPD option is hidden. 8. Specify the settings according to the requirements. For example, you can either setup basic DDR parameters, import a DDR configuration from a memory dump, or load an existing preset DDR configuration (available within the QCVS product). In this screen, you can configure one DDR controller or all DDR controllers depending on the selected device. 9. The best way to setup the DDR parameters would be reading of SPD information. In the Configuration mode, select Read from SPD option. This option allows to read some of the basic parameters recommended by the DDR vendor. In the Configuration mode, select Read from SPD option. 10. In Skew box, the default clocks are necessary to determine, Write leveling start time from DQS[0:8]. You can enter the strobe to clock trace length skews for each byte lane for their board. 11. Click Finish to complete the project creation. The created project appears in the Project Explorer view. NOTE SPD information should be used only for the boards that have DRAM modules, but not for Discrete DRAM implementation. In case SPD could not be read or not present, an information message is displayed on the wizard. Chapter 1 DDR Validation Tool Freescale Semiconductor, Inc. 9

10 Using DDR Validation Tool Figure 1-3. Project Explorer view Starting DDR Validation Tool To validate DDR using an existing QCS project that has no DDR component, add a new DDR component to the project using the component wizard. To start the DDRv tool: 1. In the Components view, expand the Embedded Components folder. 2. Select the DDR component under the Embedded Components folder. The DDR Component Inspector view appears in the right side of the screen. This view displays a dedicated panel for the DDR Validation as shown in the figure below. 3. Click on the Validation page in order to display the DDR Validation panel. 10 Freescale Semiconductor, Inc.

11 Chapter 1 DDR Validation Tool Figure 1-4. Validation view NOTE To open the DDR component in the Components Inspector view, in the Components view, select the Inspector option from the context menu. DDRv is a licensed product, therefore requires a valid license. In case a valid license is not found, the content of the Validation page from the DDR Component Inspector is replaced by an information page about the license error. Freescale Semiconductor, Inc. 11

12 Using DDR Validation Tool Figure 1-5. Validation view - Licence error So, the next step is to do the following: Get a new license. Use the provided link to go to the appropriate web page and request for a license. Apply an existing license. Select the Browse button, choose the license and apply it. You are informed about the automatic restart that is required. The detailed description of each section of the Validation view: 1. Validation scenarios - the predefined DDR Validation scenarios are grouped into panels. A scenario represents a method of testing DDR. A scenario takes a DDR configuration as input, applies changes to it, verifies it and then provides an optimal DDR configuration. A particular case is the Operational DDR tests, which takes the newly created DDR configuration as input and verifies it against several tests without applying any changes on it. The scenarios are grouped into two stages: Validation and Margins. You have the option to choose the scenarios that you want to run. At least, one scenario should be selected. If multiple scenarios are selected, they will run in the sequential order, output of each scenario represents the input for the next scenario. While running, each scenario performs changes to the input DDR configuration. 12 Freescale Semiconductor, Inc.

13 Chapter 1 DDR Validation Tool Changes mean programming the DDR controller memory mapped registers with a different set of values. Each change of the input represents a new DDR configuration which is tested against a set of tests. Therefore, a scenario checks a range of DDR configurations using an iterative approach. During the iterations, different other DDR settings are adjusted. Following the last iteration, an optimal DDR configuration is determined. The optimal DDR configuration represents the input for the next scenario. 2. Test configuration panel - each scenario is performing a set of tests. During each iteration of scenario, the following operations take place: a. the DDR block is configured with a DDR configuration corresponding to that iteration (that is derived from the scenario's input). b. several test are run checking the read and write reliability of the DDR block. c. test that pass or fail are marked appropriately with colors (color code described further in the document). DDRv provides several predefined tests, some of them are configurable. In order to have optimal DDR configuration, for each scenario, a test could be run multiple times. You can choose and configure the tests that you want to run by selecting from the Choose Tests page. You can add your own tests using Add custom test button located in the right upper side of the tests list. When you add a new test to the list, a default test is created using a template that you have to fill in with your own DDR testing code. The code has to be written in Python syntax. You can remove or rename the user-defined tests using a context menu of each test. Any test from the list can be seen by double-clicking on it. The test content is displayed in a new window. Thus, you can modify the test content and also see the DDR default test scripts. 3. Scenario results panel - This is located in the center of the Validation view inside the Test results page. It is organized into two sections: high level summary and detailed summary. The high level summary is organized into one or more tables that shows the following: all the variations of the scenario's input DDR configuration. Each input derivative is abstracted as a cell. the validation progress while it is running A variation table is a visual representation of how the input DDR configuration for a scenario varies while the scenario runs. The validation progress is displayed using colors and numbers decoded as follows: the current cell that is being tested flashes Freescale Semiconductor, Inc. 13

14 Using DDR Validation Tool the cells, which are being validated displays the number in fraction. The numerator represents how many tests have passed, while the denominator represents how many tests were run for that cell each cell is colored differently when the validation ends. The color depicts the validation results: in green (all tests passed), orange (some tests failed), white (all tests failed), gold (optimal configuration) The color code helps in visualizing the results of the executed scenario. The detailed summary displays the information about each cell organized into three pages: Summary: contains the changed DDR register as compared to the scenarios's input DDR configuration; the detailed status for each test run (passed, failed, queued are displayed when tests are running); the DDR error register values. Logs: contains the execution log for each test iteration. This is redirected from CDDE log. Scripts: contains the exact Python scripts that were executed using CDDE on target. The scripts can be opened in a separate editor by clicking Open in editor button located in the upper right side of the Scripts page. The high level and detailed scenario execution summary is available during and after the scenario has executed. The information is updated as the scenario execution progresses. 4. Target connection panel: DDR validation requires access to target. The target connection defines how the connection is being made, the type of probe and the connection provider software whether the target is local or remote. Local refers to a target that is connected using a probe to the user's PC. Remote represents a target that is not directly visible from user's PC (for example, several boards connected to a remote lab PC using USB TAP, or target connected to an IP of ETAP). In order to setup the target connection, click the Target Connection button that allows the target to get connected to PC and also searches for the connection provider (CDDE or GDB). For mor details, see Target connection setup section. After setting the target connection, the connection will appear in the combo box located above the Target Connections button. Notice that several connections can be defined at the same time. You can choose any of the target connections by selecting it from the available list. When you will select a connection, the system will test it to determine if it is alive, otherwise, you will be notified. NOTE A working target connection is mandatory in order to run DDR validation. The Start Validation button is disabled unless all the validation preconditions are met. The tooltip displays that preconditions are not yet met. 14 Freescale Semiconductor, Inc.

15 Chapter 1 DDR Validation Tool 5. Validation control panel: You can control the validation process in order to start, stop, pause or resume it. This is performed by two buttons, Start Validation and Pause that are present above the target connection panel Target connection setup The DDR validation uses a client server architecture to allow validation on both local and remote systems. If you have a target board connected (by USBTAP or ETAP) directly to your PC, you can validate it locally. Validation on the local system is default. DDRv tool requires a working target connection. Also, it requires a target connection provider (either CDDE or GDB both bundled into QCVS layout) which facilitates the connection with target. With a new DDR project, a default target connection is created having a USB TAP probe with empty connection string. The Read from SPD option requires a probe and a connection string. A target connection is created for reading from SPD and the DIMM vendor parameters. You can change any of the target connection attributes: name, device, target connection provider, probe and connection string. In most cases, you will have to change only the probe type and connection string to match the hardware setup. In order to setup (edit, create new or delete) a target connection, click the Target Connections... button. Figure 1-6. Target connection setup screen The Hardware Configuration Manager dialog (shown below) allows you to define a connection name, target device to which the connection is to be established and also which probe (USBTAP, ETAP, GTAP, CWTAP) to be used. Depending on the probe that you have selected, you will have to fill in the appropriate connection string (for example, USB TAP id for USB TAP, IP address for ETAP, IP address and Tag for GTAP, USB TAP id or IP address for CW TAP). Freescale Semiconductor, Inc. 15

16 Using DDR Validation Tool You can add, edit or delete a connection using the New, Edit, and Delete buttons. The Refresh button will check all the existing target connections in order to determine if they are active. In the Hardware Configuration Manager window, you can choose to use a different target connection provider (CDDE or GDB). The target connection provider are provided in the QCVS layout and are chosen automatically. However, you are able to point to a different CDDE or GDB. Figure 1-7. Hardware Configuration Manager dialog In order to setup a remote connection, you have to do the following steps: Click the Harware accessible from list box to switch from localhost to remote. Enter the IP address of the remote PC to which the target is connected. Click Connect. Figure 1-8. Setup remote connection screen 16 Freescale Semiconductor, Inc.

17 After defining all the connections that you want to use, click the Close button so that you can choose one of the target connection. All the defined target connections will be available into the combo box above the Target Connections button. In order to choose a connection to work with, do the following steps: Choose one of the available target connection from the combo box. Chapter 1 DDR Validation Tool Figure 1-9. List of available connections screen When a target connection is created or modified, it is checked for responsiveness. This happens either when closing the Hardware Configuration Manager window or selecting a connection from the combo list. Depending on the result of verification of the connection, the connection combo list is displayed with a different icon and tooltip. Figure Network connection Figure Connection problem Freescale Semiconductor, Inc. 17

18 Using DDR Validation Tool Remote configuration setup DDRv allows you to connect to a remote target which is neither directly connected to user's PC nor accessible using a remote probe such as ETAP, GTAP, CW TAP. This capability allows validation of a DDR configuration defined on user's PC, onto a target which is connected to another PC with an IP visible from user's PC (for example, you have DDRv installed on your PC and would like to connect to a remote target which is connected using USB TAP to a PC which you can access using IP). The following steps should be performed in order to validate DDR as described above: Install CDDE service on the remote machine to which the target is connected. CDDE is included in the installation layout of CodeWarrior for Power Architecture in the <CW_INSTALLATION_DIR>\PA\cdde folder. From the local machine where DDRv is installed, copy <INSTALL_DIR>\eclipse \Optimization\remote-service and <INSTALL_DIR>\eclipse\Optimization\target-connection folders on the remote machine. This represents the binaries of the connection management process required for running DDRv. Start the connection management process by double-clicking the com.freescale.processorexpert.validation.service_<plugin_version>.jar file. This file is present in the DDRv installation layout in the <DDRV_Installation_DIR>\eclipse \Optimization\remote-service folder. An icon appears in the taskbar that indicates that the Connection Manager is up and running. Figure Connection Manager icon While using remote setup, you will have to enter the IP of the PC to which the target is connected (see Target connection setup section) Running DDR Validation tool When one or more test scenarios are selected, then you can start the validation of the DDR component. Before running the DDR validation, you can configure several validation parameters such as: 18 Freescale Semiconductor, Inc.

19 which elements of the validation to run; what DDR specific tests to run. how thorough to perform the validation. Select the Choose validation mode combo box to do either full validation or to select a more optimized validation in terms of speed (Custom option from the combo box) This sections explains: Test scenarios Configure tests parameters View and interpret DDR Validation results Restore DDR configuration to default Reporting validation tests Read from SPD Chapter 1 DDR Validation Tool Test scenarios DDR validation uses various testing scenarios. Each scenario represents how a DDR configuration is varied into a set of derived DDR configurations. Each of those derived DDR configuration are then tested with a set of predefined tests. You can choose which scenarios to be tested by selecting them from the available list (shown below). Figure List of scenarios screen Each scenario's variation of DDR configuration is displayed as a table that describes which parameters and how they are varied (shown below). One variation parameter (name and value) is represented on the rows while the other on the columns. Each cell of the table represents one of the DDR configuration variations, where row and column correspond to the two varied parameters. You can choose one of the DDR parameter to be tested using three icons on the table panel: choose none, all or an area. This option is useful when you target a quick test of a specific variation without waiting for the full set to be tested. Freescale Semiconductor, Inc. 19

20 Using DDR Validation Tool Figure List of tests screen When multiple scenarios are selected, by default, the tool run them one after the other. This behavior can be (de)activated using the Continuous validation option. After each scenario completes, you will have to manually move to the next scenario by clicking the Next button. This is the same button as the Start Validation, but with its text changed. Figure List of tests screen 20 Freescale Semiconductor, Inc.

21 Chapter 1 DDR Validation Tool For each scenario, a set of tests can be run, you have the choice to define which tests and how many times to run the same test. You can also add new custom tests to a scenario using the Add icon. To rename or remove a custom test, right-click on it and select Rename or Remove option Configure tests parameters You can configure some of the tests, such as Read Write Compare, Walking Ones or Walking Zeros. When you select a test on the left side, a configuration panel appears on the right side of the test. You can set the parameters such as start address, size of the DDR, and end address that is the memory area that need to be tested or pattern to be used. Figure Configuring test parameters A custom test represents a template which you have to fill with your own DDR validation logic. The validation process consists of the following: 1. You cannot start the validation even if you have selected a target connection, scenarios, tests and validation mode, and clicked the Start Validation button unless you have completed the following steps: Freescale Semiconductor, Inc. 21

22 Using DDR Validation Tool a valid target connection is chosen a validation scenario is selected from the list NOTE In case the DDR Configuration has errors, the validation cannot run and the Validation tab will be marked with a red x. 2. The DDR configuration project represents the input to the first selected scenario. 3. The scenario performs variations on its DDR configuration input, each variation is tested with the tests chosen by you. 4. After all the cells (a derived DDR configuration) are tested and the cells that have passed all the tests, the optimal cell is chosen (for example, middle of the green area). This optimal configuration represents the input for the next scenario. 5. You can overwrite the optimal DDR configuration by right-clicking on a cell that passed all tests. 6. To move to another scenario, click the Next Scenario button. It is a toggle button which changes its caption when a scenario execution is finished. To pause or resume the execution of a scenario, click Start Validation. Click Cancel button to cancel or restart the execution of a scenario. Both are the toggle buttons and their captions are changed depending on user interaction and progress of the validation View and interpret DDR Validation results The validation produces different levels of logs that can be seen during the validation process. The information displayed by the validation is: For each DDR configuration, the testing results are displayed in different color codes. If the color code is: Green all tests are passed Orange some tests are passed White all tests are failed or could not run due to the incorrect DDR configuration Gold optimal cell Each color code is explained in a legend. You can place the mouse over each colored square to see what each color code means. 22 Freescale Semiconductor, Inc.

23 Chapter 1 DDR Validation Tool Figure Displaying test results Detailed information for each cell is explained in the summary, logs and scripts pages. Summary a brief description of the DDR configuration changes, execution result and DDR error registers, corresponding to the cell Logs the log messages are generated after test execution Scripts the validation script run on target NOTE Most of the test run on the device cores for speed purposes. The Scripts tab contains mostly the control part of the test rather than the actual test which is a binary application Restore DDR configuration to default The initial DDR configuration is modified while DDR validation is running. In order to restart the validation with initial DDR configuration, click on an icon (as shown below) to switch to default. The icon is disabled during the validation process. Freescale Semiconductor, Inc. 23

24 Using DDR Validation Tool Figure Restoring DDR configuration Restoring DDR configuration to initial value is useful when you have to run the validation again. Running the validation again on the same initial configuration requires either import/export operation or is restored to default. While the import has to be performed before the first validation is run, the restore to default can be used at any time needed Reporting validation tests After or during the validation, there is an option to save the validation results for a scenario in a format, such as PDF, XLS or CSV. In order to print the results in a format, use the action buttons as shown in figure below. Figure Validation test In addition, you can setup a reporting job to auto-generate reports at different events, such as scenario completion or periodically after some time. 24 Freescale Semiconductor, Inc.

25 Chapter 1 DDR Validation Tool Figure Auto-generate DDRv Report The report is generated periodically with all the validation that is executed until that time. Do the setup before running the validation. Figure On demand report Read from SPD Read from SPD is an option of configuring the DDR according to the DIMM vendor recommendation. This option allows to configure and takes less time for determining an optimized DDR configuration. The steps to configure DDR are as follows: 1. Select an update package from the Configure drop-down list. 2. Select the Configuration mode as Read from SPD. Freescale Semiconductor, Inc. 25

26 Using DDR Validation Tool Figure Read from SPD 3. Select the debug device from the Probe drop-down list. Type the probe Id or IP address in the text box. 4. Click the Read SPD link. In the text box, it will be displayed if SPD is read successfully or not. Disabled parameters are read from SPD. 5. Click Finish. This button will be enabled if SPD is read successfully. In addition, you can setup a reporting job to auto-generate reports at different events, such as scenario completion or periodically after some time. 26 Freescale Semiconductor, Inc.

27 Chapter 1 DDR Validation Tool Figure Auto-generate DDRv Report The report is generated periodically with all the validation that has been executed until that time. Do the setup before running the validation. Figure On demand report Customize Validation code DDR Validation communicates with the target using CDDE. The actual communication is facilitated by Python extensions build on top of CDDE which allow to execute target operations by means of Python scripting. Freescale Semiconductor, Inc. 27

28 DDR Validation Scenarios The DDR Validation tests run as applications on the device cores, therefore, their customization is hidden. However, the pre and post validation operations (for example, target reset, apply of the DDR configuration, clearing the error debug registers) can be customized as they are written in Python. Such customization could take the form of additional operations required at reset. In case such customizations (for example, do a RCW override operation before target reset happens) are needed, you have the option to adjust the code provided by DDR Validation. The python scripts used by DDRv are located at: <INSTALL_DIR> \Optimization\resources\QorIQ\DDR\templates\init\ folder. At the time of customization, it requires a basic understanding of the target operations which are exposed via Python extensions (for example, memory/registers read, write, target reset, etc). For details, see <INSTALL_DIR>\Optimization\docs \PythonScripting.html file. 1.3 DDR Validation Scenarios This is also one of the validation scenario that is provided by QCVS. This section describes some of the DDR validation scenarios that are provided by QCVS. Some of them are easy to grasp while others are complex. Read and write data bus margin Read and write data bus margin The flow of the operations followed during the validation process are: 1. The read or write margin validation scenario allows the memory controller to complete its normal initialization process and perform the normal operation. 2. The timing location of each strobe corresponding to its data byte lane (golden value) is stored. 3. The scenario sweeps the strobe signal in the data eye for each byte lane, using small timing steps. At each timing step during the sweep: Randomly generated data is transferred via DMA engine from one memory space in DDR to another and values at the destination are compared with generated data to determine pass or fail. 28 Freescale Semiconductor, Inc.

29 When the DMA test is passed, the corresponding cell/step is marked as pass and displayed as green cells in the generated margin table. When an error is detected, the cell is marked as fail and displayed as white cells in the margin table. 4. After all data byte lanes have gone through this process and determined the pass or fail, the location of strobe where memory controller was selected during its initialization process, golden value is added to the margin table. NOTE Not all QorIQ families support this feature. If the scenarios described here are not visible in the GUI, then the DDR controller in the processor you are working with doesn t support this feature, the support has not yet been added to QCVS for these scenarios for that particular processor. The QorIQ processors (B4/G4/T) were the first ones to support this feature. Chapter 1 DDR Validation Tool Every time the read or write margin test is run, the memory controller is initialized at the start. The resulting display is a reconstructed margin data eye, including the strobe signal crossing location within the data eye. A simple visual inspection of location of strobe with the reconstructed margin data eye will show the number timing steps before a failure could occur. Freescale Semiconductor, Inc. 29

30 Licensing Figure Interpretation of results of a read or write margins scenario NOTE For additional details about the margin scenarios, see Frequently asked questions (FAQ) section. 1.4 Licensing The DDR Validation tool is a licensed software. To use it, a valid license (license.dat file) should be copied into the <INSTALL_DIR>\eclipse\ProcessorExpert\ folder. In case no valid license is found, you get notification into the Validation page of the DDR Component Inspector view. It also guides you to the website from where a license can be purchased. In case you have a license, the Apply button from Validation page of the DDR Component Inspector is used in order to apply for the license. 1.5 Frequently asked questions (FAQ) Q1. What information do the green cells in read/write margin table provide? 30 Freescale Semiconductor, Inc.

31 A1. These are the cells that have passed the test. The validation sweeps the strobe signal in the data eye for each byte lane and at each timing step during the sweep, a stress DMA test is conducted to check for pass or fail. When the DMA test is passed, the corresponding cell/timing step is marked green. Q2. What information do the golden cells in the margin table provide? A 2. The golden cell is where the memory controller has placed the strobe signal crossing to sample the data during the initialization Q3.What is the difference between data eye and margin table? A3. A data eye is an eye shape pattern generated by setting an oscilloscope to infinitepersistent display mode and DQ signal is captured while DQ value is changed from 1 to 0 and from 0 to 1 repeated for a period of time. The scope is usually triggered on the strobe signal (DQS) indicating where the sampling of DQ takes place within the data eye. A scope captured data eye cannot identified the passing or failing regions within the data eye. The read or write margin table is the pass/fail based reconstruction of data eye with the location of strobe selected by memory controller during the initialization. The margin table identifies the passing or failing regions within the data eye of the DDR interface. Q4. What are the limitations of data eye captured by an oscilloscope? A4. A scope data eye does not have any pass or fail information. The best scope capture is at the pin of the DRAM or memory controller which is still considered as middle of the data bus transmission bus. With data rates exceeding GHz, the complexity of nonintrusive measurement becomes impossible. The equipment is costly and it can measure limited number of signals. It is time consuming to setup and capture meaningful data. Q5.What are the advantages of using the read/write margin validation scenario? A5.Running a margin scenario provides the pass and fail information of data bus. It reconstructs the pseudo data eye to the true end of the transmission line. It is simple to setup. It is very inexpensive and it provides meaningful information about the DDR interface very quickly with minimum setup. Q6. Are the margin tables same as the setup and hold timing parameter for memory controller? A6. No, the margin table displays the passing and failing regions within the data eye in the DDR interface. The passing region has satisfied the required setup and hold time for all components of DDR interface, including the setup and hold the time for memory controller, DRAM, and degradation of the board. Q7. Why and when margin table is useful? Chapter 1 DDR Validation Tool Freescale Semiconductor, Inc. 31

32 Frequently asked questions (FAQ) A7. Functionality of DDR interface is the first step for any DDR interface design. When there is a functional DDR interface, you would like to know how much timing margin are available before the DDR interface would begin to fail. A functional DDR interface with zero timing margin would be more susceptible to failure at some point during its operation. Q8. How much margin is good or acceptable? A8. The more timing margin is available the more stable the interface would be. But one or two green/passing timing steps on both sides of selected strobe location (the golden cell) is considered as good or acceptable. Q9. Why is the controller selected strobe location not in the middle of passing region? A9. The controller determines the best possible strobe location during the initialization. The test conducted by software and controller differ, hence the strobe location may not always fall exactly in the middle of the passing region determined by software means. Q10. The location of strobe is not in the center of passing region, can I manually move it to center? A10. No, manual selection of strobe location is not available. This is because a fixed setting that seems to be ideal setting cannot change and adapt itself to each individual board conditions or variations. Whereas, the controller auto calibration will take place on each individual board and it has an auto tracking capability to adjust itself as board conditions vary during operation. Therefore, the location of strobe selected by the memory controller is not ideal in the margin table, it is considered to be much better than manual selection. Q11. The result I get after running the margin scenario shows that I have a very low passing margin. Is it because of a bad memory controller? A11. No, if the margin table shows one or two timing steps on both sides of selected strobe location in the passing region, then that would be acceptable or good margin. If that is not the case and no margin is available then the DDR interface on the board under the test would be considered to have low margin. The size of the passing margin would depend on the all the components in the DDR interface. This includes the memory controller, DRAM and the board (interconnect). We have tested the memory controller with the same margin tool and have acceptable passing region in our reference design boards. If low passing margin is observed on several boards then the board could be examined for showing low margin. 32 Freescale Semiconductor, Inc.

33 How to Reach Us: Home Page: freescale.com Web Support: freescale.com/support Information in this document is provided solely to enable system and software implementers to use Freescale products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits based on the information in this document. Freescale reserves the right to make changes without further notice to any products herein. Freescale makes no warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does Freescale assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. Typical parameters that may be provided in Freescale data sheets and/or specifications can and do vary in different applications, and actual performance may vary over time. All operating parameters, including typicals, must be validated for each customer application by customer's technical experts. Freescale does not convey any license under its patent rights nor the rights of others. Freescale sells products pursuant to standard terms and conditions of sale, which can be found at the following address: freescale.com/salestermsandconditions. Freescale, the Freescale logo, CodeWarrior, Processor Expert, and QorIQ are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. All other product or service names are the property of their respective owners Freescale Semiconductor, Inc. Document Number QCVSDDRVUG Revision 4.2, 03/2015