Ptolemy Ptutorial. Edward A. Lee UC Berkeley. This tutorial is aimed at the software developer planning to use Ptolemy as a platform.

Transcription

1 Ptolemy Ptutorial Edward A. Lee UC Berkeley This tutorial is aimed at the software developer planning to use Ptolemy as a platform. For Ptolemy version 0.7. Copyright 9/24/97, The Regents of the University of California All rights reserved. ptutorial_97.fm 9/24/97, p. 1 of 79 UNIVERSITY OF CALIFORNIA AT BERKELEY

2 Ptolemy as a Tool and as a Laboratory Ptolemy is Extensible Publicly available An open architecture Object-oriented Allows for experiments with: Models of computation Domain-specific tools Design methodology Software synthesis Hardware synthesis Cosimulation Codesign Rationale for heterogeneity: specialized models are More useful to the system-level designer More amenable to hardware and software synthesis. ptutorial_97.fm 9/24/97, p. 2 of 79 UNIVERSITY OF CALIFORNIA AT BERKELEY

3 Interactive, High-Level Simulation and Specification Author: Uwe Trautwein, Technical University of Ilmenau, Germany talk.fm UNIVERSITY OF CALIFORNIA AT BERKELEY 1997, p. 5 of 24

4 Domains in Ptolemy CGC Code generation domains CG56 CG96 Silage VHDLF SDF BDF PTOLEMY KERNEL DDF PN process networks dynamic dataflow Boolean dataflow synchronous dataflow MDSDF multidimensional SDF Thor VHDLB circuit simulation CG Sproc ptutorial_97.fm DE DMM CP discrete-event communicating processes design methodology management 9/24/97, p. 13 of 79 UNIVERSITY OF CALIFORNIA AT BERKELEY

5 Domain Classes Derived from Kernel Classes A NamedObj Assume XXX and YYY are two domain names. Block Runnable Galaxy Star A Wormhole Universe XXXStar YYYStar multiple inheritance XXXWormhole XXXUserStar real work done here ptutorial_97.fm 9/24/97, p. 12 of 79 UNIVERSITY OF CALIFORNIA AT BERKELEY

6 Example: DE, Dataflow, and FSMs talk.fm UNIVERSITY OF CALIFORNIA AT BERKELEY 1997, p. 21 of 24

7 Anytype Fork: replicate a particle Commutator: merge particle streams Distributor: split particle streams Red stems indicate stars that operate on any particle. The code inside refers only to type Particle, so these stars are polymorphic. ptutorial_97.fm 9/24/97, p. 17 of 79 UNIVERSITY OF CALIFORNIA AT BERKELEY

8 Heterogeneous System-Level Specification & Modeling problem level (heterogeneous models of computation) mapping, synthesis, & modeling implementation level (heterogeneous implementation technologies) talk.fm 1997, p. 9 of 24 UNIVERSITY OF CALIFORNIA AT BERKELEY

9 A Mixed Design Flow system-level modeling cosimulation symbolic imperative FSMs dataflow discrete event synthesis partitioning compiler software synthesis ASIC synthesis logic synthesis execution model execution model ASIC model logic model cosimulation detail modeling and simulation talk.fm 1997, p. 17 of 24 UNIVERSITY OF CALIFORNIA AT BERKELEY

10 Die Co-Design Umgebung POLIS PTOLEMY ESTEREL Esterelfile Modulbeschreibung POLIS-Stars POLIS Compiler Partitionierung Kopplung CFSM`s SW-Synthese Interf.Synthese HW-Synthese Simulation SW-Code+ RTOS Prototype Logik-Netzliste

11 FSM Example KEY_ON => START_TIMER WAIT OFF KEY_OFF or BELT _ON => END_TIMER_5 => ALARM_ON END_TIMER_10 or BELT_ON or KEY_OFF => ALARM_OFF ALARM ASV et al If no condition is satisfied, implicit self-loop in the current state

12 Network of CFSMs: Depth-1 Buffers C=>F C=>G CFSM1 C=>A C F G C B=>C F^(G==1) CFSM2 CFSM2 A C=>B B C=>B (A==0)=>B CFSM3 ASV et al. 1996

13 An example of S-graph ASV et al input event *c output event *y state int a input int b forever if (detect(*c)) if (a < b) a := a + 1 emit(*y) else a := 0 emit(*y) BEGIN *c a<b F T F T a := a + 1 a := 0 emit(*y) END

14 An example of interface: hw to sw ack HW x HwtoSw y SW / 0-1 / 0 x / 1 y x ack / y 10 / 1 ack ASV et al. 1996

15 Software synthesis procedure Specification, partitioning Code generation S-graph synthesis Compilation Timing estimation fail Testing, validation pass not feasible ASV et al Scheduling, validation feasible Production

16 Eisenbahnmodell

17 Informationsfluß - Simulation Bedienfeld für manuelle Steuerung Prozeßmodell Grafische Anzeige des Fahrbetriebs Tasten für die Bahnhöfe B, E, G, M Tcl - Skript Simulationsmodell Tcl - Skript entworfene Steuerung

18 Universum für Test

19 Nutzerschnittstelle für die Simulation Gleisbild/Fahrbetrieb Bedienfeld

20 Beispiel einer Steuerung dummy merge merge merge merge Kreis_1 Z1_acht merge C_Control Weichen merge Kreis_2 Z2_acht merge3 merge

21 Design-Fluß in POLIS ESTEREL CFSM S-Graph BEGIN module Strecken_Sicherung: input B_Zug, C_Zug, Taste; output A_Halt, B_Fahrt, B_Halt, A_Fahrt; emit B_Halt; loop await B_Zug; emit A_Halt; await Taste; emit B_Fahrt; await C_Zug; emit B_Halt; emit A_Fahrt; end loop end module 1 / B_Halt!B_Zug 2 C_Zug / B_Halt A_Fahrt B_Zug / A_Halt 4!C_Zug!Taste 3 Taste / B_Fahrt B_Halt Z=2 Z? B_Zug Taste C_Zug j j j A_Halt B_Fahrt A_Fahrt Z=3 Z=4 Sicherung des Bahnhofes B END

22 CFSM S-Graph BEGIN Z? !B_Zug!Taste 1 / B_Halt 2 C_Zug / B_Halt A_Fahrt B_Zug / A_Halt 4 3 Taste / B_Fahrt B_Halt B_Zug Taste C_Zug j j j A_Halt B_Fahrt A_Fahrt!C_Zug Z=2 Z=3 Z=4 END