LTE Layer 1 Software on the MSC8156 DSP Built on StarCore Technology

Transcription

1 July 2009 LTE Layer 1 Software on the MSC8156 DSP Built on StarCore Technology Vincent Martinez Baseband DSP System Engineer service names are the property of their respective owners. Freescale Semiconductor, Inc

2 Agenda Introduction Broadband Wireless Technology Timelines 3G Evolution from Thin to Thick Data Pipe Multicore DSP Roadmap based on StarCore LTE standard overview LTE overview SC-FDMA and OFDMA LTE L1 Channel Overview Multi User (MU) - MIMO Software overview LTE Layer 1 Software Components Algorithms L1 Matlab Reference Model Uplink Processing Chain Manager API Example MAPLE Abstraction Layer Implementation proposal on MSC8156 MSC8156 device overview Performance Analysis Methodology Use case definition & System Architecture Summary service names are the property of their respective owners. Freescale Semiconductor, Inc

3 Introduction service names are the property of their respective owners. Freescale Semiconductor, Inc

4 Broadband Wireless Technology Timelines GPP GSM EDGE Radio Access Network Evolution EDGE DL: 474 kbps UL: 474 kpbs Evolved EDGE DL: 1.1 Mbps UL: 947 kbps 3GPP UMTS Radio Access Network Evolution HSDPA DL: 14.4 Mbps UL: 384 kbps in 5 MHz HSDPA/HSUPA DL: 14.4 Mbps UL: 5.76 Mbps in 5 MHz Rel 7 HSPA+ DL: 28 Mbps UL: 11.5 Mbps in 5 Mhz Rel 8 HSPA+ DL: 42 Mbps UL: 11.5 Mbps in 5 Mhz 3GPP Long Term Evolution LTE 2X2 MIMO DL: 173 Mbps UL: 58 Mbps in 20 MHz LTE 4X4 MIMO DL: 326 Mbps UL: 86 Mbps in 20 MHz CDMA2000 Evolution EV-DO Rev 0 DL: 2.4 Mbps UL: 153 kbps in 1.25 MHz EV-DO Rev A DL: 3.1 Mbps UL: 1.8 Mbps in 1.25 MHz EV-DO Rev B DL: 14.7 Mbps UL: 4.9 Mbps in 5 MHz UMB 2X2 MIMO DL: 140 Mbps UL: 34 Mbps in 20 MHz UMB 4X4 MIMO DL: 280 Mbps UL: 68 Mbps in 20 MHz Mobile WiMAX Evolution Fixed WiMAX Wave 1 DL: 23 Mbps UL: 4 Mbps 10 MHz 3:1 TDD Wave 2 DL: 46 Mbps UL: 4 Mbps 10 MHz 3:1 TDD IEEE m Source: Rysavy Research Note: Throughput rates are peak network rates. Radio channel bandwidths indicated. Dates refer to initial network deployment except 2006 which shows available technologies that year. service names are the property of their respective owners. Freescale Semiconductor, Inc

5 3G Evolution from Thin to Thick Data Pipe 3G LTE Significantly Outperforms 3G Standards Increasing flexibility for data rates and bandwidth Algorithm differentiation and flexibility require high-performance multicore DSPs for programmability combined with integrated or attached accelerators for cost and power efficiency 3G-LTE 300+ Mbps DL at 20 MHz WCDMA 0.5 Mbps at 5MHz HSDPA Up to 14 Mbps DL at 5MHz HSUPA Up to 5 Mbps UL at 5Mhz HSPA+ Up to 42 Mbps DL at 5MHz service names are the property of their respective owners. Freescale Semiconductor, Inc

6 Binary Code Compatible Multicore DSP Roadmap based on StarCore Performance MSC8122 Quad core 500-MHz SC140 8 (16-bit) GMACs 1.4Mbyte RAM 90nm MSC8126 Quad core 500-MHz SC140 8 (16-bit) GMACs Integrated Turbo & Viterbi COPs 1.4 Mbyte RAM Ethernet, Serial 90nm Tri & Dual core 400/300-MHz SC140 Starcore cores 8 (16-bit) GMACs 1.4Mbyte RAM 90nm 2008 intro MSC8144/E Quad core 1-GHz SC3400 cores 16 (16-bit) GMACs 10.5 Mbyte RAM Dual 1G Ethernet (SGMII) A/Utopia Integrated Security Accel. Serial RapidIO port x4 (3.125 Gbaud) 90nm MSC8112/3 Enabled with Advanced BaseBand Accelerators MSBA8100 Accelerator device for 3G-LTE, TDD-LTE, WiMAX, TD-SCDMA, 3GPP, 3GPP2 Turbo, Viterbi, FFT, DFT 512 KB internal RAM DDR2 PCI Dual Serial RapidIO ports x4 (3.125 Gbaud) Companion for MSC nm MSC8156 Multicore DSP SoCs Next generation StarCore Core Positioned for 3G- LTE, TDD-LTE, WiMAX, TD-SCDMA, 3GPP, 3GPP2 Next generation process technology Enabled MSC81xx Future StarCore DSP Production Sampling Alpha Sampling Future service names are the property of their respective owners. Freescale Semiconductor, Inc

7 LTE standard overview service names are the property of their respective owners. Freescale Semiconductor, Inc

8 LTE overview LTE facts 3GPP LTE (ongoing) WiMAX e Base standard Currently v8.5.0 IEEE e-2005 Duplex method FDD/TDD TDD (FDD optional) Downlink OFDMA OFDMA Uplink SC-FDMA OFDMA Channel BW (MHz) 1.25, 2.5, 5, 10,15, 20 5, 7, 8.75, 10 (1.25~20 opt) Frame size 10 ms TDD 5 ms TDD Modulation DL QPSK/16QAM/64QAM QPSK/16QAM/64QAM Modulation UL QPSK/16QAM/64QAM QPSK/16QAM Channel Coding DL Turbo / CC Turbo / CC Channel Coding UL Turbo / CC Turbo / CC Throughput (DL/UL) 100/50 Mbps (20 MHz) ~40 shared (10 MHz, TDD) HARQ Incremental redundancy Chase combining service names are the property of their respective owners. Freescale Semiconductor, Inc

9 Single Carrier FDMA (SC-FDMA) and OFDMA OFDMA (downlink) X(k) S/P IFFT P/S x(n) Cyclic Prefix The symbol mapping in OFDM happens in the frequency domain. Frequency Domain Time Domain In SC-FDMA, the symbol mapping is done in the time domain. SC-FDMA (uplink) DFT Subcarrier Mapping X(k) IFFT P/S x(n) Cyclic Prefix Appropriate subcarrier mapping in the frequency domain allows control of the PAPR Time Domain Frequency Domain Time Domain SC-FDMA enables frequency domain equalizer approaches like OFDMA service names are the property of their respective owners. Freescale Semiconductor, Inc

10 LTE L1 Channel Overview Dir Transport Channel Physical Channel Usage Coding DL DL-SCH PDSCH DL data channel Turbo 1/3 PCH PDSCH Paging channel for call initialization BCH PBCH Broadcast channel for general cell information Turbo 1/3 Conv. 1/3 Data DL-SCH PCH BCH MCH Control CFI HI DCI MCH PMCH Multicase channel Turbo 1/3 DL CFI PCFICH Control format indicator, encodes the number of DL-CCH OFDMA symbols HI PHICH HARQ feedback channel DCI PDCCH DL control channel with subframe scheduling information Block Code 1/16 Repet. 1/3 Conv. 1/3 UL UL-SCH PUSCH UL data channel Turbo 1/3 RACH PRACH Random access channel for UE connection init 64 ZC signatures UL PDSCH PBCH PMCH UL-SCH RACH PUSCH PRACH Transport Channels Physical Channels PCFICH PHICH PDCCH UCI PUCCH UCI PUCCH UL control channel for CQI and HARQ feedback Reed Muller encoding service names are the property of their respective owners. Freescale Semiconductor, Inc

11 Multi User (MU) MIMO LTE Uplink: classic SIMO or MU- MIMO for enhanced data rates SISO/SIMO: (1xM) MU-MIMO: several users are transmitting data simultaneously onto the same frequencies. Tx h siso Channel Rx MIMO Decoder: Tx users streams demultiplexed at Equalization stage. Equalization based on MMSE, IRC or iterative cancellations (SIC) MIMO: (2xM) Tx1 x 1 h 11 h 12 y 1 Rx1 y 2 Tx2 Rx2 h 2m x 2 y m service names are the property of their respective owners. Freescale Semiconductor, Inc

12 Software Overview service names are the property of their respective owners. Freescale Semiconductor, Inc

13 Application Layer: Integration and application scheduler functionality. LTE Library: The OS independent implementation of the LTE Layer1 functionality. Multicore Framework: Responsible for memory management, multicore communication and low level resource scheduling. MAPLE Abstraction Layer: Thin layer to abstract OS implementation details for controling the MAPLE HW accelerator. (Multi Accelerator Platform for BaseBand, details in next slides) Coherency Abstraction Layer: Function library with services to handle the coherency management. IF1 and IF4 interfaces: Cover the protocol and LTE specific aspects of the interface with PQ and FPGA. Operating System: Operating system services and driver level support for device peripheral access. LTE Layer 1 Software Components IF1 IF4 MAPLE Abstraction Application Layer LTE SP Lib Operating System Software Coherency Abstraction Framework service names are the property of their respective owners. Freescale Semiconductor, Inc

14 L1 Matlab Reference Model Maintaining LTE Matlab model for fast algorithm validation Channel estimator MIMO detector Equalization Modulation Demapper HARQ Combining Matlab model also serves as Golden Reference DSP C code included through MEX files Ability to generate test vectors High simulation speed Between 10 kbps to 150 kbps real time speed depending on config service names are the property of their respective owners. Freescale Semiconductor, Inc

15 Uplink Processing Chain SBL1_PHULSPM_RSP RxAnt0 CP Removal FFT Guard Removal Ref Vec Correlation IDFT User Path Separation DFT RxAnt1 CP Removal FFT Guard Removal Ref Vec Correlation IDFT User Path Separation DFT SBL1_PHULSPM_VRB DeScrambling DemodMapping IDFT MMSE Equalization Matrix interpolation SNR estimation DeScrambling DemodMapping IDFT SBL1_PHULSPM_PRB Chnl De-Interleav. DC Demux Code Block Deconcatenation Soft Combining Sub-block De-interl Turbo Decoding CB CRC Check.. Soft Combining Sub-block De-interl Turbo Decoding CB CRC Check SBL1_PHULSPM_DCdemux Chnl De-Interleav. DC Demux Code Block Deconcatenation Soft Combining Sub-block De-interl Turbo Decoding CB CRC Check. SBL1_PHULSPM_CBP. Soft Combining Sub-block De-interl Turbo Decoding CB CRC Check SBL1_PHULSPM_TBP TB CRC Check CB DeSegmentation TB CRC Check CB DeSegmentation service names are the property of their respective owners. Freescale Semiconductor, Inc

16 Manager API Example INT32 SBL1_PHULSPM_PRB( SPM_PRB_DYNAMIC_T *spm_prb_dynamic, void *spm_prb_static, SPM_PRB_CTRL_DYNAMIC_T *spm_prb_ctrl_dynamic, SYS_CONFIG_T *sys_config, SWC_T *swc_handler, type_dftpe_mal maple_handler) IF1 1 2 IF4 MAPLE Abstraction Application Layer LTE SP Lib 3 Software Coherency Abstraction 4 Framework (1) SPM_PRB_DYNAMIC_T pointers to the buffers specific to the current manager call instance. 6 5 Operating System (2) SPM_PRB_STATIC_T pointers to the buffers common to all the instances of this manager. (3) SPM_PRB_CTRL_DYNAMIC_T control parameters that are specific to the current manager call instance (the number of allocations, number of codeblocks ) (4) SYS_CONFIG_T system configuration parameter information, setup at system initiation (sector bandwidth, the number of antennas, etc.) (5) SWC_T pointers to the software coherency functions (cache flush and cache invalidate). (6) type_dftpe_mal pointers to the Maple abstraction function for IDFT / DFT / TurboDecoder / ViterbiDecoder service names are the property of their respective owners. Freescale Semiconductor, Inc

17 Application layer SPKernal 1 SPKernal 2 L1 SW Manager MAPLE Drivers MAPLE Abstraction Layer MAPLE Abstraction Layer (MAL) is responsible for the encapsulation of the MAPLE interaction based on SDOS drivers. The goal is to keep the SP Lib independent of the underlaying OS while allowing a close integration of the MAPLE accelerator in the processing chains MAL API covers: MAPLE init functionality for LTE mode FFTPE, DFTPE and TVPE drivers configured for LTE operation Callback functions MAPLE Abstraction MAPLE Blocking Master Slave PE Non-Blocking Master Slave PE Call Back Process MAPLE Feedback Dispatch & post msg Get msg & FMWK sched Manager execution Dispatch & post msg Get msg & FMWK sched Manager execution Idle: Mape Abstraction PE execution Manager execution PE execution Polling mechanism FMWK sched ISR post msg #1 Manager execution FMWK sched & Post msg #0 FMWK sched & Post msg #0 service names are the property of their respective owners. Freescale Semiconductor, Inc

18 Implementation Proposal on MSC8156 service names are the property of their respective owners. Freescale Semiconductor, Inc

19 6 SC3850 Cores Subsystems (up to 6GHz/48GMACS) each with: SC3850 DSP core at up to 1GHz (8GMACs 16b or 8b) 512 Kbyte unified L2 cache / M2 memory. 32 Kbyte I-cache, 32Kbyte D-cache, WBB, WTB, MMU, PIC Internal/External Memories/Caches 1056 KByte M3 shared memory (SRAM) Two DDR 2/3 64-bit SDRAM interfaces at up to 800 MHz CLASS Chip-Level Arbitration & Switching Fabric Non-Blocking, fully pipelined, low latency Full fabric 12 masters to 8 slaves, up to 512 Gbps throughput MAPLE-B Baseband Accelerator Turbo/Viterbi Decoder up to 160/115 Mbps, supporting: 3G- LTE, , 3G, CDMA2K standards FFT/DFT accelerator up to 280/180 Msps DFT Security Engine (Talitos 3.1) Data and Code Protection (AES, SHA, Kasumi, SNOW3G) High Speed Interconnects Dual 4x/1x Serial RapidIO at 1.25/2.5/3.125 Gbaud PCI-e 4x/1x Dual RISC QUICCEngine supporting Dual SGMII/RGMII Gigabit Ethernet ports Eth. L1 Protocols, Talitos control and offload TDM Highway 1024 ch., 400Mbps, divided into 4 ports of 256 DMA Engine 16 bi-directional channels w/ external req/ack 8 hardware semaphores Other Peripheral Interfaces SPI, UART, I2C, 32 GPIO, 16 Timers, 96KB boot ROM, JTAG/SAP, 8 WDT Technology 45nm SOI, 1V core, 2.5, 1.8/1.5V I/O FCBPGA (29x29) 1mm pitch, RoHS MSC8156E Broadband Wireless DSP CLASS Non-Blocking Switch Fabric SerDes x4 SC3850 core 32KB L1 I-Cache SC3850 core 32KB L1 I-Cache On-Chip Network 2x SRIO 4x/1x, 1x PCIe 4x/1x 32KB L1 D-Cache 512KB Unified M2/L2 SC3850 core 32KB L1 I-Cache 32KB L1 D-Cache 512KB Unified M2/L2 32KB L1 D-Cache 512KB Unified M2/L2 6 cores CLASS Non-Blocking Switch Fabric SerDes x4 2x Gigabit Ethernet, SPI SC3850 core 32KB L1 I-Cache SC3850 core 32KB L1 I-Cache 32KB L1 D-Cache 512KB Unified M2/L2 SC3850 core 32KB L1 I-Cache 32KB L1 D-Cache 512KB Unified M2/L2 32KB L1 D-Cache 512KB Unified M2/L2 TDM Highway 4 ports CLASS Non-Blocking Switch Fabric DDR 2/3 Memory Controller Security Processing Engine Alpha Sampling Now Shared Memory 1056 KB DMA Engine DDR 2/3 Memory Controller I²C, UART, GPIOs H/W Semaphores MAPLE-B Baseband Accelerator Freescale Semiconductor Proprietary Information. Freescale and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. Freescale Semiconductor, Inc

20 MSC8156 MAPLE-B Throughput & Compliance Data Technology Accel. Standard Compliance Data Rates Comments 3G-LTE, TDD-LTE Turbo 3G-LTE (Evolved UTRA) turbo decoding as specified in 3GPP TS , section up to 160 Mbps (8 iterations) up to 200 Mbps (6 iterations) Max Log Map or Linear Log Map (MAX*) Support Rate-De-Matching (sub-block de-interleaving and de-interlacing) CRC calculation Viterbi 3G-LTE (Evolved UTRA) channel decoding as specified in 3GPP TS , section up to 100 Mbps (K=7 with tail biting) Multi-iteration decoding FFT/DFT FFT sizes - 128, 256, 512, 1024, 2048 points DFT sizes - Variable lengths DFT/IDFT processing of the form 2 k 3 m 5 n 12, up to 1536 points FFT up to 280 Mega samples/sec DFT up to 175 Mega samples/sec Advanced scaling options Guard bands insertion in ifft CRC Transport and Code Block CRC for UL and DL up to 12 Gbps CRC check or insertion WiMAX Turbo WiMAX OFDMA turbo decoding as specified in IEEE standard up to 156 Mbps (8 iterations) up to 195 Mbps (6 iterations) Max Log Map or Linear Log Map (MAX*) Support Rate-De-Matching (sub-block de-interleaving and de-interlacing) Viterbi WiMAX OFDMA turbo decoding as specified in IEEE standard up to 100 Mbps (K=7 with tail biting) Multi-iteration decoding FFT FFT sizes - 128, 256, 512, 1024, 2048 points FFT2048 up to 280 Mega samples/sec FFT1024 up to 350 Mega samples/sec Advanced scaling options Guard bands insertion in ifft CRC PHY Burst CRC for UL and DL up to 12 Gbps CRC check or insertion HSPA+ Turbo 3GPP turbo decoding as specified in 3GPP TS , section up to 131 Mbps (8 iterations) up to 165 Mbps (6 iterations) Max Log Map or Linear Log Map (MAX*) Support EDCH Rate De-Matching Viterbi 3GPP viterbi decoding as specified in 3GPP TS , section up to 115 Mbps (K=9 zero tail) Programming Model ALL Buffer descriptors paradigm for allocation of data and control parameters Sharing of MAPLE-B modules in multiple devices using SRIO GO command activation, no DSP core pre-processing or intervention are required Freescale Semiconductor Proprietary Information. Freescale and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. Freescale Semiconductor, Inc

21 Performance Analysis Methodology Development steps used to perform capacity analysis on MSC8156: 1. 3GPP LTE standards detailed analysis 2. LTE Matlab Model: Validation of full LTE chain functionality, uplink and downlink Research, development and performance validation of algorithms (Channel Estimation, MIMO Equalizer, RACH, HARQ Combining) 3. StarCore C code implementation Code generation Fixed point validation, feeding code back in Matlab with mexfiles Target cycles measurements on MSC8156 simulator and ADS boards Code optimization 4. Real time integration Integration of all LTE Layer 1 Software Components Validation of real time throughput and latency service names are the property of their respective owners. Freescale Semiconductor, Inc

22 Use case definition & System Architecture DDR2 DDR2 DDR DDR MSC8156 DSP MSC8156 DSP 4x 4x Switch 4x QorIQ LB DDR DDR2/DDR3 FLASH PHY PHY Port 1 Port 0 Back Plane Ant. CPRI- Bridge LTE - FDD: 20 MHz 4x4 MIMO DL, up to 300 Mbps 2x4 MIMO UL, MMSE MIMO Equalizer, up to 150 Mbps 1 device DL, 1 device UL (+remote TVPE of DL device) 1 master core per device for I/O and application scheduling service names are the property of their respective owners. Freescale Semiconductor, Inc

23 Use case definition & System Architecture DDR2 DDR2 DDR DDR MSC8156 DSP MSC8156 DSP 4x 4x DL Device: Cores: From transport block encoding down to physical channel Mapping Maple: IFFT Switch 4x QorIQ LB DDR DDR2/DDR3 FLASH PHY PHY Port 1 Port 0 Back Plane Ant. CPRI- Bridge LTE - FDD: 20 MHz 4x4 MIMO DL, up to 300 Mbps 2x4 MIMO UL, MMSE MIMO Equalizer, up to 150 Mbps 1 device DL, 1 device UL (+remote TVPE of DL device) 1 master core per device for I/O and application scheduling service names are the property of their respective owners. Freescale Semiconductor, Inc

24 Use case definition & System Architecture DDR2 DDR2 DDR DDR MSC8156 DSP MSC8156 DSP 4x 4x Switch UL Device: Cores: Channel estimation, MIMO Detector, Equalization,LLR calculation. Maple: FFT, IDFT, Turbo Dec. 4x QorIQ LB DDR DDR2/DDR3 FLASH PHY PHY Port 1 Port 0 Back Plane Ant. CPRI- Bridge LTE - FDD: 20 MHz 4x4 MIMO DL, up to 300 Mbps 2x4 MIMO UL, MMSE MIMO Equalizer, up to 150 Mbps 1 device DL, 1 device UL (+remote TVPE of DL device) 1 master core per device for I/O and application scheduling service names are the property of their respective owners. Freescale Semiconductor, Inc

25 Summary LTE standard designed for high throughput with 4x4 MIMO OFDMA in Downlink and 2x4 MIMO SC-FDMA in Uplink. Real challenge for: High signal processing complexity for advanced algorithms Complex system SW architecture in multicore environment Very high data rates and low latency systems Freescale LTE Layer1 enablement software components include Advanced Signal Processing library with key algorithms a Multicore Framework all needed application & abstraction layers for a smooth integration Freescale DSP MSC8156: The MAPLE-B baseband accelerator together with the advanced StarCore cores provides key factor for current and future BaseBand systems design with very high data throughput and low latency requirements service names are the property of their respective owners. Freescale Semiconductor, Inc

26 Q&A Thank you for attending this presentation. We ll now take a few moments to review the audience questions, and then we ll begin the question and answer session. service names are the property of their respective owners. Freescale Semiconductor, Inc

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