BOSCH. CAN Specification. Version 2.0. 1991, Robert Bosch GmbH, Postfach 30 02 40, D-70442 Stuttgart

CAN Specification Version 2.0 1991, Robert Bosch GmbH, Postfach 30 02 40, D-70442 Stuttgart

CAN Specification 2.0 page 1 Recital The acceptance an introuction of serial communication to more an more applications has le to requirements that the assignment of message ientifiers to communication functions be stanarize for certain applications. These applications can be realize with CAN more comfortably, if the aress range that originally has been efine by 11 ientifier bits is enlarge Therefore a secon message format ( extene format ) is introuce that provies a larger aress range efine by 29 bits. This will relieve the system esigner from compromises with respect to efining well-structure naming schemes. Users of CAN who o not nee the ientifier range offere by the extene format, can rely on the conventional 11 bit ientifier range ( stanar format ) further on. In this case they can make use of the CAN implementations that are alreay available on the market, or of new controllers that implement both formats. In orer to istinguish stanar an extene format the first reserve bit of the CAN message format, as it is efine in CAN Specification 1.2, is use. This is one in such a way that the message format in CAN Specification 1.2 is equivalent to the stanar format an therefore is still vali. Furthermore, the extene format has been efine so that messages in stanar format an extene format can coexist within the same network. This CAN Specification consists of two parts, with Part A escribing the CAN message format as it is efine in CAN Specification 1.2; Part B escribing both stanar an extene message formats. In orer to be compatible with this CAN Specification 2.0 it is require that a CAN implementation be compatible with either Part A or Part B. Note CAN implementations that are esigne accoring to part A of this or accoring to previous CAN Specifications, an CAN implementations that are esigne accoring to part B of this specification can communicate with each other as long as it is not mae use of the extene format.

PART A

Contents Part A - page 3 1 INTRODUCTION...4 2 BASIC CONCEPTS...5 3 MESSAGE TRANSFER...10 3.1 Frame Types...10 3.1.1 DATA FRAME...10 3.1.2 REMOTE FRAME...15 3.1.3 ERROR FRAME...16 3.1.4 OVERLOAD FRAME...17 3.1.5 INTERFRAME SPACING...18 3.2 Definition of TRANSMITTER/RECEIVER...20 4 MESSAGE VALIDATION...21 5 CODING...22 6 ERROR HANDLING...23 6.1 Error Detection...23 6.2 Error Signalling...23 7 FAULT CONFINEMENT...24 8 BIT TIMING REQUIREMENTS...27 9 INCREASING CAN OSCILLATOR TOLERANCE...31 9.1 Protocol Moifications...31

1 INTRODUCTION Introuction Part A - page 4 The Controller Area Network (CAN) is a serial communications protocol which efficiently supports istribute realtime control with a very high level of security. Its omain of application ranges from high spee networks to low cost multiplex wiring. In automotive electronics, engine control units, sensors, anti-ski-systems, etc. are connecte using CAN with bitrates up to 1 Mbit/s. At the same time it is cost effective to buil into vehicle boy electronics, e.g. lamp clusters, electric winows etc. to replace the wiring harness otherwise require. The intention of this specification is to achieve compatibility between any two CAN implementations. Compatibility, however, has ifferent aspects regaring e.g. electrical features an the interpretation of ata to be transferre. To achieve esign transparency an implementation flexibility CAN has been subivie into ifferent layers. the (CAN-) object layer the (CAN-) transfer layer the physical layer The object layer an the transfer layer comprise all services an functions of the ata link layer efine by the ISO/OSI moel. The scope of the object layer inclues fining which messages are to be transmitte eciing which messages receive by the transfer layer are actually to be use, proviing an interface to the application layer relate harware. There is much freeom in efining object hanling. The scope of the transfer layer mainly is the transfer protocol, i.e. controlling the framing, performing arbitration, error checking, error signalling an fault confinement. Within the transfer layer it is ecie whether the bus is free for starting a new transmission or whether a reception is just starting. Also some general features of the bit timing are regare as part of the transfer layer. It is in the nature of the transfer layer that there is no freeom for moifications. The scope of the physical layer is the actual transfer of the bits between the ifferent noes with respect to all electrical properties. Within one network the physical layer, of course, has to be the same for all noes. There may be, however, much freeom in selecting a physical layer. The scope of this specification is to efine the transfer layer an the consequences of the CAN protocol on the surrouning layers.

2 BASIC CONCEPTS CAN has the following properties prioritization of messages guarantee of latency times configuration flexibility Basic Concepts Part A - page 5 multicast reception with time synchronization system wie ata consistency multimaster error etection an signalling automatic retransmission of corrupte messages as soon as the bus is ile again istinction between temporary errors an permanent failures of noes an autonomous switching off of efect noes Layere Structure of a CAN Noe Application Layer Object Layer - Message Filtering - Message an Status Hanling Transfer Layer - Fault Confinement - Error Detection an Signalling - Message Valiation - Acknowlegment - Arbitration - Message Framing - Transfer Rate an Timing Physical Layer - Signal Level an Bit Representation - Transmission Meium

Basic Concepts Part A - page 6 The Physical Layer efines how signals are actually transmitte. Within this specification the physical layer is not efine so as to allow transmission meium an signal level implementations to be optimize for their application. The Transfer Layer represents the kernel of the CAN protocol. It presents messages receive to the object layer an accepts messages to be transmitte from the object layer. The transfer layer is responsible for bit timing an synchronization, message framing, arbitration, acknowlegment, error etection an signalling, an fault confinement. The Object Layer is concerne with message filtering as well as status an message hanling. The scope of this specification is to efine the transfer layer an the consequences of the CAN protocol on the surrouning layers. Messages Information on the bus is sent in fixe format messages of ifferent but limite length (see section 3: Message Transfer). When the bus is free any connecte unit may start to transmit a new message. Information Routing In CAN systems a CAN noe oes not make use of any information about the system configuration (e.g. station aresses). This has several important consequences. System Flexibility: Noes can be ae to the CAN network without requiring any change in the software or harware of any noe an application layer. Message Routing: The content of a message is name by an IDENTIFIER. The IDENTIFIER oes not inicate the estination of the message, but escribes the meaning of the ata, so that all noes in the network are able to ecie by MESSAGE FILTERING whether the ata is to be acte upon by them or not. Multicast: As a consequence of the concept of MESSAGE FILTERING any number of noes can receive an simultaneously act upon the same message. Data Consistency: Within a CAN network it is guarantee that a message is simultaneously accepte either by all noes or by no noe. Thus ata consistency of a system is achieve by the concepts of multicast an by error hanling.

Basic Concepts Part A - page 7 Bit rate The spee of CAN may be ifferent in ifferent systems. However, in a given system the bitrate is uniform an fixe. Priorities The IDENTIFIER efines a static message priority uring bus access. Remote Data Request By sening a REMOTE FRAME a noe requiring ata may request another noe to sen the corresponing DATA FRAME. The DATA FRAME an the corresponing REMOTE FRAME are name by the same IDENTIFIER. Multimaster When the bus is free any unit may start to transmit a message. The unit with the message of higher priority to be transmitte gains bus access. Arbitration Whenever the bus is free, any unit may start to transmit a message. If 2 or more units start transmitting messages at the same time, the bus access conflict is resolve by bitwise arbitration using the IDENTIFIER. The mechanism of arbitration guarantees that neither information nor time is lost. If a DATA FRAME an a REMOTE FRAME with the same IDENTIFIER are initiate at the same time, the DATA FRAME prevails over the REMOTE FRAME. During arbitration every transmitter compares the level of the bit transmitte with the level that is monitore on the bus. If these levels are equal the unit may continue to sen. When a recessive level is sent an a ominant level is monitore (see Bus Values), the unit has lost arbitration an must withraw without sening one more bit. Safety In orer to achieve the utmost safety of ata transfer, powerful measures for error etection, signalling an self-checking are implemente in every CAN noe. Error Detection For etecting errors the following measures have been taken: - Monitoring (transmitters compare the bit levels to be transmitte with the bit levels etecte on the bus) - Cyclic Reunancy Check - Bit Stuffing - Message Frame Check

Basic Concepts Part A - page 8 Performance of Error Detection The error etection mechanisms have the following properties: - all global errors are etecte. - all local errors at transmitters are etecte. - up to 5 ranomly istribute errors in a message are etecte. - burst errors of length less than 15 in a message are etecte. - errors of any o number in a message are etecte. Total resiual error probability for unetecte corrupte messages: less than message error rate * 4.7 * 10-11. Error Signalling an Recovery Time Corrupte messages are flagge by any noe etecting an error. Such messages are aborte an will be retransmitte automatically. The recovery time from etecting an error until the start of the next message is at most 29 bit times, if there is no further error. Fault Confinement CAN noes are able to istinguish short isturbances from permanent failures. Defective noes are switche off. Connections The CAN serial communication link is a bus to which a number of units may be connecte. This number has no theoretical limit. Practically the total number of units will be limite by elay times an/or electrical loas on the bus line. Single Channel The bus consists of a single channel that carries bits. From this ata resynchronization information can be erive. The way in which this channel is implemente is not fixe in this specification. E.g. single wire (plus groun), two ifferential wires, optical fibres, etc. Bus values The bus can have one of two complementary logical values: ominant or recessive. During simultaneous transmission of ominant an recessive bits, the resulting bus value will be ominant. For example, in case of a wire-and implementation of the bus, the ominant level woul be represente by a logical 0 an the recessive level by a logical 1. Physical states (e.g. electrical voltage, light) that represent the logical levels are not given in this specification.

Basic Concepts Part A - page 9 Acknowlegment All receivers check the consistency of the message being receive an will acknowlege a consistent message an flag an inconsistent message. Sleep Moe / Wake-up To reuce the system s power consumption, a CAN-evice may be set into sleep moe without any internal activity an with isconnecte bus rivers. The sleep moe is finishe with a wake-up by any bus activity or by internal conitions of the system. On wake-up, the internal activity is restarte, although the transfer layer will be waiting for the system s oscillator to stabilize an it will then wait until it has synchronize itself to the bus activity (by checking for eleven consecutive recessive bits), before the bus rivers are set to "on-bus" again. In orer to wake up other noes of the system, which are in sleep-moe, a special wake-up message with the eicate, lowest possible IDENTIFIER (rrr rrr rrrr; r = recessive = ominant ) may be use.

Message Transfer Part A - page 10 3 MESSAGE TRANSFER 3.1 Frame Types Message transfer is manifeste an controlle by four ifferent frame types: A DATA FRAME carries ata from a transmitter to the receivers. A REMOTE FRAME is transmitte by a bus unit to request the transmission of the DATA FRAME with the same IDENTIFIER. An ERROR FRAME is transmitte by any unit on etecting a bus error. An OVERLOAD FRAME is use to provie for an extra elay between the preceing an the succeeing DATA or REMOTE FRAMEs. DATA FRAMEs an REMOTE FRAMEs are separate from preceing frames by an INTERFRAME SPACE. 3.1.1 DATA FRAME A DATA FRAME is compose of seven ifferent bit fiels: START OF FRAME, ARBITRATION FIELD, CONTROL FIELD, DATA FIELD, CRC FIELD, ACK FIELD, END OF FRAME. The DATA FIELD can be of length zero. Interframe Space DATA FRAME Interframe Space Start of Frame or Overloa Frame Arbitration Fiel Control Fiel Data Fiel CRC Fiel ACK Fiel En of Frame

Data Frame Part A - page 11 START OF FRAME marks the beginning of DATA FRAMES an REMOTE FRAMEs. It consists of a single ominant bit. A station is only allowe to start transmission when the bus is ile (see BUS IDLE). All stations have to synchronize to the leaing ege cause by START OF FRAME (see HARD SYNCHRONIZATION ) of the station starting transmission first. ARBITRATION FIELD The ARBITRATION FIELD consists of the IDENTIFIER an the RTR-BIT. Interframe Space Start of Frame ARBITRATION FIELD Control Fiel Ientifier RTR Bit IDENTIFIER The IDENTIFIER s length is 11 bits. These bits are transmitte in the orer from ID-10 to ID-0. The least significant bit is ID-0. The 7 most significant bits (ID-10 - ID-4) must not be all recessive. RTR BIT Remote Transmission Request BIT In DATA FRAMEs the RTR BIT has to be ominant. Within a REMOTE FRAME the RTR BIT has to be recessive. CONTROL FIELD The CONTROL FIELD consists of six bits. It inclues the DATA LENGTH CODE an two bits reserve for future expansion. The reserve bits have to be sent ominant. Receivers accept ominant an recessive bits in all combinations. DATA LENGTH CODE The number of bytes in the DATA FIELD is inicate by the DATA LENGTH CODE. This DATA LENGTH CODE is 4 bits wie an is transmitte within the CONTROL FIELD.

Data Frame Part A - page 12 Arbitration Fiel CONTROL FIELD Data Fiel r1 r0 DLC3 DLC2 DLC1 DLC0 or CRC Fiel reserve bits Data Length Coe Coing of the number of ata bytes by the DATA LENGTH CODE abbreviations: ominant r recessive Number of Data Bytes Data Length Coe DLC3 DLC2 DLC1 DLC0 0 1 r 2 r 3 r r 4 r 5 r r 6 r r 7 r r r 8 r DATA FRAME: amissible numbers of ata bytes: {0,1,...,7,8}. Other values may not be use.

Data Frame Part A - page 13 DATA FIELD The DATA FIELD consists of the ata to be transferre within a DATA FRAME. It can contain from 0 to 8 bytes, which each contain 8 bits which are transferre MSB first. CRC FIELD contains the CRC SEQUENCE followe by a CRC DELIMITER. Data or Control Fiel CRC FIELD Ack Fiel CRC Sequence CRC Delimiter CRC SEQUENCE The frame check sequence is erive from a cyclic reunancy coe best suite for frames with bit counts less than 127 bits (BCH Coe). In orer to carry out the CRC calculation the polynomial to be ivie is efine as the polynomial, the coefficients of which are given by the estuffe bit stream consisting of START OF FRAME, ARBITRATION FIELD, CONTROL FIELD, DATA FIELD (if present) an, for the 15 lowest coefficients, by 0. This polynomial is ivie (the coefficients are calculate moulo-2) by the generator-polynomial: X 15 + X 14 + X 10 + X 8 + X 7 + X 4 + X 3 + 1. The remainer of this polynomial ivision is the CRC SEQUENCE transmitte over the bus. In orer to implement this function, a 15 bit shift register CRC_RG(14:0) can be use. If NXTBIT enotes the next bit of the bit stream, given by the estuffe bit sequence from START OF FRAME until the en of the DATA FIELD, the CRC SEQUENCE is calculate as follows: CRC_RG = 0; REPEAT CRCNXT = NXTBIT EXOR CRC_RG(14); CRC_RG(14:1) = CRC_RG(13:0); CRC_RG(0) = 0; // initialize shift register // shift left by // 1 position

Data Frame Part A - page 14 IF CRCNXT THEN CRC_RG(14:0) = CRC_RG(14:0) EXOR (4599hex); ENDIF UNTIL (CRC SEQUENCE starts or there is an ERROR conition) After the transmission / reception of the last bit of the DATA FIELD, CRC_RG contains the CRC sequence. CRC DELIMITER The CRC SEQUENCE is followe by the CRC DELIMITER which consists of a single recessive bit. ACK FIELD The ACK FIELD is two bits long an contains the ACK SLOT an the ACK DELIMITER. In the ACK FIELD the transmitting station sens two recessive bits. A RECEIVER which has receive a vali message correctly, reports this to the TRANSMITTER by sening a ominant bit uring the ACK SLOT (it sens ACK ). CRC Fiel ACK FIELD En of Frame ACK Slot ACK Delimiter ACK SLOT All stations having receive the matching CRC SEQUENCE report this within the ACK SLOT by superscribing the recessive bit of the TRANSMITTER by a ominant bit. ACK DELIMITER The ACK DELIMITER is the secon bit of the ACK FIELD an has to be a recessive bit. As a consequence, the ACK SLOT is surroune by two recessive bits (CRC DELIMITER, ACK DELIMITER). END OF FRAME Each DATA FRAME an REMOTE FRAME is elimite by a flag sequence consisting of seven recessive bits.

Remote Frame Part A - page 15 3.1.2 REMOTE FRAME A station acting as a RECEIVER for certain ata can initiate the transmission of the respective ata by its source noe by sening a REMOTE FRAME. A REMOTE FRAME is compose of six ifferent bit fiels: START OF FRAME, ARBITRATION FIELD, CONTROL FIELD, CRC FIELD, ACK FIELD, END OF FRAME. Contrary to DATA FRAMEs, the RTR bit of REMOTE FRAMEs is recessive. There is no DATA FIELD, inepenent of the values of the DATA LENGTH CODE which may be signe any value within the amissible range 0...8. The value is the DATA LENGTH CODE of the corresponing DATA FRAME. Inter Frame Space REMOTE FRAME Inter Frame Space or Overloa Frame Start of Frame Arbitration Fiel Control Fiel CRC Fiel ACK Fiel En of Frame The polarity of the RTR bit inicates whether a transmitte frame is a DATA FRAME (RTR bit ominant ) or a REMOTE FRAME (RTR bit recessive ).

Error Frame Part A - page 16 3.1.3 ERROR FRAME The ERROR FRAME consists of two ifferent fiels. The first fiel is given by the superposition of ERROR FLAGs contribute from ifferent stations. The following secon fiel is the ERROR DELIMITER. Data Frame Error Flag ERROR FRAME Interframe Space or Overloa Frame superposition of Error Flags Error Delimiter In orer to terminate an ERROR FRAME correctly, an error passive noe may nee the bus to be bus ile for at least 3 bit times (if there is a local error at an error passive receiver). Therefore the bus shoul not be loae to 100%. ERROR FLAG There are 2 forms of an ERROR FLAG: an ACTIVE ERROR FLAG an a PASSIVE ERROR FLAG. 1. The ACTIVE ERROR FLAG consists of six consecutive ominant bits. 2. The PASSIVE ERROR FLAG consists of six consecutive recessive bits unless it is overwritten by ominant bits from other noes. An error active station etecting an error conition signals this by transmission of an ACTIVE ERROR FLAG. The ERROR FLAG s form violates the law of bit stuffing (see CODING) applie to all fiels from START OF FRAME to CRC DELIMITER or estroys the fixe form ACK FIELD or END OF FRAME fiel. As a consequence, all other stations etect an error conition an on their part start transmission of an ERROR FLAG. So the sequence of ominant bits which actually can be monitore on the bus results from a superposition of ifferent ERROR FLAGs transmitte by iniviual stations. The total length of this sequence varies between a minimum of six an a maximum of twelve bits. An error passive station etecting an error conition tries to signal this by transmission of a PASSIVE ERROR FLAG. The error passive station waits for six consecutive bits

Overloa Frame Part A - page 17 of equal polarity, beginning at the start of the PASSIVE ERROR FLAG. The PASSIVE ERROR FLAG is complete when these 6 equal bits have been etecte. ERROR DELIMITER The ERROR DELIMITER consists of eight recessive bits. After transmission of an ERROR FLAG each station sens recessive bits an monitors the bus until it etects a recessive bit. Afterwars it starts transmitting seven more recessive bits. 3.1.4 OVERLOAD FRAME The OVERLOAD FRAME contains the two bit fiels OVERLOAD FLAG an OVERLOAD DELIMITER. There are two kins of OVERLOAD conitions, which both lea to the transmission of an OVERLOAD FLAG: 1. The internal conitions of a receiver, which requires a elay of the next DATA FRAME or REMOTE FRAME. 2. Detection of a ominant bit uring INTERMISSION. The start of an OVERLOAD FRAME ue to OVERLOAD conition 1 is only allowe to be starte at the first bit time of an expecte INTERMISSION, whereas OVERLOAD FRAMEs ue to OVERLOAD conition 2 start one bit after etecting the ominant bit. En of Frame or Error Delimiter or Overloa Delimiter Overloa Flag OVERLOAD FRAME Inter Frame Space or Overloa Frame superposition of Overloa Flags Overloa Delimiter At most two OVERLOAD FRAMEs may be generate to elay the next DATA or REMOTE FRAME.

Overloa Frame Part A - page 18 OVERLOAD FLAG consists of six ominant bits. The overall form correspons to that of the ACTIVE ERROR FLAG. The OVERLOAD FLAG s form estroys the fixe form of the INTERMISSION fiel. As a consequence, all other stations also etect an OVERLOAD conition an on their part start transmission of an OVERLOAD FLAG. (In case that there is a ominant bit etecte uring the 3r bit of INTERMISSION locally at some noe, the other noes will not interpret the OVERLOAD FLAG correctly, but interpret the first of these six ominant bits as START OF FRAME. The sixth ominant bit violates the rule of bit stuffing causing an error conition). OVERLOAD DELIMITER consists of eight recessive bits. The OVERLOAD DELIMITER is of the same form as the ERROR DELIMITER. After transmission of an OVERLOAD FLAG the station monitors the bus until it etects a transition from a ominant to a recessive bit. At this point of time every bus station has finishe sening its OVERLOAD FLAG an all stations start transmission of seven more recessive bits in coincience. 3.1.5 INTERFRAME SPACING DATA FRAMEs an REMOTE FRAMEs are separate from preceing frames whatever type they are (DATA FRAME, REMOTE FRAME, ERROR FRAME, OVERLOAD FRAME) by a bit fiel calle INTERFRAME SPACE. In contrast, OVERLOAD FRAMEs an ERROR FRAMEs are not precee by an INTERFRAME SPACE an multiple OVERLOAD FRAMEs are not separate by an INTERFRAME SPACE. INTERFRAME SPACE contains the bit fiels INTERMISSION an BUS IDLE an, for error passive stations, which have been TRANSMITTER of the previous message, SUSPEND TRANSMISSION.

Interframe Space Part A - page 19 For stations which are not error passive or have been RECEIVER of the previous message: Frame INTERFRAME SPACE Frame Intermission Bus Ile For error passive stations which have been TRANSMITTER of the previous message: Frame INTERFRAME SPACE Frame Intermission Bus Ile Suspen Transmission INTERMISSION consists of three recessive bits. During INTERMISSION no station is allowe to start transmission of a DATA FRAME or REMOTE FRAME. The only action to be taken is signalling an OVERLOAD conition. BUS IDLE The perio of BUS IDLE may be of arbitrary length. The bus is recognize to be free an any station having something to transmit can access the bus. A message, which is pening for transmission uring the transmission of another message, is starte in the first bit following INTERMISSION. The etection of a ominant bit on the bus is interprete as a START OF FRAME. SUSPEND TRANSMISSION After an error passive station has transmitte a message, it sens eight recessive bits following INTERMISSION, before starting to transmit a further message or recognizing the bus to be ile. If meanwhile a transmission (cause by another station) starts, the station will become receiver of this message.

Transmitter / Receiver Part A - page 20 3.2 Definition of TRANSMITTER / RECEIVER TRANSMITTER A unit originating a message is calle TRANSMITTER of that message. The unit stays TRANSMITTER until the bus is ile or the unit loses ARBITRATION. RECEIVER A unit is calle RECEIVER of a message, if it is not TRANSMITTER of that message an the bus is not ile.

Message Valiation Part A - page 21 4 MESSAGE VALIDATION The point of time at which a message is taken to be vali, is ifferent for the transmitter an the receivers of the message. Transmitter: The message is vali for the transmitter, if there is no error until the en of END OF FRAME. If a message is corrupte, retransmission will follow automatically an accoring to prioritization. In orer to be able to compete for bus access with other messages, retransmission has to start as soon as the bus is ile. Receivers: The message is vali for the receivers, if there is no error until the last but one bit of END OF FRAME.

5 CODING BIT STREAM CODING Coing Part A - page 22 The frame segments START OF FRAME, ARBITRATION FIELD, CONTROL FIELD, DATA FIELD an CRC SEQUENCE are coe by the metho of bit stuffing. Whenever a transmitter etects five consecutive bits of ientical value in the bit stream to be transmitte it automatically inserts a complementary bit in the actual transmitte bit stream. The remaining bit fiels of the DATA FRAME or REMOTE FRAME (CRC DELIMITER, ACK FIELD, an END OF FRAME) are of fixe form an not stuffe. The ERROR FRAME an the OVERLOAD FRAME are of fixe form as well an not coe by the metho of bit stuffing. The bit stream in a message is coe accoring to the Non-Return-to-Zero (NRZ) metho. This means that uring the total bit time the generate bit level is either ominant or recessive.

6 ERROR HANDLING 6.1 Error Detection Error Hanling Part A - page 23 There are 5 ifferent error types (which are not mutually exclusive): BIT ERROR A unit that is sening a bit on the bus also monitors the bus. A BIT ERROR has to be etecte at that bit time, when the bit value that is monitore is ifferent from the bit value that is sent. An exception is the sening of a recessive bit uring the stuffe bit stream of the ARBITRATION FIELD or uring the ACK SLOT. Then no BIT ERROR occurs when a ominant bit is monitore. A TRANSMITTER sening a PASSIVE ERROR FLAG an etecting a ominant bit oes not interpret this as a BIT ERROR. STUFF ERROR A STUFF ERROR has to be etecte at the bit time of the 6th consecutive equal bit level in a message fiel that shoul be coe by the metho of bit stuffing. CRC ERROR The CRC sequence consists of the result of the CRC calculation by the transmitter. The receivers calculate the CRC in the same way as the transmitter. A CRC ERROR has to be etecte, if the calculate result is not the same as that receive in the CRC sequence. FORM ERROR A FORM ERROR has to be etecte when a fixe-form bit fiel contains one or more illegal bits. ACKNOWLEDGMENT ERROR An ACKNOWLEDGMENT ERROR has to be etecte by a transmitter whenever it oes not monitor a ominant bit uring the ACK SLOT. 6.2 Error Signalling A station etecting an error conition signals this by transmitting an ERROR FLAG. For an error active noe it is an ACTIVE ERROR FLAG, for an error passive noe it is a PASSIVE ERROR FLAG. Whenever a BIT ERROR, a STUFF ERROR, a FORM ERROR or an ACKNOWLEDGMENT ERROR is etecte by any station, transmission of an ERROR FLAG is starte at the respective station at the next bit. Whenever a CRC ERROR is etecte, transmission of an ERROR FLAG starts at the bit following the ACK DELIMITER, unless an ERROR FLAG for another conition has alreay been starte.

Fault Confinement Part A - page 24 7 FAULT CONFINEMENT With respect to fault confinement a unit may be in one of three states: error active error passive bus off An error active unit can normally take part in bus communication an sens an ACTIVE ERROR FLAG when an error has been etecte. An error passive unit must not sen an ACTIVE ERROR FLAG. It takes part in bus communication but when an error has been etecte only a PASSIVE ERROR FLAG is sent. Also after a transmission, an error passive unit will wait before initiating a further transmission. (See SUSPEND TRANSMISSION) A bus off unit is not allowe to have any influence on the bus. (E.g. output rivers switche off.) For fault confinement two counts are implemente in every bus unit: 1) TRANSMIT ERROR COUNT 2) RECEIVE ERROR COUNT These counts are moifie accoring to the following rules: (note that more than one rule may apply uring a given message transfer) 1. When a RECEIVER etects an error, the RECEIVE ERROR COUNT will be increase by 1, except when the etecte error was a BIT ERROR uring the sening of an ACTIVE ERROR FLAG or an OVERLOAD FLAG. 2. When a RECEIVER etects a ominant bit as the first bit after sening an ERROR FLAG the RECEIVE ERROR COUNT will be increase by 8. 3. When a TRANSMITTER sens an ERROR FLAG the TRANSMIT ERROR COUNT is increase by 8. Exception 1: If the TRANSMITTER is error passive an etects an ACKNOWLEDGMENT

Fault Confinement Part A - page 25 ERROR because of not etecting a ominant ACK an oes not etect a ominant bit while sening its PASSIVE ERROR FLAG. Exception 2: If the TRANSMITTER sens an ERROR FLAG because a STUFF ERROR occurre uring ARBITRATION whereby the STUFFBIT is locate before the RTR bit, an shoul have been recessive, an has been sent as recessive but monitore as ominant. In exceptions 1 an 2 the TRANSMIT ERROR COUNT is not change. 4. If an TRANSMITTER etects a BIT ERROR while sening an ACTIVE ERROR FLAG or an OVERLOAD FLAG the TRANSMIT ERROR COUNT is increase by 8. 5. If an RECEIVER etects a BIT ERROR while sening an ACTIVE ERROR FLAG or an OVERLOAD FLAG the RECEIVE ERROR COUNT is increase by 8. 6. Any noe tolerates up to 7 consecutive ominant bits after sening an ACTIVE ERROR FLAG, PASSIVE ERROR FLAG or OVERLOAD FLAG. After etecting the 14th consecutive ominant bit (in case of an ACTIVE ERROR FLAG or an OVERLOAD FLAG) or after etecting the 8th consecutive ominant bit following a PASSIVE ERROR FLAG, an after each sequence of aitional eight consecutive ominant bits every TRANSMITTER increases its TRANSMIT ERROR COUNT by 8 an every RECEIVER increases its RECEIVE ERROR COUNT by 8. 7. After the successful transmission of a message (getting ACK an no error until END OF FRAME is finishe) the TRANSMIT ERROR COUNT is ecrease by 1 unless it was alreay 0. 8. After the successful reception of a message (reception without error up to the ACK SLOT an the successful sening of the ACK bit), the RECEIVE ERROR COUNT is ecrease by 1, if it was between 1 an 127. If the RECEIVE ERROR COUNT was 0, it stays 0, an if it was greater than 127, then it will be set to a value between 119 an 127. 9. A noe is error passive when the TRANSMIT ERROR COUNT equals or excees 128, or when the RECEIVE ERROR COUNT equals or excees 128. An error conition letting a noe become error passive causes the noe to sen an ACTIVE ERROR FLAG.

Fault Confinement Part A - page 26 10. A noe is bus off when the TRANSMIT ERROR COUNT is greater than or equal to 256. 11.An error passive noe becomes error active again when both the TRANSMIT ERROR COUNT an the RECEIVE ERROR COUNT are less than or equal to 127. 12.An noe which is bus off is permitte to become error active (no longer bus off ) with its error counters both set to 0 after 128 occurrence of 11 consecutive recessive bits have been monitore on the bus. Note: An error count value greater than about 96 inicates a heavily isturbe bus. It may be of avantage to provie means to test for this conition. Note: Start-up / Wake-up: If uring start-up only 1 noe is online, an if this noe transmits some message, it will get no acknowlegment, etect an error an repeat the message. It can become error passive but not bus off ue to this reason.

Fault Confinement Part A - page 27 8 BIT TIMING REQUIREMENTS NOMINAL BIT RATE The Nominal Bit Rate is the number of bits per secon transmitte in the absence of resynchronization by an ieal transmitter. NOMINAL BIT TIME NOMINAL BIT TIME = 1 / NOMINAL BIT RATE The Nominal Bit Time can be thought of as being ivie into separate non-overlapping time segments. These segments - SYNCHRONIZATION SEGMENT (SYNC_SEG) - PROPAGATION TIME SEGMENT (PROP_SEG) - PHASE BUFFER SEGMENT1 (PHASE_SEG1) - PHASE BUFFER SEGMENT2 (PHASE_SEG2) form the bit time as shown in figure 1. NOMINAL BIT TIME SYNC_SEG PROP_SEG PHASE_SEG1 PHASE_SEG2 Fig. 1 Partition of the Bit Time Sample Point SYNC SEG This part of the bit time is use to synchronize the various noes on the bus. An ege is expecte to lie within this segment. PROP SEG This part of the bit time is use to compensate for the physical elay times within the network.

Bit Timing Part A - page 28 It is twice the sum of the signal s propagation time on the bus line, the input comparator elay, an the output river elay. PHASE SEG1, PHASE SEG2 These Phase-Buffer-Segments are use to compensate for ege phase errors. These segments can be lengthene or shortene by resynchronization. SAMPLE POINT The SAMPLE POINT is the point of time at which the bus level is rea an interprete as the value of that respective bit. It s location is at the en of PHASE_SEG1. INFORMATION PROCESSING TIME The INFORMATION PROCESSING TIME is the time segment starting with the SAMPLE POINT reserve for calculation the subsequent bit level. TIME QUANTUM The TIME QUANTUM is a fixe unit of time erive from the oscillator perio. There exists a programmable prescaler, with integral values, ranging at least from 1 to 32. Starting with the MINIMUM TIME QUANTUM, the TIME QUANTUM can have a length of TIME QUANTUM = m * MINIMUM TIME QUANTUM with m the value of the prescaler. Length of Time Segments SYNC_SEG is 1 TIME QUANTUM long. PROP_SEG is programmable to be 1,2,...,8 TIME QUANTA long. PHASE_SEG1 is programmable to be 1,2,...,8 TIME QUANTA long. PHASE_SEG2 is the maximum of PHASE_SEG1 an the INFORMATION PROCESSING TIME The INFORMATION PROCESSING TIME is less than or equal to 2 TIME QUANTA long. The total number of TIME QUANTA in a bit time has to be programmable at least from 8 to 25.

Bit Timing Part A - page 29 SYNCHRONIZATION HARD SYNCHRONIZATION After a HARD SYNCHRONIZATION the internal bit time is restarte with SYNC_SEG. Thus HARD SYNCHRONIZATION forces the ege which has cause the HARD SYNCHRONIZATION to lie within the SYNCHRONIZATION SEGMENT of the restarte bit time. RESYNCHRONIZATION JUMP WIDTH As a result of RESYNCHRONIZATION PHASE_SEG1 may be lengthene or PHASE_SEG2 may be shortene. The amount of lengthening or shortening of the PHASE BUFFER SEGMENTs has an upper boun given by the RESYNCHRONIZATION JUMP WIDTH. The RESYNCHRONIZATION JUMP WIDTH shall be programmable between 1 an min(4, PHASE_SEG1). Clocking information may be erive from transitions from one bit value to the other. The property that only a fixe maximum number of successive bits have the same value provies the possibility of resynchronizing a bus unit to the bit stream uring a frame. The maximum length between two transitions which can be use for resynchronization is 29 bit times. PHASE ERROR of an ege The PHASE ERROR of an ege is given by the position of the ege relative to SYNC_SEG, measure in TIME QUANTA. The sign of PHASE ERROR is efine as follows: e = 0 if the ege lies within SYNC_SEG. e > 0 if the ege lies before the SAMPLE POINT. e < 0 if the ege lies after the SAMPLE POINT of the previous bit. RESYNCHRONIZATION The effect of a RESYNCHRONIZATION is the same as that of a HARD SYNCHRONIZATION, when the magnitue of the PHASE ERROR of the ege which causes the RESYNCHRONIZATION is less than or equal to the programme value of the RESYNCHRONIZATION JUMP WIDTH. When the magnitue of the PHASE ERROR is larger than the RESYNCHRONIZATION JUMP WIDTH, an if the PHASE ERROR is positive, then PHASE_SEG1 is lengthene by an amount equal to the RESYNCHRONIZATION JUMP WIDTH. an if the PHASE ERROR is negative, then PHASE_SEG2 is shortene by an amount equal to the RESYNCHRONIZATION JUMP WIDTH.

Bit Timing Part A - page 30 SYNCHRONIZATION RULES HARD SYNCHRONIZATION an RESYNCHRONIZATION are the two forms of SYNCHRONIZATION. They obey the following rules: 1. Only one SYNCHRONIZATION within one bit time is allowe. 2. An ege will be use for SYNCHRONIZATION only if the value etecte at the previous SAMPLE POINT (previous rea bus value) iffers from the bus value immeiately after the ege. 3. HARD SYNCHRONIZATION is performe whenever there is a recessive to ominant ege uring BUS IDLE. 4. All other recessive to ominant eges (an optionally ominant to recessive eges in case of low bit rates) fulfilling the rules 1 an 2 will be use for RESYNCHRONIZATION with the exception that a noe transmitting a ominant bit will not perform a RESYNCHRONIZATION as a result of a recessive to ominant ege with a positive PHASE ERROR, if only recessive to ominant eges are use for resynchronization.

Oscillator Tolerance Part A - page 31 9 INCREASING CAN OSCILLATOR TOLERANCE This section escribes an upwars compatible moification of the CAN protocol, as specifie in sections 1 to 8. 9.1 Protocol Moifications In orer to increase the maximum oscillator tolerance from the 0.5% currently possible to 1.5%, the following moifications, which are upwars compatible to the existing CAN specification, are necessary: [1] If a CAN noe samples a ominant bit at the thir bit of INTERMISSION, then it will interpret this bit as a START OF FRAME bit. [2] If a CAN noe has a message waiting for transmission an it samples a ominant bit at the thir bit of INTERMISSION, it will interpret this as a START OF FRAME bit, an, with the next bit, start transmitting its message with the first bit of the IDENTIFIER without first transmitting a START OF FRAME bit an without becoming a receiver. [3] If a CAN noe samples a ominant bit at the eighth bit (the last bit) of an ERROR DELIMITER or OVERLOAD DELIMITER, it will, at the next bit, start transmitting an OVERLOAD FRAME (not an ERROR FRAME). The Error Counters will not be incremente. [4] Only recessive to ominant eges will be use for synchronization. In agreement with the existing specification, the following rules are still vali. [5] All CAN controllers synchronize on the START OF FRAME bit with a har synchronization. [6] No CAN controller will sen a START OF FRAME bit until it has counte three recessive bits of INTERMISSION. This moifications allow a maximum oscillator tolerance of 1.58% an the use of a ceramic resonator at a bus spee of up to 125 Kbits/secon. For the full bus spee range of the CAN protocol, still a quartz oscillator is require. The compatibility of the enhance an the existing protocol is maintaine, as long as: [7] CAN controllers with the enhance an existing protocols, use in one an the same network, have all to be provie with a quartz oscillator. The chip with the highest requirement for its oscillator accuracy etermines the oscillator accuracy which is require from all the other noes. Ceramic resonators can only be use when all the noes in the network use the enhance protocol.

Content Part B - page 32 PART B

Introuction Part B - page 33 1 INTRODUCTION...34 2 BASIC CONCEPTS...36 3 MESSAGE TRANSFER...42 3.1 Frame Formats...42 3.2 Frame Types...42 3.2.1 DATA FRAME...42 3.2.2 REMOTE FRAME...49 3.2.3 ERROR FRAME...50 3.2.4 OVERLOAD FRAME...51 3.2.5 INTERFRAME SPACING...53 3.3 Conformance with regar to Frame Formats...55 3.4 Definition of TRANSMITTER / RECEIVER...55 4 MESSAGE FILTERING...56 5 MESSAGE VALIDATION...57 6 CODING...58 7 ERROR HANDLING...59 7.1 Error Detection...59 7.2 Error Signalling...60 8 FAULT CONFINEMENT...61 9 OSCILLATOR TOLERANCE...64 10 BIT TIMING REQUIREMENTS...65

1 INTRODUCTION Introuction Part B - page 34 The Controller Area Network (CAN) is a serial communications protocol which efficiently supports istribute realtime control with a very high level of security. Its omain of application ranges from high spee networks to low cost multiplex wiring. In automotive electronics, engine control units, sensors, anti-ski-systems, etc. are connecte using CAN with bitrates up to 1 Mbit/s. At the same time it is cost effective to buil into vehicle boy electronics, e.g. lamp clusters, electric winows etc. to replace the wiring harness otherwise require. The intention of this specification is to achieve compatibility between any two CAN implementations. Compatibility, however, has ifferent aspects regaring e.g. electrical features an the interpretation of ata to be transferre. To achieve esign transparency an implementation flexibility CAN has been subivie into ifferent layers accoring to the ISO/OSI Reference Moel: the Data Link Layer - the Logical Link Control (LLC) sublayer - the Meium Access Control (MAC) sublayer the Physical Layer Note that in previous versions of the CAN specification the services an functions of the LLC an MAC sublayers of the Data Link Layer ha been escribe in layers enote as object layer an transfer layer. The scope of the LLC sublayer is to provie services for ata transfer an for remote ata request, to ecie which messages receive by the LLC sublayer are actually to be accepte, to provie means for recovery management an overloa notifications. There is much freeom in efining object hanling. The scope of the MAC sublayer mainly is the transfer protocol, i.e. controlling the Framing, performing Arbitration, Error Checking, Error Signalling an Fault Confinement. Within the MAC sublayer it is ecie whether the bus is free for starting a new transmission or whether a reception is just starting. Also some general features of the bit timing are regare as part of the MAC sublayer. It is in the nature of the MAC sublayer that there is no freeom for moifications. The scope of the physical layer is the actual transfer of the bits between the ifferent noes with respect to all electrical properties. Within one network the physical layer, of

Basic Concepts Part B - page 35 course, has to be the same for all noes. There may be, however, much freeom in selecting a physical layer. The scope of this specification is to efine the MAC sublayer an a small part of the LLC sublayer of the Data Link Layer an to escribe the consequences of the CAN protocol on the surrouning layers.

2 BASIC CONCEPTS CAN has the following properties prioritization of messages guarantee of latency times configuration flexibility Basic Concepts Part B - page 36 multicast reception with time synchronization system wie ata consistency multimaster error etection an signalling automatic retransmission of corrupte messages as soon as the bus is ile again istinction between temporary errors an permanent failures of noes an autonomous switching off of efect noes Layere Architecture of CAN accoring to the OSI Reference Moel The Physical Layer efines how signals are actually transmitte an therefore eals with the escription of Bit Timing, Bit Encoing, an Synchronization. Within this specification the Driver/Receiver Characteristics of the Physical Layer are not efine so as to allow transmission meium an signal level implementations to be optimize for their application. The MAC sublayer represents the kernel of the CAN protocol. It presents messages receive from the LLC sublayer an accepts messages to be transmitte to the LLC sublayer. The MAC sublayer is responsible for Message Framing, Arbitration, Acknowlegment, Error Detection an Signalling. The MAC sublayer are supervise by a management entity calle Fault Confinement which is self-checking mechanism for istinguishing short isturbances from permanent failures. The LLC sublayer is concerne with Message Filtering, Overloa Notification an Recovery Management.

Basic Concepts Part B - page 37 Data Link Layer LLC Acceptance Filtering Overloa Notification Recovery Management MAC Data Encapsulation /Decapsulation Frame Coing (Stuffing, Destuffing) Meium Access Management Error Detection Error Signalling Acknowlegment Serialization / Deserialization Supervisor Fault Confinement Physical Layer Bit Encoing/Decoing Bit Timing Synchronization Bus Failure Management Driver/Receiver Characteristics LLC = Logical Link Control MAC = Meium Access Control

Basic Concepts Part B - page 38 The scope of this specification is to efine the Data Link Layer an the consequences of the CAN protocol on the surrouning layers. Messages Information on the bus is sent in fixe format messages of ifferent but limite length (see section 3: Message Transfer). When the bus is free any connecte unit may start to transmit a new message. Information Routing In CAN systems a CAN noe oes not make use of any information about the system configuration (e.g. station aresses). This has several important consequences. System Flexibility: Noes can be ae to the CAN network without requiring any change in the software or harware of any noe an application layer. Message Routing: The content of a message is name by an IDENTIFIER. The IDENTIFIER oes not inicate the estination of the message, but escribes the meaning of the ata, so that all noes in the network are able to ecie by Message Filtering whether the ata is to be acte upon by them or not. Multicast: As a consequence of the concept of Message Filtering any number of noes can receive an simultaneously act upon the same message. Data Consistency: Within a CAN network it is guarantee that a message is simultaneously accepte either by all noes or by no noe. Thus ata consistency of a system is achieve by the concepts of multicast an by error hanling. Bit rate The spee of CAN may be ifferent in ifferent systems. However, in a given system the bit-rate is uniform an fixe. Priorities The IDENTIFIER efines a static message priority uring bus access.

Basic Concepts Part B - page 39 Remote Data Request By sening a REMOTE FRAME a noe requiring ata may request another noe to sen the corresponing DATA FRAME. The DATA FRAME an the corresponing REMOTE FRAME are name by the same IDENTIFIER. Multimaster When the bus is free any unit may start to transmit a message. The unit with the message of higher priority to be transmitte gains bus access. Arbitration Whenever the bus is free, any unit may start to transmit a message. If 2 or more units start transmitting messages at the same time, the bus access conflict is resolve by bitwise arbitration using the IDENTIFIER. The mechanism of arbitration guarantees that neither information nor time is lost. If a DATA FRAME an a REMOTE FRAME with the same IDENTIFIER are initiate at the same time, the DATA FRAME prevails over the REMOTE FRAME. During arbitration every transmitter compares the level of the bit transmitte with the level that is monitore on the bus. If these levels are equal the unit may continue to sen. When a recessive level is sent an a ominant level is monitore (see Bus Values), the unit has lost arbitration an must withraw without sening one more bit. Safety In orer to achieve the utmost safety of ata transfer, powerful measures for error etection, signalling an self-checking are implemente in every CAN noe. Error Detection For etecting errors the following measures have been taken: - Monitoring (transmitters compare the bit levels to be transmitte with the bit levels etecte on the bus) - Cyclic Reunancy Check - Bit Stuffing - Message Frame Check Performance of Error Detection The error etection mechanisms have the following properties: - all global errors are etecte. - all local errors at transmitters are etecte. - up to 5 ranomly istribute errors in a message are etecte. - burst errors of length less than 15 in a message are etecte. - errors of any o number in a message are etecte.

Basic Concepts Part B - page 40 Total resiual error probability for unetecte corrupte messages: less than message error rate * 4.7 * 10-11. Error Signalling an Recovery Time Corrupte messages are flagge by any noe etecting an error. Such messages are aborte an will be retransmitte automatically. The recovery time from etecting an error until the start of the next message is at most 31 bit times, if there is no further error. Fault Confinement CAN noes are able to istinguish short isturbances from permanent failures. Defective noes are switche off. Connections The CAN serial communication link is a bus to which a number of units may be connecte. This number has no theoretical limit. Practically the total number of units will be limite by elay times an/or electrical loas on the bus line. Single Channel The bus consists of a single channel that carries bits. From this ata resynchronization information can be erive. The way in which this channel is implemente is not fixe in this specification. E.g. single wire (plus groun), two ifferential wires, optical fibres, etc. Bus values The bus can have one of two complementary logical values: ominant or recessive. During simultaneous transmission of ominant an recessive bits, the resulting bus value will be ominant. For example, in case of a wire-and implementation of the bus, the ominant level woul be represente by a logical 0 an the recessive level by a logical 1. Physical states (e.g. electrical voltage, light) that represent the logical levels are not given in this specification. Acknowlegment All receivers check the consistency of the message being receive an will acknowlege a consistent message an flag an inconsistent message. Sleep Moe / Wake-up To reuce the system s power consumption, a CAN-evice may be set into sleep moe

Message Transfer Part B - page 41 without any internal activity an with isconnecte bus rivers. The sleep moe is finishe with a wake-up by any bus activity or by internal conitions of the system. On wake-up, the internal activity is restarte, although the MAC sublayer will be waiting for the system s oscillator to stabilize an it will then wait until it has synchronize itself to the bus activity (by checking for eleven consecutive recessive bits), before the bus rivers are set to "on-bus" again. Oscillator Tolerance The Bit Timing requirements allow ceramic resonators to be use in applications with transmission rates of up to 125kbit/s as a rule of thumb; for a more precise evaluation refer to Dais, S; Chapman, M; Impact of Bit Representation on Transport Capacity an Clock Accuracy in Serial Data Streams, SAE Technical Paper Series 890532, Multiplexing in Automobiles SP-773 March 1989 For the full bus spee range of the CAN protocol, a quartz oscillator is require.

Data Frame Part B - page 42 3 MESSAGE TRANSFER 3.1 Frame Formats There are two ifferent formats which iffer in the length of the IDENTIFIER fiel: Frames with the number of 11 bit IDENTIFIER are enote Stanar Frames. In contrast, frames containing 29 bit IDENTIFIER are enote Extene Frames. 3.2 Frame Types Message transfer is manifeste an controlle by four ifferent frame types: A DATA FRAME carries ata from a transmitter to the receivers. A REMOTE FRAME is transmitte by a bus unit to request the transmission of the DATA FRAME with the same IDENTIFIER. An ERROR FRAME is transmitte by any unit on etecting a bus error. An OVERLOAD FRAME is use to provie for an extra elay between the preceing an the succeeing DATA or REMOTE FRAMEs. DATA FRAMEs an REMOTE FRAMEs can be use both in Stanar Frame Format an Extene Frame Format; they are separate from preceing frames by an INTERFRAME SPACE. 3.2.1 DATA FRAME A DATA FRAME is compose of seven ifferent bit fiels: START OF FRAME, ARBITRATION FIELD, CONTROL FIELD, DATA FIELD, CRC FIELD, ACK FIELD, END OF FRAME. The DATA FIELD can be of length zero.

Data Frame Part B - page 43 Interframe Space DATA FRAME Interframe Space Start of Frame or Overloa Frame Arbitration Fiel Control Fiel Data Fiel CRC Fiel ACK Fiel En of Frame START OF FRAME (Stanar Format as well as Extene Format) The START OF FRAME (SOF) marks the beginning of DATA FRAMES an REMOTE FRAMEs. It consists of a single ominant bit. A station is only allowe to start transmission when the bus is ile (see INTERFRAME Spacing ). All stations have to synchronize to the leaing ege cause by START OF FRAME (see HARD SYNCHRONIZATION ) of the station starting transmission first. ARBITRATION FIELD The format of the ARBITRATION FIELD is ifferent for Stanar Format an Extene Format Frames. - In Stanar Format the ARBITRATION FIELD consists of the 11 bit IDENTIFIER an the RTR-BIT. The IDENTIFIER bits are enote ID-28... ID-18. - In Extene Format the ARBITRATION FIELD consists of the 29 bit IDENTIFIER, the SRR-Bit, the IDE-Bit, an the RTR-BIT. The IDENTIFIER bits are enote ID-28... ID-0.

Data Frame Part B - page 44 In orer to istinguish between Stanar Format an Extene Format the reserve bit r1 in previous CAN specifications version 1.0-1.2 now is enote as IDE Bit. Stanar Format Arbitration Fiel Control Fiel Data Fiel S O F 11 bit IDENTIFIER R T R I D E r 0 DLC Extene Format Arbitration Fiel Control Fiel Data Fiel S O F 11 bit IDENTIFIER S R R I D E 18 bit IDENTIFIER R T R r 1 r 0 DLC IDENTIFIER IDENTIFIER - Stanar Format The IDENTIFIER s length is 11 bits an correspons to the Base ID in Extene Format. These bits are transmitte in the orer from ID-28 to ID-18. The least significant bit is ID-18. The 7 most significant bits (ID-28 - ID-22) must not be all recessive. IDENTIFIER - Extene Format In contrast to the Stanar Format the Extene Format consists of 29 bits. The format comprises two sections: Base ID with 11 bits an the Extene ID with 18 bits

Data Frame Part B - page 45 Base ID The Base ID consists of 11 bits. It is transmitte in the orer from ID-28 to ID-18. It is equivalent to format of the Stanar Ientifier. The Base ID efines the Extene Frame s base priority. Extene ID The Extene ID consists of 18 bits. It is transmitte in the orer of ID-17 to ID-0. In a Stanar Frame the IDENTIFIER is followe by the RTR bit. RTR BIT (Stanar Format as well as Extene Format) Remote Transmission Request BIT In DATA FRAMEs the RTR BIT has to be ominant. Within a REMOTE FRAME the RTR BIT has to be recessive. In an Extene Frame the Base ID is transmitte first, followe by the IDE bit an the SRR bit. The Extene ID is transmitte after the SRR bit. SRR BIT (Extene Format) Substitute Remote Request BIT The SRR is a recessive bit. It is transmitte in Extene Frames at the position of the RTR bit in Stanar Frames an so substitutes the RTR-Bit in the Stanar Frame. Therefore, collisions of a Stanar Frame an an Extene Frame, the Base ID (see Extene IDENTIFIER below) of which is the same as the Stanar Frame s Ientifier, are resolve in such a way that the Stanar Frame prevails the Extene Frame. IDE BIT (Extene Format) Ientifier Extension Bit The IDE Bit belongs to - the ARBITRATION FIELD for the Extene Format - the Control Fiel for the Stanar Format The IDE bit in the Stanar Format is transmitte ominant, whereas in the Extene Format the IDE bit is recessive. CONTROL FIELD (Stanar Format as well as Extene Format) The CONTROL FIELD consists of six bits. The format of the CONTROL FIELD is ifferent for Stanar Format an Extene Format. Frames in Stanar Format inclue the DATA LENGTH CODE, the IDE bit, which is transmitte ominant (see

Data Frame Part B - page 46 above), an the reserve bit r0. Frames in the Extene Format inclue the DATA LENGTH CODE an two reserve bits r1 an r0. The reserve bits have to be sent ominant, but receivers accept ominant an recessive bits in all combinations. Arbitration Fiel CONTROL FIELD Stanar Format an Extene Format IDE / r1 r0 DLC3 DLC2 DLC1 DLC0 Data Fiel or CRC Fiel reserve bits Data Length Coe DATA LENGTH CODE (Stanar Format as well as Extene Format) The number of bytes in the DATA FIELD is inicate by the DATA LENGTH CODE. This DATA LENGTH CODE is 4 bits wie an is transmitte within the CONTROL FIELD. Coing of the number of ata bytes by the DATA LENGTH CODE abbreviations: ominant r recessive Number of Data Bytes Data Length Coe DLC3 DLC2 DLC1 DLC0 0 1 r 2 r 3 r r 4 r 5 r r 6 r r 7 r r r 8 r

Data Frame Part B - page 47 DATA FRAME: amissible numbers of ata bytes: {0,1,...,7,8}. Other values may not be use. DATA FIELD (Stanar Format as well as Extene Format) The DATA FIELD consists of the ata to be transferre within a DATA FRAME. It can contain from 0 to 8 bytes, which each contain 8 bits which are transferre MSB first. CRC FIELD (Stanar Format as well as Extene Format) contains the CRC SEQUENCE followe by a CRC DELIMITER. Data or Control Fiel CRC FIELD Ack Fiel CRC Sequence CRC Delimiter CRC SEQUENCE (Stanar Format as well as Extene Format) The frame check sequence is erive from a cyclic reunancy coe best suite for frames with bit counts less than 127 bits (BCH Coe). In orer to carry out the CRC calculation the polynomial to be ivie is efine as the polynomial, the coefficients of which are given by the estuffe bit stream consisting of START OF FRAME, ARBITRATION FIELD, CONTROL FIELD, DATA FIELD (if present) an, for the 15 lowest coefficients, by 0. This polynomial is ivie (the coefficients are calculate moulo-2) by the generator-polynomial: X 15 + X 14 + X 10 + X 8 + X 7 + X 4 + X 3 + 1. The remainer of this polynomial ivision is the CRC SEQUENCE transmitte over the bus. In orer to implement this function, a 15 bit shift register CRC_RG(14:0) can be use. If NXTBIT enotes the next bit of the bit stream, given by the estuffe bit sequence from START OF FRAME until the en of the DATA FIELD, the CRC SEQUENCE is calculate as follows: CRC_RG = 0; // initialize shift register

Remote Frame Part B - page 48 REPEAT CRCNXT = NXTBIT EXOR CRC_RG(14); CRC_RG(14:1) = CRC_RG(13:0); // shift left by CRC_RG(0) = 0; // 1 position IF CRCNXT THEN CRC_RG(14:0) = CRC_RG(14:0) EXOR (4599hex); ENDIF UNTIL (CRC SEQUENCE starts or there is an ERROR conition) After the transmission / reception of the last bit of the DATA FIELD, CRC_RG contains the CRC sequence. CRC DELIMITER (Stanar Format as well as Extene Format) The CRC SEQUENCE is followe by the CRC DELIMITER which consists of a single recessive bit. ACK FIELD (Stanar Format as well as Extene Format) The ACK FIELD is two bits long an contains the ACK SLOT an the ACK DELIMITER. In the ACK FIELD the transmitting station sens two recessive bits. A RECEIVER which has receive a vali message correctly, reports this to the TRANSMITTER by sening a ominant bit uring the ACK SLOT (it sens ACK ). CRC Fiel ACK FIELD En of Frame ACK Slot ACK Delimiter ACK SLOT All stations having receive the matching CRC SEQUENCE report this within the ACK SLOT by superscribing the recessive bit of the TRANSMITTER by a ominant bit. ACK DELIMITER The ACK DELIMITER is the secon bit of the ACK FIELD an has to be a recessive bit. As a consequence, the ACK SLOT is surroune by two recessive bits (CRC DELIMITER, ACK DELIMITER).

Error Frame Part B - page 49 END OF FRAME (Stanar Format as well as Extene Format) Each DATA FRAME an REMOTE FRAME is elimite by a flag sequence consisting of seven recessive bits. 3.2.2 REMOTE FRAME A station acting as a RECEIVER for certain ata can initiate the transmission of the respective ata by its source noe by sening a REMOTE FRAME. A REMOTE FRAME exists in both Stanar Format an Extene Format. In both cases it is compose of six ifferent bit fiels: START OF FRAME, ARBITRATION FIELD, CONTROL FIELD, CRC FIELD, ACK FIELD, END OF FRAME. Contrary to DATA FRAMEs, the RTR bit of REMOTE FRAMEs is recessive. There is no DATA FIELD, inepenent of the values of the DATA LENGTH CODE which may be signe any value within the amissible range 0...8. The value is the DATA LENGTH CODE of the corresponing DATA FRAME. Inter Frame Space REMOTE FRAME Inter Frame Space or Overloa Frame Start of Frame Arbitration Fiel Control Fiel CRC Fiel ACK Fiel En of Frame

Overloa Frame Part B - page 50 The polarity of the RTR bit inicates whether a transmitte frame is a DATA FRAME (RTR bit ominant ) or a REMOTE FRAME (RTR bit recessive ). 3.2.3 ERROR FRAME The ERROR FRAME consists of two ifferent fiels. The first fiel is given by the superposition of ERROR FLAGs contribute from ifferent stations. The following secon fiel is the ERROR DELIMITER. Data Frame Error Flag ERROR FRAME Interframe Space or Overloa Frame superposition of Error Flags Error Delimiter In orer to terminate an ERROR FRAME correctly, an error passive noe may nee the bus to be bus ile for at least 3 bit times (if there is a local error at an error passive receiver). Therefore the bus shoul not be loae to 100%. ERROR FLAG There are 2 forms of an ERROR FLAG: an ACTIVE ERROR FLAG an a PASSIVE ERROR FLAG. 1. The ACTIVE ERROR FLAG consists of six consecutive ominant bits. 2. The PASSIVE ERROR FLAG consists of six consecutive recessive bits unless it is overwritten by ominant bits from other noes. An error active station etecting an error conition signals this by transmission of an ACTIVE ERROR FLAG. The ERROR FLAG s form violates the law of bit stuffing (see CODING) applie to all fiels from START OF FRAME to CRC DELIMITER or estroys the fixe form ACK FIELD or END OF FRAME fiel. As a consequence, all other stations etect an error conition an on their part start transmission of an ERROR

Overloa Frame Part B - page 51 FLAG. So the sequence of ominant bits which actually can be monitore on the bus results from a superposition of ifferent ERROR FLAGs transmitte by iniviual stations. The total length of this sequence varies between a minimum of six an a maximum of twelve bits. An error passive station etecting an error conition tries to signal this by transmission of a PASSIVE ERROR FLAG. The error passive station waits for six consecutive bits of equal polarity, beginning at the start of the PASSIVE ERROR FLAG. The PASSIVE ERROR FLAG is complete when these 6 equal bits have been etecte. ERROR DELIMITER The ERROR DELIMITER consists of eight recessive bits. After transmission of an ERROR FLAG each station sens recessive bits an monitors the bus until it etects a recessive bit. Afterwars it starts transmitting seven more recessive bits. 3.2.4 OVERLOAD FRAME The OVERLOAD FRAME contains the two bit fiels OVERLOAD FLAG an OVERLOAD DELIMITER. There are two kins of OVERLOAD conitions, which both lea to the transmission of an OVERLOAD FLAG: 1. The internal conitions of a receiver, which requires a elay of the next DATA FRAME or REMOTE FRAME. 2. Detection of a ominant bit at the first an secon bit of INTERMISSION. 3. If a CAN noe samples a ominant bit at the eighth bit (the last bit) of an ERROR DELIMITER or OVERLOAD DELIMITER, it will start transmitting an OVERLOAD FRAME (not an ERROR FRAME). The Error Counters will not be incremente. The start of an OVERLOAD FRAME ue to OVERLOAD conition 1 is only allowe to be starte at the first bit time of an expecte INTERMISSION, whereas OVERLOAD FRAMEs ue to OVERLOAD conition 2 an conition 3 start one bit after etecting the ominant bit.

Interframe Space Part B - page 52 At most two OVERLOAD FRAMEs may be generate to elay the next DATA or REMOTE FRAME. En of Frame or Error Delimiter or Overloa Delimiter Overloa Flag OVERLOAD FRAME Inter Frame Space or Overloa Frame superposition of Overloa Flags Overloa Delimiter OVERLOAD FLAG consists of six ominant bits. The overall form correspons to that of the ACTIVE ERROR FLAG. The OVERLOAD FLAG s form estroys the fixe form of the INTERMISSION fiel. As a consequence, all other stations also etect an OVERLOAD conition an on their part start transmission of an OVERLOAD FLAG. In case that there is a ominant bit etecte uring the 3r bit of INTERMISSION then it will interpret this bit as START OF FRAME. Note: Controllers base on the CAN Specification version 1.0 an 1.1 have another interpretation of the 3r bit if INTERMISSION: If a ominant bit was etecte locally at some noe, the other noes will not interpret the OVERLOAD FLAG correctly, but interpret the first of these six ominant bits as START OF FRAME; the sixth ominant bit violates the rule of bit stuffing causing an error conition. OVERLOAD DELIMITER consists of eight recessive bits. The OVERLOAD DELIMITER is of the same form as the ERROR DELIMITER. After transmission of an OVERLOAD FLAG the station monitors the bus until it etects a transition from a ominant to a recessive bit. At this point of time every bus station has finishe sening its OVERLOAD FLAG an all stations start transmission of seven more recessive bits in coincience.

Interframe Space Part B - page 53 3.2.5 INTERFRAME SPACING DATA FRAMEs an REMOTE FRAMEs are separate from preceing frames whatever type they are (DATA FRAME, REMOTE FRAME, ERROR FRAME, OVERLOAD FRAME) by a bit fiel calle INTERFRAME SPACE. In contrast, OVERLOAD FRAMEs an ERROR FRAMEs are not precee by an INTERFRAME SPACE an multiple OVERLOAD FRAMEs are not separate by an INTERFRAME SPACE. INTERFRAME SPACE contains the bit fiels INTERMISSION an BUS IDLE an, for error passive stations, which have been TRANSMITTER of the previous message, SUSPEND TRANSMISSION. For stations which are not error passive or have been RECEIVER of the previous message: Frame INTERFRAME SPACE Frame Intermission Bus Ile For error passive stations which have been TRANSMITTER of the previous message: Frame INTERFRAME SPACE Frame Intermission Bus Ile Suspen Transmission INTERMISSION consists of three recessive bits. During INTERMISSION the only action to be taken is signalling an OVERLOAD conition an no station is allowe to actively start transmission of a DATA FRAME or REMOTE FRAME.

Conformance Part B - page 54 Note: If a CAN noe has a message waiting for transmission an it samples a ominant bit at the thir bit of INTERMISSION, it will interpret this as a START OF FRAME bit, an, with the next bit, start transmitting its message with the first bit of its IDENTIFIER without first transmitting a START OF FRAME bit an without becoming receiver. BUS IDLE The perio of BUS IDLE may be of arbitrary length. The bus is recognize to be free an any station having something to transmit can access the bus. A message, which is pening for transmission uring the transmission of another message, is starte in the first bit following INTERMISSION. The etection of a ominant bit on the bus is interprete as a START OF FRAME. SUSPEND TRANSMISSION After an error passive station has transmitte a message, it sens eight recessive bits following INTERMISSION, before starting to transmit a further message or recognizing the bus to be ile. If meanwhile a transmission (cause by another station) starts, the station will become receiver of this message.

Message Filtering Part B - page 55 3.3 Conformance with regar to Frame Formats The Stanar Format is equivalent to the Data/Remote Frame Format as it is escribe in the CAN Specification 1.2. In contrast the Extene Format is a new feature of the CAN protocol. In orer to allow the esign of relatively simple controllers, the implementation of the Extene Format to its full exten is not require (e.g. sen messages or accept ata from messages in Extene Format), whereas the Stanar Format must be supporte without restriction. New controllers are consiere to be in conformance with this CAN Specification, if they have at least the following properties with respect to the Frame Formats efine in 3.1 an 3.2: - Every new controller supports the Stanar Format; - Every new controller can receive messages of the Extene Format. This requires that Extene Frames are not estroye just because of their format. It is, however, not require that the Extene Format must be supporte by new controllers. 3.4 Definition of TRANSMITTER / RECEIVER TRANSMITTER A unit originating a message is calle TRANSMITTER of that message. The unit stays TRANSMITTER until the bus is ile or the unit loses ARBITRATION. RECEIVER A unit is calle RECEIVER of a message, if it is not TRANSMITTER of that message an the bus is not ile.

Message Valiation Part B - page 56 4 MESSAGE FILTERING Message filtering is base upon the whole Ientifier. Optional mask registers that allow any Ientifier bit to be set on t care for message filtering, may be use to select groups of Ientifiers to be mappe into the attache receive buffers. If mask registers are implemente every bit of the mask registers must be programmable, i.e. they can be enable or isable for message filtering. The length of the mask register can comprise the whole IDENTIFIER or only part of it.

5 MESSAGE VALIDATION Coing Part B - page 57 The point of time at which a message is taken to be vali, is ifferent for the transmitter an the receivers of the message. Transmitter: The message is vali for the transmitter, if there is no error until the en of END OF FRAME. If a message is corrupte, retransmission will follow automatically an accoring to prioritization. In orer to be able to compete for bus access with other messages, retransmission has to start as soon as the bus is ile. Receivers: The message is vali for the receivers, if there is no error until the last but one bit of END OF FRAME. The value of the last bit of END OF FRAME is treate as on t care, a ominant value oes not lea to a FORM ERROR (cf. section 7.1).

6 CODING Error Hanling Part B - page 58 BIT STREAM CODING The frame segments START OF FRAME, ARBITRATION FIELD, CONTROL FIELD, DATA FIELD an CRC SEQUENCE are coe by the metho of bit stuffing. Whenever a transmitter etects five consecutive bits of ientical value in the bit stream to be transmitte it automatically inserts a complementary bit in the actual transmitte bit stream. The remaining bit fiels of the DATA FRAME or REMOTE FRAME (CRC DELIMITER, ACK FIELD, an END OF FRAME) are of fixe form an not stuffe. The ERROR FRAME an the OVERLOAD FRAME are of fixe form as well an not coe by the metho of bit stuffing. The bit stream in a message is coe accoring to the Non-Return-to-Zero (NRZ) metho. This means that uring the total bit time the generate bit level is either ominant or recessive.

7 ERROR HANDLING Error Hanling Part B - page 59 7.1 Error Detection There are 5 ifferent error types (which are not mutually exclusive): BIT ERROR A unit that is sening a bit on the bus also monitors the bus. A BIT ERROR has to be etecte at that bit time, when the bit value that is monitore is ifferent from the bit value that is sent. An exception is the sening of a recessive bit uring the stuffe bit stream of the ARBITRATION FIELD or uring the ACK SLOT. Then no BIT ERROR occurs when a ominant bit is monitore. A TRANSMITTER sening a PASSIVE ERROR FLAG an etecting a ominant bit oes not interpret this as a BIT ERROR. STUFF ERROR A STUFF ERROR has to be etecte at the bit time of the 6th consecutive equal bit level in a message fiel that shoul be coe by the metho of bit stuffing. CRC ERROR The CRC sequence consists of the result of the CRC calculation by the transmitter. The receivers calculate the CRC in the same way as the transmitter. A CRC ERROR has to be etecte, if the calculate result is not the same as that receive in the CRC sequence. FORM ERROR A FORM ERROR has to be etecte when a fixe-form bit fiel contains one or more illegal bits. (Note, that for a Receiver a ominant bit uring the last bit of END OR FRAME is not treate as FORM ERROR). ACKNOWLEDGMENT ERROR An ACKNOWLEDGMENT ERROR has to be etecte by a transmitter whenever it oes not monitor a ominant bit uring the ACK SLOT.

7.2 Error Signalling Fault Confinement Part B - page 60 A station etecting an error conition signals this by transmitting an ERROR FLAG. For an error active noe it is an ACTIVE ERROR FLAG, for an error passive noe it is a PASSIVE ERROR FLAG. Whenever a BIT ERROR, a STUFF ERROR, a FORM ERROR or an ACKNOWLEDGMENT ERROR is etecte by any station, transmission of an ERROR FLAG is starte at the respective station at the next bit. Whenever a CRC ERROR is etecte, transmission of an ERROR FLAG starts at the bit following the ACK DELIMITER, unless an ERROR FLAG for another conition has alreay been starte.

Fault Confinement Part B - page 61 8 FAULT CONFINEMENT With respect to fault confinement a unit may be in one of three states: error active error passive bus off An error active unit can normally take part in bus communication an sens an ACTIVE ERROR FLAG when an error has been etecte. An error passive unit must not sen an ACTIVE ERROR FLAG. It takes part in bus communication, but when an error has been etecte only a PASSIVE ERROR FLAG is sent. Also after a transmission, an error passive unit will wait before initiating a further transmission. (See SUSPEND TRANSMISSION) A bus off unit is not allowe to have any influence on the bus. (E.g. output rivers switche off.) For fault confinement two counts are implemente in every bus unit: 1) TRANSMIT ERROR COUNT 2) RECEIVE ERROR COUNT These counts are moifie accoring to the following rules: (note that more than one rule may apply uring a given message transfer) 1. When a RECEIVER etects an error, the RECEIVE ERROR COUNT will be increase by 1, except when the etecte error was a BIT ERROR uring the sening of an ACTIVE ERROR FLAG or an OVERLOAD FLAG. 2. When a RECEIVER etects a ominant bit as the first bit after sening an ERROR FLAG the RECEIVE ERROR COUNT will be increase by 8. 3. When a TRANSMITTER sens an ERROR FLAG the TRANSMIT ERROR COUNT is increase by 8.

Fault Confinement Part B - page 62 Exception 1: If the TRANSMITTER is error passive an etects an ACKNOWLEDGMENT ERROR because of not etecting a ominant ACK an oes not etect a ominant bit while sening its PASSIVE ERROR FLAG. Exception 2: If the TRANSMITTER sens an ERROR FLAG because a STUFF ERROR occurre uring ARBITRATION, an shoul have been recessive, an has been sent as recessive but monitore as ominant. In exceptions 1 an 2 the TRANSMIT ERROR COUNT is not change. 4. If an TRANSMITTER etects a BIT ERROR while sening an ACTIVE ERROR FLAG or an OVERLOAD FLAG the TRANSMIT ERROR COUNT is increase by 8. 5. If an RECEIVER etects a BIT ERROR while sening an ACTIVE ERROR FLAG or an OVERLOAD FLAG the RECEIVE ERROR COUNT is increase by 8. 6. Any noe tolerates up to 7 consecutive ominant bits after sening an ACTIVE ERROR FLAG, PASSIVE ERROR FLAG or OVERLOAD FLAG. After etecting the 14th consecutive ominant bit (in case of an ACTIVE ERROR FLAG or an OVERLOAD FLAG) or after etecting the 8th consecutive ominant bit following a PASSIVE ERROR FLAG, an after each sequence of aitional eight consecutive ominant bits every TRANSMITTER increases its TRANSMIT ERROR COUNT by 8 an every RECEIVER increases its RECEIVE ERROR COUNT by 8. 7. After the successful transmission of a message (getting ACK an no error until END OF FRAME is finishe) the TRANSMIT ERROR COUNT is ecrease by 1 unless it was alreay 0. 8. After the successful reception of a message (reception without error up to the ACK SLOT an the successful sening of the ACK bit), the RECEIVE ERROR COUNT is ecrease by 1, if it was between 1 an 127. If the RECEIVE ERROR COUNT was 0, it stays 0, an if it was greater than 127, then it will be set to a value between 119 an 127. 9. A noe is error passive when the TRANSMIT ERROR COUNT equals or excees 128, or when the RECEIVE ERROR COUNT equals or excees 128. An error conition letting a noe become error passive causes the noe to sen an ACTIVE ERROR FLAG.

Oscillator Tolerance Part B - page 63 10. A noe is bus off when the TRANSMIT ERROR COUNT is greater than or equal to 256. 11.An error passive noe becomes error active again when both the TRANSMIT ERROR COUNT an the RECEIVE ERROR COUNT are less than or equal to 127. 12.An noe which is bus off is permitte to become error active (no longer bus off ) with its error counters both set to 0 after 128 occurrence of 11 consecutive recessive bits have been monitore on the bus. Note: An error count value greater than about 96 inicates a heavily isturbe bus. It may be of avantage to provie means to test for this conition. Note: Start-up / Wake-up: If uring start-up only 1 noe is online, an if this noe transmits some message, it will get no acknowlegment, etect an error an repeat the message. It can become error passive but not bus off ue to this reason.

Bit Timing Part B - page 64 9 OSCILLATOR TOLERANCE A maximum oscillator tolerance of 1.58% is given an therefore the use of a ceramic resonator at a bus spee of up to 125 Kbits/s as a rule of thumb; for a more precise evaluation refer to Dais, S; Chapman, M; Impact of Bit Representation on Transport Capacity an Clock Accuracy in Serial Data Streams, SAE Technical Paper Series 890532, Multiplexing in Automobiles SP-773 March 1989 For the full bus spee range of the CAN protocol, a quartz oscillator is require. The chip of the CAN network with the highest requirement for its oscillator accuracy etermines the oscillator accuracy which is require from all the other noes. Note: Can controllers following this CAN Specification an controllers following the previous versions 1.0 an 1.1, use in one an the same network, must all be equippe with a quartz oscillator. That means ceramic resonators can only be use in a network with all the noes of the network following CAN Protocol Specification versions 1.2 or later.

Bit Timing Part B - page 65 10 BIT TIMING REQUIREMENTS NOMINAL BIT RATE The Nominal Bit Rate is the number of bits per secon transmitte in the absence of resynchronization by an ieal transmitter. NOMINAL BIT TIME NOMINAL BIT TIME = 1 / NOMINAL BIT RATE The Nominal Bit Time can be thought of as being ivie into separate non-overlapping time segments. These segments - SYNCHRONIZATION SEGMENT (SYNC_SEG) - PROPAGATION TIME SEGMENT (PROP_SEG) - PHASE BUFFER SEGMENT1 (PHASE_SEG1) - PHASE BUFFER SEGMENT2 (PHASE_SEG2) form the bit time as shown in figure 1. NOMINAL BIT TIME SYNC_SEG PROP_SEG PHASE_SEG1 PHASE_SEG2 Sample Point Fig. 1 Partition of the Bit Time SYNC SEG This part of the bit time is use to synchronize the various noes on the bus. An ege is expecte to lie within this segment.

Bit Timing Part B - page 66 PROP SEG This part of the bit time is use to compensate for the physical elay times within the network. It is twice the sum of the signal s propagation time on the bus line, the input comparator elay, an the output river elay. PHASE SEG1, PHASE SEG2 These Phase-Buffer-Segments are use to compensate for ege phase errors. These segments can be lengthene or shortene by resynchronization. SAMPLE POINT The SAMPLE POINT is the point of time at which the bus level is rea an interprete as the value of that respective bit. It s location is at the en of PHASE_SEG1. INFORMATION PROCESSING TIME The INFORMATION PROCESSING TIME is the time segment starting with the SAMPLE POINT reserve for calculation the subsequent bit level. TIME QUANTUM The TIME QUANTUM is a fixe unit of time erive from the oscillator perio. There exists a programmable prescaler, with integral values, ranging at least from 1 to 32. Starting with the MINIMUM TIME QUANTUM, the TIME QUANTUM can have a length of TIME QUANTUM = m * MINIMUM TIME QUANTUM with m the value of the prescaler. Length of Time Segments SYNC_SEG is 1 TIME QUANTUM long. PROP_SEG is programmable to be 1,2,...,8 TIME QUANTA long. PHASE_SEG1 is programmable to be 1,2,...,8 TIME QUANTA long. PHASE_SEG2 is the maximum of PHASE_SEG1 an the INFORMATION PROCESSING TIME The INFORMATION PROCESSING TIME is less than or equal to 2 TIME QUANTA long.

Bit Timing Part B - page 67 The total number of TIME QUANTA in a bit time has to be programmable at least from 8 to 25. Note: It is often intene that control units o not make use of ifferent oscillators for the local CPU an its communication evice. Therefore the oscillator frequency of a CAN evice tens to be that of the local CPU an is etermine by the requirements of the control unit. In orer to erive the esire bitrate, programmability of the bittiming is necessary. In case of CAN implementations that are esigne for use without a local CPU the bittiming cannot be programmable. On the other han these evices allow to choose an external oscillator in such a way that the evice is ajuste to the appropriate bit rate so that the programmability is ispensable for such components. The position of the sample point, however, shoul be selecte in common for all noes. Therefore the bit timing of SLIO evices must be compatible to the following efinition of the bit time: Sync- Seg 1 Time Quantum Prop- Seg 1 Time Quantum Phase Buffer Seg. 1 Phase Buffer Seg. 2 4 Time Quanta 1 Bit Time 10 Time Quanta 4 Time Quanta HARD SYNCHRONIZATION After a HARD SYNCHRONIZATION the internal bit time is restarte with SYNC_SEG. Thus HARD SYNCHRONIZATION forces the ege which has cause the HARD SYNCHRONIZATION to lie within the SYNCHRONIZATION SEGMENT of the restarte bit time. RESYNCHRONIZATION JUMP WIDTH As a result of RESYNCHRONIZATION PHASE_SEG1 may be lengthene or PHASE_SEG2 may be shortene. The amount of lengthening or shortening of the PHASE BUFFER SEGMENTs has an upper boun given by the RESYNCHRONIZATION JUMP WIDTH. The RESYNCHRONIZATION JUMP WIDTH shall be programmable between 1 an min(4, PHASE_SEG1). Clocking information may be erive from transitions from one bit value to the other. The property that only a fixe maximum number of successive bits have the same value provies the possibility of resynchronizing a bus unit to the bit stream uring a frame. The maximum length between two transitions which can be use for resynchronization is 29 bit times.

Bit Timing Part B - page 68 PHASE ERROR of an ege The PHASE ERROR of an ege is given by the position of the ege relative to SYNC_SEG, measure in TIME QUANTA. The sign of PHASE ERROR is efine as follows: e = 0 if the ege lies within SYNC_SEG. e > 0 if the ege lies before the SAMPLE POINT. e < 0 if the ege lies after the SAMPLE POINT of the previous bit. RESYNCHRONIZATION The effect of a RESYNCHRONIZATION is the same as that of a HARD SYNCHRONIZATION, when the magnitue of the PHASE ERROR of the ege which causes the RESYNCHRONIZATION is less than or equal to the programme value of the RESYNCHRONIZATION JUMP WIDTH. When the magnitue of the PHASE ERROR is larger than the RESYNCHRONIZATION JUMP WIDTH, an if the PHASE ERROR is positive, then PHASE_SEG1 is lengthene by an amount equal to the RESYNCHRONIZATION JUMP WIDTH. an if the PHASE ERROR is negative, then PHASE_SEG2 is shortene by an amount equal to the RESYNCHRONIZATION JUMP WIDTH. SYNCHRONIZATION RULES HARD SYNCHRONIZATION an RESYNCHRONIZATION are the two forms of SYNCHRONIZATION. They obey the following rules: 1. Only one SYNCHRONIZATION within one bit time is allowe. 2. An ege will be use for SYNCHRONIZATION only if the value etecte at the previous SAMPLE POINT (previous rea bus value) iffers from the bus value immeiately after the ege. 3. HARD SYNCHRONIZATION is performe whenever there is a recessive to ominant ege uring BUS IDLE. 4. All other recessive to ominant eges fulfilling the rules 1 an 2 will be use for RESYNCHRONIZATION with the exception that a noe transmitting a ominant bit will not perform a RESYNCHRONIZATION as a result of a recessive to ominant ege with a positive PHASE ERROR, if only recessive to ominant eges are use for resynchronization.

Differences of CAN Specification Versions 1.2 an 2.0-1 - Differences Amenment of CAN Specification 1.2 has been inclue in part B of this Specification. The respective alterations are marke with an asterisk. page B-25 an page B-62: Alteration of Fault Confinement rule 6 page B-34 to B-37: The layere architecture of CAN was escribe by ifferent layers accoring to the ISO/OSI Reference Moel. page B-41:* Note to Oscillator Tolerance inclue page B-43: The numbering of the Ientifier bits has been change. page B-51:* Accoring to the Oscillator Tolerance a thir conition for generation of an Overloa Frame was introuce. page B-52:* A note was ae because the Interpretation of the last bit of Intermission has been change. page B-54:* A note was introuce because of another interpretation of Start of Frame. page B-55: Section 3.3 Conformance with regar to Frame Formats. page B-56: Chapter 4 Message Filtering was introuce recently. page B-64:* Note to the compatibility of the protocol moifie accoring to the Oscillator Tolerances. page B-67: Note to the bittiming of implementations for ECUs without local CPU.

CAN Specification 2.0 Aenum Mar. 1997-1 - Implementation Guie for the CAN Protocol (Aenum to the protocol specification) The Controller Area Network protocol specification ocument escribes the function of the network on the whole. Aitionally, Bosch provies a Reference CAN Moel to the CAN licensees, supporting the protocol s implementation into the licensees CAN controller noes. This Reference CAN Moel is in some cases, where the reaction to certain conitions was left open, more restricte than the protocol specification. The specific reaction to those conitions efine by the Reference CAN Moel can be regare as a e facto stanar, simplifying the implementation s verification. The verifiction is one by the comparision of the functions of an implementation to the functions of the Reference Moel when applying a set of test conitions. All existing CAN implementations comply to this e facto stanar, incluing 82526 an 82C200, which were esigne before the existence of the Reference CAN Moel. In this paper, the label "Reference CAN Moel" stans for both versions, the "C Reference CAN Moel" an the "VHDL Reference CAN Moel"; their functions are ientical. The aitional restrictions of the Reference CAN Moel apply in the cases of the reception of a Data Length Coe > 8 (1), the reception of a ominant SRR bit in an Extene Frame (2), the reception of a ominant bit as last bit of En Of Frame (3), the increment of the Receive Error Count when it has reache the Error Passive level (4), an the conition for Har Synchronization (5). These cases are explaine in the following, with references to the CAN Specification Revision 2.0, Part B : (1) Accoring to the CAN Specification, no transmitter may sen a frame with DLC > 8. The case of DLC > 8 is not covere by any of the error types efine in chapter 7.1 "Error Detection". It is neither a Bit Error, nor a Stuff Error, nor a CRC Error, nor an Acknowlege Error. It coul be regare as a Form Error, but the DLC belongs to the stuffe Control Fiel an the Form Error is only efine for the fixe-form bit fiels (see chapter 6 "Bit Stream Coing"). So no conition for Error Signalling (see chapter 7.2) is fulfille, the reaction of a receiver to a DLC > 8 is not efine. The Reference CAN Moel efines as e-facto stanar the assumption [if receive DLC > 8 then DLC := 8], expecting to receive 8 ata bytes even when the receive Data Length Coe excees its upper limit of 8. (2) The CAN Specification requires the SRR bit to be sent as recessive. The receiver s reaction to a SRR bit sample as ominant is not efine. It is obviously neither a Bit Error, nor a Stuff Error, nor a CRC Error, nor an Acknowlege Error (see chapter

CAN Specification 2.0 Aenum Mar. 1997-2 - 7.1 "Error Detection"). An, since the SRR bit is locate in a stuffe bit fiel, a SRR bit receive as ominant is not a Form Error. The Reference CAN Moel efines as e-facto stanar that the SRR bit is treate like the Reserve Bits, which have to be sent as ominant, but whose actual value is ignore by receivers. So no transmitter may sen a ominant SRR bit in an Extene Frame while a receiver ignores the value of the SRR bit (but the value is not ignore for bit stuffing an arbitration). Since the SRR bit is receive before the IDE bit, a receiver cannot ecie instantly whether it receives a RTR or a SRR bit. That means only the IDE bit ecies whether the frame is a Stanar Frame or an Extene Frame. (3) Accoring to chapter 5 "Message Valiation", a message is vali for receivers, even when the last bit of En of Frame is receive as ominant. Therefore, this ominant bit is not regare as an error. On the other han, the fixe-form bit fiel En of Frame contains an illegal bit an the receiver of the ominant bit may have lost synchronization, which requires a reaction. The Reference CAN Moel follows the example of chapter 3.2.4 "Overloa Flag", conition 3, where the reception of a ominant bit as the last bit or Error Delimiter of Overloa Delimiter is respone with an Overloa Frame. (4) Theoretically, the Fault Confinement Rules coul increment the Receive Error Count s value over all limits, when an Error Passive receiver etects aitional errors without receiving any error free message. This cannot be implemente in harware, the counter s value is limite by its actual number of igits. In the Reference CAN Moel, the Receive Error Count has a resolution of 8 bits, which is sufficient for all purposes of fault confinement, because once the Receive Error Count has reache its Error Passive level (128), it is irrelevant how much this level is exceee. So the Receive Error Count nees not to be incremente above the Error Passive level. In the Reference CAN Moel, the Receive Error Counter is use to count the 128 sequences neee for the Busoff Recovery Sequence (see Fault Confinement Rule 12). This technique is not intene as an example for harware implementations of CAN protocol controllers, the CAN licensee is free to use other solutions best suite for the iniviual implementation. (5) Synchronization Rule 4 requires the Har Synchronization to be performe at every ege from recessive to ominant uring Bus Ile. Aitionally, chapter 3.2.1 "Data Frame - Start of Frame" requires the Har Synchronization for each receive Start of Frame. A Start of Frame can be receive not only uring Bus Ile, but also uring Suspen Transmission an at the en of Intermission. Therefore, the Reference CAN Moel enables the Har Synchronisation not only for Bus Ile state, but also for Suspen state an for the en of the Intermission State. Any noe isables Har Synchronization when it samples an ege from recessive to ominant or when it

CAN Specification 2.0 Aenum Mar. 1997-3 - starts to sen the ominant Start of Frame bit. Since the synchronization on eges from ominant to recessive has become obsolete with the upgrae from CAN protocol version 1.1 to version 1.2 (see CAN Specification Revision 2.0, Part A, chapter 9.1 section [4]) the Reference CAN Moel oes not support this kin of synchronization.