HEF4027B. 1. General description. 2. Features and benefits. 3. Applications. 4. Ordering information. Dual JK flip-flop

Similar documents
HEF4011B. 1. General description. 2. Features and benefits. 3. Ordering information. 4. Functional diagram. Quad 2-input NAND gate

HEF4021B. 1. General description. 2. Features and benefits. 3. Ordering information. 8-bit static shift register

1-of-4 decoder/demultiplexer

HEF4013B. 1. General description. 2. Features and benefits. 3. Applications. 4. Ordering information. Dual D-type flip-flop

Quad 2-input NAND Schmitt trigger

14-stage ripple-carry binary counter/divider and oscillator

HEF4013B. 1. General description. 2. Features and benefits. 3. Applications. 4. Ordering information. Dual D-type flip-flop

3-to-8 line decoder, demultiplexer with address latches

The 74LVC1G11 provides a single 3-input AND gate.

74HC377; 74HCT General description. 2. Features and benefits. 3. Ordering information

74HC175; 74HCT175. Quad D-type flip-flop with reset; positive-edge trigger

74HC107; 74HCT107. Dual JK flip-flop with reset; negative-edge trigger

Triple single-pole double-throw analog switch

74HC02; 74HCT General description. 2. Features and benefits. Ordering information. Quad 2-input NOR gate

8-channel analog multiplexer/demultiplexer

74HC2G02; 74HCT2G General description. 2. Features and benefits. 3. Ordering information. Dual 2-input NOR gate

Low-power configurable multiple function gate

74HC154; 74HCT to-16 line decoder/demultiplexer

74HC574; 74HCT574. Octal D-type flip-flop; positive edge-trigger; 3-state

74HC238; 74HCT to-8 line decoder/demultiplexer

74HC4040; 74HCT stage binary ripple counter

74HC165; 74HCT bit parallel-in/serial out shift register

74HC74; 74HCT General description. 2. Features and benefits. 3. Ordering information

8-bit binary counter with output register; 3-state

74HC393; 74HCT393. Dual 4-bit binary ripple counter

74HCU General description. 2. Features and benefits. 3. Ordering information. Hex unbuffered inverter

3-input EXCLUSIVE-OR gate. The 74LVC1G386 provides a 3-input EXCLUSIVE-OR function.

NPN wideband transistor in a SOT89 plastic package.

Planar PIN diode in a SOD323 very small plastic SMD package.

Schottky barrier quadruple diode

Hex buffer with open-drain outputs

The 74LVC1G04 provides one inverting buffer.

74HC138; 74HCT to-8 line decoder/demultiplexer; inverting

BAT54 series SOT23 Schottky barrier diodes Rev. 5 5 October 2012 Product data sheet 1. Product profile 1.1 General description

74AUP1G General description. 2. Features and benefits. Low-power D-type flip-flop with set and reset; positive-edge trigger

74HC32; 74HCT General description. 2. Features and benefits. Quad 2-input OR gate

The sensor can be operated at any frequency between DC and 1 MHz.

Low forward voltage High breakdown voltage Guard-ring protected Hermetically sealed glass SMD package

High-speed switching diodes. Type number Package Configuration Package NXP JEITA JEDEC

Passivated, sensitive gate triacs in a SOT54 plastic package. General purpose switching and phase control

8-bit synchronous binary down counter

10 ma LED driver in SOT457

SiGe:C Low Noise High Linearity Amplifier

Low-power D-type flip-flop; positive-edge trigger; 3-state

74HC573; 74HCT General description. 2. Features and benefits. Octal D-type transparent latch; 3-state

74LVC1G General description. 2. Features and benefits. Single D-type flip-flop with set and reset; positive edge trigger

DISCRETE SEMICONDUCTORS DATA SHEET. dbook, halfpage M3D088. BB201 Low-voltage variable capacitance double diode. Product specification 2001 Oct 12

Buffer with open-drain output. The 74LVC1G07 provides the non-inverting buffer.

IP4220CZ6. 1. Product profile. Dual USB 2.0 integrated ESD protection. 1.1 General description. 1.2 Features and benefits. 1.

BAS16 series. 1. Product profile. High-speed switching diodes. 1.1 General description. 1.2 Features and benefits. 1.

DATA SHEET. BF245A; BF245B; BF245C N-channel silicon field-effect transistors DISCRETE SEMICONDUCTORS

74HC595; 74HCT General description. 2. Features and benefits. 3. Applications

74HC595; 74HCT General description. 2. Features and benefits. 3. Applications

74HC123; 74HCT123. Dual retriggerable monostable multivibrator with reset

4-bit binary full adder with fast carry CIN + (A1 + B1) + 2(A2 + B2) + 4(A3 + B3) + 8(A4 + B4) = = S1 + 2S2 + 4S3 + 8S4 + 16COUT

Bus buffer/line driver; 3-state

74HC4067; 74HCT channel analog multiplexer/demultiplexer

45 V, 100 ma NPN general-purpose transistors

DISCRETE SEMICONDUCTORS DATA SHEET. BT151 series C Thyristors

DISCRETE SEMICONDUCTORS DATA SHEET M3D848. CGD MHz, 20 db gain power doubler amplifier. Product specification 2002 Oct 08

74HC4066; 74HCT4066. Quad single-pole single-throw analog switch

Ultrafast, epitaxial rectifier diode in a SOD59 (TO-220AC) plastic package

LIN-bus ESD protection diode

74ALVC bit dual supply translating transceiver; 3-state. This device can be used as two 8-bit transceivers or one 16-bit transceiver.

Femtofarad bidirectional ESD protection diode

40 V, 200 ma NPN switching transistor

INTEGRATED CIRCUITS. 74LVC08A Quad 2-input AND gate. Product specification IC24 Data Handbook Jun 30

MOSFET N-channel enhancement switching transistor IMPORTANT NOTICE. use

CAN bus ESD protection diode

DATA SHEET. MMBT3904 NPN switching transistor DISCRETE SEMICONDUCTORS. Product data sheet Supersedes data of 2002 Oct Feb 03.

General purpose low power phase control General purpose low power switching Solid-state relay. Symbol Parameter Conditions Min Typ Max Unit V DRM

Medium power Schottky barrier single diode

PMEG3005EB; PMEG3005EL

PMEG2020EH; PMEG2020EJ

PMEG3015EH; PMEG3015EJ

IP4294CZ10-TBR. ESD protection for ultra high-speed interfaces

65 V, 100 ma PNP/PNP general-purpose transistor

High-speed USB 2.0 switch with enable

74HC4051; 74HCT channel analog multiplexer/demultiplexer

PESDxU1UT series. 1. Product profile. Ultra low capacitance ESD protection diode in SOT23 package. 1.1 General description. 1.

NPN wideband silicon germanium RF transistor

DISCRETE SEMICONDUCTORS DATA SHEET BC856; BC857; BC858

45 V, 100 ma NPN/PNP general-purpose transistor

INTEGRATED CIRCUITS. 74F74 Dual D-type flip-flop. Product specification Supercedes data of 1990 Oct 23 IC15 Data Handbook.

BLL6G1214L Product profile. LDMOS L-band radar power transistor. 1.1 General description. 1.2 Features and benefits. 1.

INTEGRATED CIRCUITS. 74F153 Dual 4-line to 1-line multiplexer. Product specification 1996 Jan 05 IC15 Data Handbook

DATA SHEET. PMEGXX10BEA; PMEGXX10BEV 1 A very low V F MEGA Schottky barrier rectifier DISCRETE SEMICONDUCTORS

SCR, 12 A, 15mA, 500 V, SOT78. Planar passivated SCR (Silicon Controlled Rectifier) in a SOT78 plastic package.

PMEG1020EA. 1. Product profile. 2 A ultra low V F MEGA Schottky barrier rectifier. 1.1 General description. 1.2 Features. 1.

2PD601ARL; 2PD601ASL

BZT52H series. Single Zener diodes in a SOD123F package

NPN wideband silicon RF transistor

Silicon temperature sensors. Other special selections are available on request.

PUSB3FR4. 1. Product profile. ESD protection for ultra high-speed interfaces. 1.1 General description. 1.2 Features and benefits. 1.

PRTR5V0U2F; PRTR5V0U2K

Description. Table 1. Device summary. Order code Temperature range Package Packaging Marking

DATA SHEET. PBSS5540Z 40 V low V CEsat PNP transistor DISCRETE SEMICONDUCTORS. Product data sheet Supersedes data of 2001 Jan Sep 21.

MC14008B. 4-Bit Full Adder

DISCRETE SEMICONDUCTORS DATA SHEET

BAS70 series; 1PS7xSB70 series

Transcription:

Rev. 9 18 November 2011 Product data sheet 1. General description 2. Features and benefits 3. Applications The is a edge-triggered dual JK flip-flop which features independent set-direct (SD), clear-direct (D), clock (P) inputs and outputs (Q, Q). Data is accepted when P is LOW, and transferred to the output on the positive-going edge of the clock. The active HIGH asynchronous clear-direct (D) and set-direct (SD) inputs are independent and override the J, K, and P inputs. The outputs are buffered for best system performance. Schmitt trigger action makes the clock input highly tolerant of slower rise and fall times. It operates over a recommended V DD power supply range of 3 V to 15 V referenced to V SS (usually ground). Unused inputs must be connected to V DD, V SS, or another input. Fully static operation 5 V, 10 V, and 15 V parametric ratings Standardized symmetrical output characteristics Specified from 40 to +85 omplies with JEDE standard JESD 13-B Registers ounters ontrol circuits 4. Ordering information Table 1. Ordering information T amb from 40 to +85. Type number Package Name Description Version P DIP16 plastic dual in-line package; 16 leads (300 mil) SOT38-4 T SO16 plastic small outline package; 16 leads; body width 3.9 mm SOT109-1

5. Functional diagram 9 10 13 11 12 7 6 3 5 4 FF 1 1SD 1J 1Q 1P 1Q 1K 1D FF 2 2SD 2J 2Q 2P 2Q 2K 2D 15 14 1 2 001aae593 Fig 1. Functional diagram P Q J Q K D SD 001aae595 Fig 2. Logic diagram of one flip-flop All information provided in this document is subject to legal disclaimers. NXP B.V. 2011. All rights reserved. Product data sheet Rev. 9 18 November 2011 2 of 14

6. Pinning information 6.1 Pinning 2Q 1 16 V DD 2Q 2 15 1Q 2P 3 14 1Q 2D 4 13 1P 2K 5 12 1D 2J 6 11 1K 2SD 7 10 1J V SS 8 9 1SD 001aae594 Fig 3. Pin configuration 6.2 Pin description Table 2. Pin description Symbol Pin Description V SS 8 ground supply voltage 1SD, 2SD 9, 7 asynchronous set-direct input (active HIGH) 1J, 2J 10, 6 synchronous input 1K, 2K 11, 5 synchronous input 1D, 2D 12, 4 asynchronous clear-direct input (active HIGH) 1P, 2P 13, 3 clock input (LOW-to-HIGH edge-triggered) 1Q, 2Q 14, 2 complement output 1Q, 2Q 15, 1 true output V DD 16 supply voltage 7. Functional description Table 3. Function table [1] Inputs Outputs nsd nd np nj nk nq nq H L X X X H L L H X X X L H H H X X X H H All information provided in this document is subject to legal disclaimers. NXP B.V. 2011. All rights reserved. Product data sheet Rev. 9 18 November 2011 3 of 14

Table 3. Function table [1] continued Inputs Outputs nsd nd np nj nk nq nq L L L L no change no change L L H L H L L L L H L H L L H H nq nq [1] H = HIGH voltage level; L = LOW voltage level; X = don t care.; = positive-going transition. 8. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IE 60134). Symbol Parameter onditions Min Max Unit V DD supply voltage 0.5 +18 V I IK input clamping current V I < 0.5 V or V I >V DD + 0.5 V - 10 ma V I input voltage 0.5 V DD + 0.5 V I OK output clamping current V O < 0.5 V or V O >V DD + 0.5 V - 10 ma I I/O input/output current - 10 ma I DD supply current - 50 ma T stg storage temperature 65 +150 T amb ambient temperature in free air 40 +85 P tot total power dissipation T amb 40 to +85 DIP16 package [1] - 750 mw SO16 package [2] - 500 mw P power dissipation per output - 100 mw [1] For DIP16 package: P tot derates linearly with 12 mw/k above 70. [2] For SO16 package: P tot derates linearly with 8 mw/k above 70. 9. Recommended operating conditions Table 5. Recommended operating conditions Symbol Parameter onditions Min Max Unit V DD supply voltage 3 15 V V I input voltage 0 V DD V T amb ambient temperature in free air 40 +85 t/ V input transition rise and fall rate V DD = 5 V - 3.75 s/v V DD = 10 V - 0.5 s/v V DD = 15 V - 0.08 s/v All information provided in this document is subject to legal disclaimers. NXP B.V. 2011. All rights reserved. Product data sheet Rev. 9 18 November 2011 4 of 14

10. Static characteristics Table 6. Static characteristics V SS = 0 V; V I = V SS or V DD ; unless otherwise specified. Symbol Parameter onditions V DD T amb = 40 T amb = 25 T amb = 85 Unit Min Max Min Max Min Max V IH HIGH-level input voltage I O < 1 A 5 V 3.5-3.5-3.5 - V 10 V 7.0-7.0-7.0 - V 15 V 11.0-11.0-11.0 - V V IL LOW-level input voltage I O < 1 A 5 V - 1.5-1.5-1.5 V 10 V - 3.0-3.0-3.0 V 15 V - 4.0-4.0-4.0 V V OH HIGH-level output voltage I O < 1 A 5 V 4.95-4.95-4.95 - V 10 V 9.95-9.95-9.95 - V 15 V 14.95-14.95-14.95 - V V OL LOW-level output voltage I O < 1 A 5 V - 0.05-0.05-0.05 V 10 V - 0.05-0.05-0.05 V 15 V - 0.05-0.05-0.05 V I OH HIGH-level output current V O = 2.5 V 5 V - 1.7-1.4-1.1 ma V O = 4.6 V 5 V - 0.52-0.44-0.36 ma V O = 9.5 V 10 V - 1.3-1.1-0.9 ma V O = 13.5 V 15 V - 3.6-3.0-2.4 ma I OL LOW-level output current V O = 0.4 V 5 V 0.52-0.44-0.36 - ma V O = 0.5 V 10 V 1.3-1.1-0.9 - ma V O = 1.5 V 15 V 3.6-3.0-2.4 - ma I I input leakage current 15 V - 0.3-0.3-1.0 A I DD supply current I O = 0 A 5 V - 4.0-4.0-30 A 10 V - 8.0-8.0-60 A 15 V - 16.0-16.0-120 A I input capacitance - - - - 7.5 - - pf All information provided in this document is subject to legal disclaimers. NXP B.V. 2011. All rights reserved. Product data sheet Rev. 9 18 November 2011 5 of 14

11. Dynamic characteristics Table 7. Dynamic characteristics V SS = 0 V; T amb = 25 ; for test circuit see Figure 7; unless otherwise specified. Symbol Parameter onditions V DD Extrapolation formula [1] Min Typ Max Unit t PHL HIGH to LOW P Q, Q; 5 V 78 ns + (0.55 ns/pf) L - 105 210 ns propagation delay see Figure 4 10 V 29 ns + (0.23 ns/pf) L - 40 80 ns 15 V 22 ns + (0.16 ns/pf) L - 30 60 ns D Q; 5 V 93 ns + (0.55 ns/pf) L - 120 240 ns see Figure 4 10 V 33 ns + (0.23 ns/pf) L - 45 90 ns 15 V 27 ns + (0.16 ns/pf) L - 35 70 ns SD Q; 5 V 113 ns + (0.55 ns/pf) L - 140 280 ns see Figure 4 10 V 44 ns + (0.23 ns/pf) L - 55 110 ns 15 V 32 ns + (0.16 ns/pf) L - 40 80 ns t PLH LOW to HIGH P Q, Q; 5 V 58 ns + (0.55 ns/pf) L - 85 170 ns propagation delay see Figure 4 10 V 27 ns + (0.23 ns/pf) L - 35 70 ns 15 V 22 ns + (0.16 ns/pf) L - 30 60 ns D Q; 5 V 48 ns + (0.55 ns/pf) L - 75 150 ns see Figure 4 10 V 24 ns + (0.23 ns/pf) L - 35 70 ns 15 V 17 ns + (0.16 ns/pf) L - 25 50 ns SD Q; 5 V 43 ns + (0.55 ns/pf) L - 70 140 ns see Figure 4 10 V 19 ns + (0.23 ns/pf) L - 30 60 ns 15 V 17 ns + (0.16 ns/pf) L - 25 50 ns t t transition time see Figure 4 5 V [2] 10 ns + (1.00 ns/pf) L - 60 120 ns 10 V 9 ns + (0.42 ns/pf) L - 30 60 ns 15 V 6 ns + (0.28 ns/pf) L - 20 40 ns t su set-up time J, K P; 5 V 50 25 - ns see Figure 5 10 V 30 10 - ns 15 V 20 5 - ns t h hold time J, K P; 5 V 25 0 - ns see Figure 5 10 V 20 0 - ns 15 V 15 5 - ns t W pulse width P LOW; 5 V 80 40 - ns minimum width 10 V 30 15 - ns see Figure 5 15 V 24 12 - ns SD, D HIGH; 5 V 90 45 - ns minimum width 10 V 40 20 - ns see Figure 6 15 V 30 15 - ns t rec recovery time SD, D inputs; 5 V +20 15 - ns see Figure 6 10 V +15 10 - ns 15 V +10 5 - ns All information provided in this document is subject to legal disclaimers. NXP B.V. 2011. All rights reserved. Product data sheet Rev. 9 18 November 2011 6 of 14

Table 7. Dynamic characteristics continued V SS = 0 V; T amb = 25 ; for test circuit see Figure 7; unless otherwise specified. Symbol Parameter onditions V DD Extrapolation formula [1] Min Typ Max Unit f max maximum P input; 5 V 4 8 - MHz frequency J = K = HIGH; 10 V 12 25 - MHz see Figure 5 15 V 15 30 - MHz [1] The typical values of the propagation delay and transition times are calculated from the extrapolation formulas shown ( L in pf). [2] t t is the same as t TLH and t THL. Table 8. Dynamic power dissipation P D P D can be calculated from the formulas shown. V SS = 0 V; t r = t f 20 ns; T amb = 25. Symbol Parameter V DD Typical formula for P D ( W) Where: P D dynamic power 5 V P D = 900 f i + (f o L ) V 2 DD f i = input frequency in MHz; dissipation 10 V P D = 4500 f i + (f o L ) V 2 DD f o = output frequency in MHz; 15 V P D = 13200 f i + (f o L ) V 2 DD L = output load capacitance in pf; V DD = supply voltage in V; (f o L ) = sum of the outputs. 12. Waveforms V I SD, D or P INPUT 0 V 10 % t r 90 % V M t PLH t f t PHL V OH Q or Q OUTPUT V OL V M 10 % 90 % t TLH t THL 001aah863 Fig 4. V OH and V OL are typical output voltages levels that occur with the output load. Measurement points are given in Table 9. Waveforms showing rise, fall and transition times and propagation delays 1/f max t W P INPUT V M t h J,K INPUT V M t su 001aae596 Fig 5. Measurement points are given in Table 9. Waveforms showing set-up and hold times and minimum clock pulse width All information provided in this document is subject to legal disclaimers. NXP B.V. 2011. All rights reserved. Product data sheet Rev. 9 18 November 2011 7 of 14

V I SD INPUT 0 V V M t W V I D INPUT V M 0 V t rec t W t rec V I P INPUT 0 V V M V OH Q OUTPUT V OL 001aae597 Fig 6. V OH and V OL are typical output voltages levels that occur with the output load. Measurement points are given in Table 9. Waveforms showing pulse widths and recovery times Table 9. Measurement points Supply voltage Input Output V DD V M V M 5 V to 15 V 0.5V DD 0.5V DD V DD G V I DUT V O RT L 001aag182 Fig 7. Test data is given in Table 10. Definitions for test circuit: DUT = Device Under Test. L = load capacitance including jig and probe capacitance. R T = termination resistance should be equal to the output impedance Z o of the pulse generator. Test circuit Table 10. Test data Supply voltage Input Load V DD V I t r, t f L 5 V to 15 V V SS or V DD 20 ns 50 pf All information provided in this document is subject to legal disclaimers. NXP B.V. 2011. All rights reserved. Product data sheet Rev. 9 18 November 2011 8 of 14

13. Package outline DIP16: plastic dual in-line package; 16 leads (300 mil) SOT38-4 D M E seating plane A 2 A L A 1 Z 16 e b b 1 9 b 2 w M c (e ) 1 M H pin 1 index E 1 8 0 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) A A UNIT 1 A 2 (1) (1) (1) max. b 1 b 2 c D E e L M Z min. max. b e 1 M E H w max. mm inches 4.2 0.51 3.2 0.17 0.02 0.13 1.73 1.30 0.068 0.051 0.53 0.38 0.021 0.015 1.25 0.85 0.049 0.033 0.36 0.23 0.014 0.009 19.50 18.55 0.77 0.73 6.48 6.20 0.26 0.24 Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. 2.54 7.62 0.1 0.3 3.60 3.05 0.14 0.12 8.25 7.80 0.32 0.31 10.0 8.3 0.39 0.33 0.254 0.01 0.76 0.03 OUTLINE VERSION REFERENES IE JEDE JEITA EUROPEAN PROJETION ISSUE DATE SOT38-4 95-01-14 03-02-13 Fig 8. Package outline SOT38-4 (DIP16) All information provided in this document is subject to legal disclaimers. NXP B.V. 2011. All rights reserved. Product data sheet Rev. 9 18 November 2011 9 of 14

SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 D E A X c y H E v M A Z 16 9 Q A 2 A 1 (A ) 3 A pin 1 index θ L p 1 8 L e b p w M detail X 0 2.5 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 0.25 1.75 0.10 0.069 0.010 0.004 A 1 A 2 A 3 b p c D (1) E (1) e H (1) E L L p Q v w y Z 1.45 1.25 0.057 0.049 0.25 0.01 0.49 0.36 0.019 0.014 0.25 0.19 0.0100 0.0075 10.0 9.8 0.39 0.38 4.0 3.8 0.16 0.15 1.27 6.2 5.8 0.244 0.228 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. 0.05 1.05 0.041 1.0 0.4 0.039 0.016 0.7 0.6 0.028 0.020 0.25 0.25 0.1 0.01 0.01 0.004 θ 0.7 0.3 o 8 o 0.028 0 0.012 OUTLINE VERSION REFERENES IE JEDE JEITA EUROPEAN PROJETION ISSUE DATE SOT109-1 076E07 MS-012 99-12-27 03-02-19 Fig 9. Package outline SOT109-1 (SO16) All information provided in this document is subject to legal disclaimers. NXP B.V. 2011. All rights reserved. Product data sheet Rev. 9 18 November 2011 10 of 14

14. Revision history Table 11. Revision history Document ID Release date Data sheet status hange notice Supersedes v.9 20111118 Product data sheet - v.8 Modifications: Legal pages updated. hanges in General description and Features and benefits. v.8 20111010 Product data sheet - v.7 v.7 20091125 Product data sheet - v.6 v.6 20090624 Product data sheet - v.5 v.5 20081110 Product data sheet - v.4 v.4 20080703 Product specification - _NV v.3 _NV v.3 19950101 Product specification - _NV v.2 _NV v.2 19950101 Product specification - - All information provided in this document is subject to legal disclaimers. NXP B.V. 2011. All rights reserved. Product data sheet Rev. 9 18 November 2011 11 of 14

15. Legal information 15.1 Data sheet status Document status [1][2] Product status [3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term short data sheet is explained in section Definitions. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 15.2 Definitions Draft The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. 15.3 Disclaimers Limited warranty and liability Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer s own risk. Applications Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. ustomers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer s applications and products planned, as well as for the planned application and use of customer s third party customer(s). ustomers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer s applications or products, or the application or use by customer s third party customer(s). ustomer is responsible for doing all necessary testing for the customer s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer s third party customer(s). NXP does not accept any liability in this respect. Limiting values Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IE 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the haracteristics sections of this document is not warranted. onstant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. All information provided in this document is subject to legal disclaimers. NXP B.V. 2011. All rights reserved. Product data sheet Rev. 9 18 November 2011 12 of 14

Non-automotive qualified products Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors specifications such use shall be solely at customer s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors standard warranty and NXP Semiconductors product specifications. 15.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 16. ontact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com All information provided in this document is subject to legal disclaimers. NXP B.V. 2011. All rights reserved. Product data sheet Rev. 9 18 November 2011 13 of 14

17. ontents 1 General description...................... 1 2 Features and benefits.................... 1 3 Applications............................ 1 4 Ordering information..................... 1 5 Functional diagram...................... 2 6 Pinning information...................... 3 6.1 Pinning............................... 3 6.2 Pin description......................... 3 7 Functional description................... 3 8 Limiting values.......................... 4 9 Recommended operating conditions........ 4 10 Static characteristics..................... 5 11 Dynamic characteristics.................. 6 12 Waveforms............................. 7 13 Package outline......................... 9 14 Revision history........................ 11 15 Legal information....................... 12 15.1 Data sheet status...................... 12 15.2 Definitions............................ 12 15.3 Disclaimers........................... 12 15.4 Trademarks........................... 13 16 ontact information..................... 13 17 ontents.............................. 14 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section Legal information. NXP B.V. 2011. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 18 November 2011 Document identifier: