Islamic University of Gaza Faculty of Engineering Electrical Department Experiment # (10) PSK Demodulator Digital Communications Lab. Prepared by: Eng. Mohammed K. Abu Foul Experiment Objectives: 1. To understand the operation theory of PSK demodulation. 2. To design the PSK demodulator by using MC1496 3. To understand the methods of measuring and adjusting the PSK demodulation circuit. Experiment theory: In experiment 9, we have discussed the operation theory of PSK modulator. In this experiment, we will discuss how to design a PSK demodulator. Figure 10.1 shows the operation theory diagram of the PSK demodulation. Figure 10.1 Signal waveforms of demodulated PSK signal. Figure 10.2 Basic circuit of PSK demodulator. 1
Figure 10.2 is the basic diagram of PSK demodulator. This circuit is similar to the PSK modulator. The only difference is there is a low-pass filter at the output port. The objective is to remove the unwanted signals. Assume that the phase and magnitude of ω c and PSK signals are similar to each other, then the output is 5 V. If the phase and magnitude of ω c and PSK signals are opposite to each other, then all the diodes will be OFF and there is no current pass through the low-pass filter. Therefore, the output of the low-pas filter is 0 V. In this section, we utilize the theory os mathematic to solve the FSK modulation as shown in equation (10.1). Assume that x PSK (t) be the modulated PSK signal, then the expression is shown as follow: Where: m: index of the symbol. M = 2 n where n is the number of bits during transmission A: amplitude = ± 1 Carrier angular velocity (ω c ) is constant. When we input this signal to signal squarer of balanced modulator then the output signal of the balanced modulator can be expressed as: If the PSK signal is 1-bit, i.e. M=2, then equation (1.2) can be simplified as follow: Where k is the gain of the balanced modulator. The first term is the DC signal. Second term is the 2 nd harmonic output (2ω c ) of the carrier signal. The output signal of the balanced modulator will pass through a filter to block the DC signal. Then by using PLL, the doublefrequency signal is converted to square wave. After that the frequency divider will reduce the frequency of this square wave, which is similar to the frequency of the carrier signal (ω c ). then this square wave will be sent to the phase shifter to adjust the phase in order to control the analog switch. Finally, the output signal from the analog switch will be sent to the rectifier and the comparator for data signal recovery. In this experiment, we utilize the squaring loop detector to implement the PSK demodulator. Figure 10.3 is the block diagram of squaring loop detector of PSK demodulator. In this structure, the signal squarer can be designed and implemented by the balanced 2
modulator of MC1496. Figure 10.4 is the internal circuit diagram of the balanced modulator of MC1496 (you may refer to experiment 5 for the circuit explanation) Figure 10.3 Block diagram of PSK demodulator Figure 10.4 Internal structure diagram of MC1496 balanced modulator. Figure 10.5 is the circuit diagram of PSK detector. VR 1 is used to control the input magnitude of PSK signal. The output signal at pin 12 if MC1496 is expressed by the equation (10.3). µa741, C 8, R 22, R 25 and R 27 to comprise a filter, which is used to remove the first term of equation (10.3), i.e. the DC signal of the PSK signal. The 2 nd harmonic of the carrier signal can be converted to the square wave output by the PLL circuit, which is comprised by 74HC4046, R 2, R 3, R 5, C 1, C 2 and VR 2. The frequency of this signal will be divided by 2 by the frequency divider (74HC393). The 74HC6538, R 12, R 18, C 5, C 7 and VR 3 comprise a phase shifter to adjust the phase of the square wave and then control the analog switch (4053). Finally the signal will pass through the rectifier (D 1, R 26 and C 10 ) and the comparator (µa741, R 28 and R 29 ) to recover the original data signal. 3
Figure 10.5 Circuit diagram of PSK detector 4
Experiment items: Experiment 1: PSK demodulator 1. Refer to the circuit diagram in figure 9.6 or refer to figure DCS15.1 on ETEK DCS- 6000-08 module to produce the modulated PSK signal as the signal source of this experiment. 2. At the input terminal of modulation signal (Data I/P), input 5 V amplitude and 100 Hz TTL signal with 50 % duty cycle, i.e. data signal streams with "10". At the input terminal of carrier signal (carrier I/P), input 600 mv amplitude and 20 khz sine wave frequency. 3. By using oscilloscope, observe on the output signal waveforms of the modulated PSK signal (PSK O/P). adjust VR 1 of PSK modulator so that the waveform does not occure distortion. Slightly adjust the VR 2 to avoid the asymmetry of the waveform. So that we can obtain the optimum output waveform modulated PSK signal. 4. Adjust VR 1 of PSK modulator of figure 10.5 or figure DCS16.1 on ETEK DCS-6000-08 module, so that the output terminal of PLL (TP6) outputs a 40 khz free-running frequency (f o ). 5. Connect the modulated PSK signal (PSK O/P) of figure DCS15.1 to the input terminal (PSK I/P) of figure DCS16.1. Adjust VR 2 so that the output signal of signal squarer (TP4) is the double of the carrier frequency, which is 40 khz. 6. By using oscilloscope, observe on the output signal waveforms of digital signal input terminal (Data I/P). Slightly adjust VR 3 to obtain the exact demodulated PSK signal. Then observe on the PSK input signal, the output signals of the buffer (TP1), signal squarer (TP2), amplifier (TP3), PLL input port (TP4), the charge and discharge test point (TP5), PLL output port (TP6), frequency divider (TP7), phase shifter (TP8), analog switch (TP9) and the data signal output port (DATA). Finally, record the measured results in table 10.1. 5
Measured results: Table 10-1 Observe on the output signal of PSK demodulator when data signal frequency = 100 Hz (V c = 600 mv, f c = 20 khz) Data signal frequencies Output signal waveforms 100 Hz PSK I/P TP1 TP2 TP3 TP4 TP5 TP6 TP7 TP8 TP9 Data O/P 6