DESCRIPTION is an LED Conroller driven on a 1/7o 1/8 duy facor. Eleven segmen oupu lines, six grid oupu lines, 1 segmen/grid oupu lines, one display memory, conrol circui, key scan circui are all incorporaed ino a single chip o build a highly reliable peripheral device for a single chip microcompuer. Serial daa is fed o via a four-line serial inerface. Housed in a 24-pin SO Package, pin assignmens and applicaion circui are opimized for easy PCB Layou and cos saving advanages. FEATURES CMOS Technology Low Power Consumpion Muliple Display Modes Key Scanning 8-Sep Dimming Circuiry Serial Inerface for Clock, Daa Inpu, Daa Oupu, Srobe Pins Available in 24-Pin, SOP Package APPLICATION Micro-compuer Peripheral Device VCR se Combi se BLOCK DIAGRAM DI/O Serial Daa Inerface OSC Conrol Dispaly Memory Timing Generaor Key Marix Memory SEGMENT DRIVER/ KEY SCAN OUTPUT/ GRID DRIVER SG1/KS1 SG2/KS2 SG3/KS3 SG4/KS4 SG5/KS5 SG6/KS6 SG7/KS7 SG8/KS8 SG9/KS9 SG10/KS10 SG12/GR7 SG13/GR6 SG14/GR5 GR4 GR3 GR2 GR1 Dimming Circui K1 K2 VDD GND 1
INPUT/OUTPUT CONFIGURATIONS The schemaic diagrams of he inpu and oupu circuis of he logic secion are shown below. Inpu Pins:, & DIN VDD GND Inpu Pins: K1 o K2 VDD GND Oupu Pins: DOUT, GR1 o GR4 VDD GND Oupu Pins: SG1 o SG10 VDD Oupu Pins: GR5, GR6 and SG12/GR7 GND VDD GND 2
PIN CONFIGURATION 1 2 3 4 5 6 7 8 9 10 11 12 DIO K1 K2 VDD SEG1/KS1 SEG2/KS2 SEG3/KS3 SEG4/KS4 SEG5/KS5 SEG6/KS6 GRID1 GRID2 GND GRID3 GRID4 GRID5 GRID6 GRID7 SEG10/KS10 SEG9/KS9 SEG8/KS8 SEG7/KS7 24 23 22 21 20 19 18 17 16 15 14 13 PIN DESCRIPTION Pin Name I/O Descripion DI/O I/O Daa Oupu Pin ( N-Channel, Open-Drain ) or Daa Inpu pin This pin Oupus/Inpu serial daa a he falling(rising) edge of he shif clock. K1 o K2 I I I GND - SG1/KS1 o SG10/KS10 SG12/GR7 osg14/gr5 O O VDD - Clock Inpu Pin This pin reads serial daa a he rising edge and oupus daa a he falling edge. Serial Inerface Srobe Pin The daa inpu afer he has fallen is processed as a command When his pin is HIGH, is ignored. Key Daa Inpu Pins. The daa sen o hese pins are lached a he end of he display cycle. ( Inernal Pull-Low Resisor) GroundPin Segmen Oupu Pins ( p-channel, open drain ) Also acs as he Key Source Segmen/Grid Oupu Pins Power Supply GR4 o GR1 O Grid Oupu Pins FUNCTIONAL DESCRIPTION COMMANDS A command is he firs bye ( b0 o b7 ) inpued o via he DIN Pin afer pin has changed from HIGH o LOW Sage. If for some reason he Pin is se o HIGH while daa or commands are being ransmied, he serial communicaions is iniialized, and he daa/commands being ransmied are considered invalid. 3
Command 1: Display Mode Seing Commands provides 2 display mode seings as shown in he diagram below: As saed earlier a command is he firs one bye ( b0 o b7 ) ransmied o via he DIN Pin when is LOW. However, for hese commands, he bi 3 o bi 6 (b2 o b5) are ignored, bi 7 & bi 8 (b6 o b7) are given value of 0. The Display Mode Seing Commands deermine he number of segmens and grids o be used (12 o 11 segmens, 6 o 7 grids). A display command ON mus be execued in order o resume display. If he same mode seing is seleced, no command execuion is ake place, herefore, nohing happens. When Power is urned ON, he 7-grid, 11-segmen modes is seleced. Command 2: Daa Seing Commands The Daa Seing Commands execues he Daa Wrie or Daa Read Modes for. The daa Seing Command, he bis 5 and 6 (b4,b5) are ignored, bi 7 (b6) is given he value of 1 while bi 8 (b7) is given he value of 0. Please refer o he diagram below. When power is urned ON, bi 4 o bi 1 (b3 o b0) are given he value of 0. KEYMATRIX & KEYINPUT DATA STORAGE RAM Key Marix consiss of 10 x 2 array as shown below: K1 K2 SG1/ SG2/ SG3/ SG4/ SG5/ SG6/ SG7/ SG8/ SG9/ SG10/ KS1 KS2 KS3 KS4 KS5 KS6 KS7 KS8 KS9 KS10 4
Each daa enered by each key is sored as follows and read by a READ Command, saring from he las significan bi. When he mos significan bi of he daa (b0) has been read, he leas significan bi of he nex daa (b7) is read. Command 3: Address Seing Commands Address Seing Commands are used o se he address of he display memory. The address is considered valid if i has a value of 00H o 0DH. If he address is se o 0EH or higher, he daa is ignored unil a valid address is se. When power is urned ON, he address is se a a 00H. Please refer o he diagram below. DISPALYMODE AND RAMADDRESS Daa ransmied from an exernal device o via he serial inerface are sored in he Display RAM and are assigned addresses. The RAM addresses of are given below in 8 bis uni. 5
Command 4: Display Conrol Commands The Display Conrol Commands are used o urn ON or OFF a display. I also used o se he pulse widh. Please refer o he diagram below. When he power is urned ON, a 1/16 Pulse widh is seleced and he displayed is urned OFF (he key scanning is sared). SCANNING AND DISPLAY TIMING The key Scanning and Display Timing diagram is given below. One cycle of key scanning consiss of 2 frames. The daa of he are 10 x 3 marix is sored in he RAM. Tdisplay-500us Key Scan Daa SG Oupu DIG1 DIG2 DIG3 DIGn DIG1 G1 G2 G3 Gn 1 Frame=Tdispaly Ö (n+1) SERIAL COMMUNICATION FROMAT The following diagram shows he serial communicaion forma. The DOUT Pin is an N-channel, opendrain oupu 6
pin, herefore, i is highly recommended ha an exernal pull-up resisor (1 KOhms o 10 KOhms) mus be conneced o DOUT. RECEPTION (Daa/Command Wrie) If daa coninues DIN b0 b1 b2 b6 b7 1 2 3 7 8 TRANSMISSION (Daa Read) DIN DOUT b0 b1 b2 b3 b4 b5 b6 b7 1 2 3 4 5 6 7 8 wai 1 2 3 4 5 6 b0 b1 b2 b3 b4 b5 Daa Read Command is se Daa Reading Sars where: wai (waiing ime) 1μs I mus be noed ha when he daa is read, he waiing ime ( wai ) beween he rising of he eighh clock ha has se he command and he falling of he firs clock ha has read he daa is greaer or equal o 1μs. SWITCHING CHARACTERISTIC WAVEFORM Swiching Characerisics Waveform is given below. fosc OSC 50% PW PW PW - seup hold DIN PZL PLZ DOUT Gn 90% TZL TLZ 10% Sn 10% TZH 90% THZ 7
where: PW (Clock Pulse Widh) 400nS PW (Srobe Pulse Widh) 1μs seup (Daa Seup Time) 100nS hold (Daa Hold Time) 100nS - (Clock-Srobe Time) 1μs THZ (Fall Time) 10μs TZH (Rise Time) 1μs PZL (Propagaion Delay Time) 100nS f osc =Oscillaion Frequency PLZ (Propagaion Delay Time) 300uS TZL < 1μs TLZ <10μs Noe: Tes condiion under THZ ( Pull low risisor=100k ohms, Loading capacior =300pf) TLZ (Pull high risisor =100k ohms, Loading capacior=300pf ) APPLICATIONS Display memory is updaed by incremening addresses. Please refer o he following diagram. DIN Command2 Command3 Daa1 Daa n Command1 Command4 where: Command 1: Display Mode Seing Command Command 2: Daa Seing Command Command 3: Address Seing Command Daa 1 o n : Transfer Display Daa (14 Byes max.) Command 4: Display Conrol Command The following diagram shows he waveforms when updaing specific addresses. DIN Command2 Command3 Daa Command 3 Daa where: Command 2 Daa Seing Command Command 3 Address Seing Command Daa Display Daa 8
RECOMMENDED SOFTWARE PROGRAMMING FLOWCHART Noe: 1. Command 1: Display Mode Commands 2. Command 2: Daa Seing Commands 3. Command 3: Address Seing Commands 4. Command 4: Display Conrol Commands 5. When IC power is applied for he firs ime, he conens of he Display RAM is no defined; hus, i is srongly suggesed ha he conens of he Display RAM mus be cleared during he iniial seing. 9
ABSOLUTE MAXIMUM RATINGS (Unless oherwise saed, Ta=25, GND=0V) Parameer Symbol Raings Uni Supply Volage V DD -0.5 o +7 Vols Logic Inpu Volage V I -0.5 o V DD +0.5 Vols Driver Oupu Curren I OLGR +250 ma I OHSG -50 ma Maximum Driver Oupu Curren/Toal I TOTAL 400 ma RECOMMENDED OPERATING RANGE (Unless oherwise saed, Ta=-20 o +70, GND=0V) Parameer Symbol Min. Typ. Max. Uni Logic Supply Volage V DD 4.5 5 5.5 V Dynamic Curren (see Noe) I DDdyn - - 10 ma High-Level Inpu Volage V IH 0.8V DD - V DD V Low-Level Inpu Volage V IL 0-0.3V DD V Noe: Tes Condiion: Se Display Conrol Commands = 80H (Display Turn OFF Sae & under no load) ELECTRICAL CHARACTERISTICS (Unless oherwise saed, V DD =5V, GND=0V, Ta=25 ) Parameer Symbol Tes Condiion Min. Typ. Max. Uni High-Level Oupu Curren IOHSG1 Vo=VDD-2V SG1 o SG10, SG12/GR7-20 -25-40 ma IOHSG2 Vo=VDD-3V SG1 o SG12, SG12/GR7-25 -30-50 ma Low-Level Oupu Curren IOLGR Vo=0.3V GR1 o GR6, SG12/GR7 100 140 - ma Low-Level Oupu Curren IOLDOUT Vo=0.4V 4 - - ma Segmen High-Level Vo=VDD-3V ITOLSG Oupu Curren Tolerance SG1 o SG10, SG12/GR7 - - ±5 ma High-Level Inpu Volage VIH - 0.8 V DD - 5 V Low-Level Inpu Volage VIL - 0-0.3V DD V Oscillaion Frequency fosc 350 500 650 KHz K1 o K2 Pull Down Resisor RKN K1 o K2 VDD=5V 40-100 KOhms 10
APPLICATION CIRCUIT 11
COMMON CATHODE TYPE LED PANEL: SEG1 a COM/DIGITAL (GRID) SEG2 SEG3 b c a SEG4 SEG5 d e f g b SEG6 f e c SEG7 SEG8 g h d h Noe: 1 The capacior (0.1uF) conneced beween he GND and he VDD pins mus be locaed as close as possible o he chip. 2 The power supply is separae from he applicaion sysem power supply. 12