Improving productivity Using Fast Monte Carlo. Yun Lan Huawei Technologies CO., LTD.

Improving productivity Using Fast Monte Carlo Yun Lan Huawei Technologies CO., LTD.

Improving productivity Using Fast Monte Carlo VAD Flow Introduction Running Monte Carlo Simulation Post-Processing & Statistical Corners Monte Carlo Mismatch Contribution Optimization and Final Verification 2 2014 Cadence Design Systems, Inc. All rights reserved.

Fast Monte Carlo Analysis Topics VAD Flow Introduction Running Monte Carlo Simulation Post-Processing & Statistical Corners Monte Carlo Mismatch Contribution Optimization and Final Verification 6 2014 Cadence Design Systems, Inc. All rights reserved.

Creating Worst Case Corner To cover process/power supply/temperature effect, we first create worst case corner for PVT combinations for each specification. Based on this corner, we then run MC simulation to take local mismatch into accounts. 7 2014 Cadence Design Systems, Inc. All rights reserved.

Monte Carlo Sampling Algorithms Random sampling Spectre supports different methods of sampling for Monte Carlo analysis: Random Random sampling algorithm allows all samples to have an equal chance of being selected from the population Can work with Monte Carlo auto-stop LDS sampling Low-discrepancy sequence sampling (LDS) Comparable or better accuracy than LHS Faster convergence, better coverage in statistical space Can work with Monte Carlo auto-stop Latin-Hypercube algorithm (LHS) Latin-Hypercube is a quasi-random sampling algorithm with sample selection and rejection Requires fewer samples to get accurate results Recommended when users know how many simulation points they need run. LHS sampling 9 2014 Cadence Design Systems, Inc. All rights reserved.

Post-Processing Fast K-sigma Corners Using standard methods, finding Monte Carlo samples representing 3s yield would require several thousand simulations Meeting design specs at 3s corners helps ensure higher circuit yield Advanced methods can be used to create these conditions from a much smaller sample size (typically ~100 samples) If there are not enough points availble in the simulation data, the tool will run more points to create corner. 14 2014 Cadence Design Systems, Inc. All rights reserved.

Running single run simulation on created corner Run single run simulation on created corner to verify that PSRR can not pass spec. Next step is to optimize the design to improve PSRR for this corner. 15 2014 Cadence Design Systems, Inc. All rights reserved.

Mismatch Contribution Overview Mismatch Contribution Identifies important contributors to variance of circuit specifications due to device mismatch Variance decomposition-based analysis Advanced methods are used to allow contributions to be reported even if the number of samples are less than the number of statistical mismatch parameters Analysis is a post processing of Monte Carlo mismatch analysis Invoke using icon on Results pane or RMB->Mismatch Contribution on History item Note: You must have opted to Save Mismatch Data in the Monte Carlo simulation options form Save Mismatch Data 17 2014 Cadence Design Systems, Inc. All rights reserved.

Mismatch Contribution Results Display Reports mismatch contribution on instance basis Allocates variance to device mismatch parameters using RSM model Model goodness of fit is represented by R^2 Displayed in column headers for each spec Contributions are normalized to sum to 100% Flat Views show individual devices or mismatch parameters Identify the most important instances by clicking on column header to sort Hierarchical and flat views Double-click in a cell to descend (or use down arrow) and view the contributions at each level of hierarchy Double-click or use arrows to navigate hierarchy 18 2014 Cadence Design Systems, Inc. All rights reserved.

Circuit Optimization Optimization target: mean value Std dev For complicated design, Virtuoso Optimization tool can be used to fine tune the design 21 2014 Cadence Design Systems, Inc. All rights reserved.

Running single run simulation on optimized design Run single run simulation on the same corner to verify that PSRR now meet spec after optimization. 22 2014 Cadence Design Systems, Inc. All rights reserved.

Running Fast MC with Auto Stop Instead of running regular MC, fast MC with auto stop can be used to verify the final yield with much less sampling points. 24 2014 Cadence Design Systems, Inc. All rights reserved.

Summary Virtuoso Variation Aware Design flow help improve productivity. In this case, yield of this design is improved from 94.5% to over 96%. Without the flow, this can be done in two days, and with this flow, we can finish it in half day. Creating statistical corner locks the corner to improve. Mismatch contribution feature provide the direction of optimizing the design. Fast Monte Carlo can be used to do final verification. 25 2014 Cadence Design Systems, Inc. All rights reserved.