Using SPI to Control isppac80 and isppac81 October 2002 Application Note AN6037 Introduction This application note describes how to use the Serial Peripheral Interface (SPI) to adjust the gain, select filter configurations, and start a calibration cycle in either the isppac 80 or isppac81. Both devices feature a front-end instrumentation amplifier (IA) with adjustable gain (in semi-logarithmic steps: 1, 2, 5, and 10) to accommodate a wide range of input signals. Both the isppac80 and isppac81 are designed to store two complete 5 th order lowpass filter configurations ( A and B ) within the non-volatile E 2 CMOS memory. This provides systems with the ability to change, on the fly, the gain, between two filter types, and/or between two corner frequencies. The calibration process nulls offsets automatically to remove the need for trim-pots and provides superior long-term stability. The isppac80 and isppac81 feature both JTAG and SPI support hardware to meet a broad range of programming or embedded scenarios. The JTAG state machine is IEEE 1532 compliant and is the only interface to program or erase the nonvolatile E 2 CMOS memory. The SPI register, on the other hand, is volatile and must be written to after each power-up cycle or before it is used. Also the SPI register can only affect the IA gain, selection of the preprogrammed filter A or B, and calibration. Once the E 2 CMOS memory and the SPI register have been written to, the pin can be used to switch between the two settings. A logic zero on the pin will return the device to the E 2 CMOS settings and raising it to a logic one will invoke the SPI settings. This is illustrated in Figure 1 where a 2:1 multiplexer (MUX) is controlled by the state of the pin. The output of the MUX sets both the gain of the instrumentation amplifier (IA) at the front end, and the filter configuration MUX in the middle. The pin is also used when shifting data into the eight bit SPI register, as will be shown later. Figure 1. isppac80 / isppac81 Data Acquisition System Using SPI 5th Order Low-Pass Filter V s Gain = 1,2,5,10 IA OA VREFout Ain+ Ain- 12- Bit ADC Reference +5V Vs CFG A JTAG/TAP E 2 CMOS SPI REGISTER CFG B Port CPU or DSP GND isppac80 / isppac81 Data Acquisition System Background Both the isppac80 and isppac81 are 5 th order time-continuous low-pass filters that operate on a single +5V supply. The isppac81 is capable of implementing filters with corner frequencies ranging from 11 khz to 75 khz, while www.latticesemi.com 1 an6037_01
the isppac80 covers frequencies from 50 khz all the way up to 500 khz (or 750 khz using Butterworth filters). The overlap between the two devices provides a PAC-based solution from 11 khz to 750 khz. PAC-Designer is a Windows based design tool that has simplified 5 th order filter design to a point and click process. The design process is as easy as selecting the filter type (Bessel, Linear Phase 1, Linear Phase 2, Gausian, Butterworth, Legendre, Chebyshev, or Elliptical) and a corner frequency (-3 db point) then clicking on either the simulation or download tool. Over 2,000 unique filters are available for the isppac81 and over 8,000 for the isppac80. For the Chebyshev and Elliptical filters, a variety of pass-band ripple and stop-band characteristics are provided at or near each corner frequency. In addition to the pre-designed filters within the tables, the user can customize the response by adjusting the capacitor values using PAC-Designer. Thus providing a transfer function for almost any situation. Both devices maintain differential signal paths from input to output to maximize noise immunity. The input and output pins are biased at mid-supply around 2.5V to provide maximum signal swing. For an interesting tutorial on Differential Signaling please see application note AN6019, Differential Signaling. SPI Register Bits From this point on, we will refer to either or both devices (isppac80 and isppac81) as simply isppac80/81, because the SPI architecture in each device is the same. Table 1 displays the eight bits of the SPI register, of which only the upper nibble is actually decoded for calibration, filter selection, and gain. Table 1. SPI Control Bits Upper Nibble Lower Nibble Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit1 Bit 0 PG2 PG1 A/B CAL X X X X Bit 7 PG2: Programmable IA Gain Bit 2 (see Table 2 for settings) Bit 6 PG1: Programmable IA Gain Bit 1 (see Table 2 for settings) Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 A/B: Filter configuration bit 0 = Use the A filter configuration 1 = Use the B filter configuration CAL: Initiate calibration sequence 0 = No effect 1 = Initiate calibration sequence and remove offsets. X: Unused bit, write as zero. X: Unused bit, write as zero. X: Unused bit, write as zero. X: Unused bit, write as zero. CAL, bit-4 (10 H ), is set to begin a calibration cycle. This calibration cycle will automatically disconnect the input pins from the IA, apply a zero signal to the IA inputs, null the internal offsets, then return the IA inputs to the pins. Note that during this process the input pins are not shorted and maintain their high input impedance. The process is sometimes called auto-cal and takes approximately 100 ms to complete. During this time the differential output will be zero with both output pins biased at 2.5V, and thus invalid. This feature provides systems with the ability to null offsets both at operating temperatures and routinely over time. This results in drift characteristics over time and temperature that are essentially flat. 2
A/B, bit-5 (20 H ), determines which of the two filter configurations stored in E 2 CMOS will be used. Setting this bit to logic 0 will cause the isppac80/81 to operate using the A configuration, while setting this bit to a logic 1 will cause the device to use the B configuration. Because both A and B configurations are used by the same circuitry to implement the 5 th order low-pass filter, a short delay (less than 1 ms) should be allowed before considering the output to be valid. This will allow the internal nodes of the circuit to stabilize when switching between configurations. The IA gain is controlled by the last two bits PG1 and PG2, bit-6 and bit-7 (40 H and 80 H ), and is independent of the filter configuration selected. Table 2 lists the available gains (in both Volts per Volt and db units) for the different bit combinations. The adjustable gain stage is positioned at the front end of the isppac80/81 to maximize the signal to noise ratio (SNR) for signals of various amplitudes. Table 2. Gain Bit Settings PG2 PG1 SPI Value (Hex) Gain (V/V) Gain (db) 0 0 00 H 1 x 0 db 0 1 40 H 2 x +6 db 1 0 80 H 5 x +14 db 1 1 C0 H 10 x +20 db Changing the Filter Configuration E 2 CMOS has to be programmed with the initial gain and both filter configurations using the JTAG-TAP interface. The recommended and default setting for the E 2 CMOS wake-up bit (set by clicking on the Wakeup = Cfg A MUX in PAC-Designer) is to wake-up in configuration A so that the algorithms can verify all the bits after programming. To activate configuration B, SPI bit-4 must be set by clocking in the eight bits as shown in the timing diagram of Figure 2. Notice in this, and all the timing diagrams that follow, that the signal can either transition from LOW to the active state or remain HIGH. Also the pin (not shown) is high-z at the beginning and end of the diagrams where is active but is not. Figure 2. Timing Diagram for Changing to Configuration B Bit 0 Bit 7 0 0 0 0 0 1 0 0 To return the device to filter configuration A two options are available. First, the pin could be lowered to logic 0, as discussed in the introduction. Alternatively, in cases where the device is left in SPI mode (by keeping the pin active), bit-4 must be reset by clocking in another eight bits. Changing the IA Gain Configuration = B [00100000] 20 Hex Unlike the wake-up bit that was discussed above, the gain bits in E 2 CMOS can assume any valid value. Thus, the power-up gain can be 1, 2, 5, or 10. After power-up, SPI can be used to change the gain by modifying PG1 and PG2 to reflect the desired gain. Figure 3 illustrates the SPI timing diagram to set the gain to 2. 3
Figure 3. Timing Diagram for Setting the Gain to 2X Bit 0 Bit 7 0 0 0 0 0 0 1 0 In some situations it is desirable to have the gain and filter configuration change at the same time. This is not a problem for the isppac80/81, as Figure 4 displays the timing diagram to set the gain to 5X and use configuration B. Figure 4. Timing Diagram for Changing to Configuration B and Gain of 5X Gain = 2X [01000000] 40 Hex Bit 0 Bit 7 0 0 0 0 0 1 0 1 As a reminder, the SPI register must be programmed, before using the pin to switch gains or filter configurations. Calibration CFG-B & Gain = 5X [10100000] A0 Hex The CAL bit can also be set when changing filter configurations or gain, just keep in mind the analog outputs will be invalid for the 100 ms it takes to complete the calibration cycle. Figure 5 indicates a timing diagram where configuration B is used, the gain is set to 2X, and a calibration cycle is started. The CAL bit does not need to be reset (by a subsequent writes to the SPI register) and will start a calibration cycle for each write to the SPI register that it is set. 4
Figure 5. Timing Diagram for Calibration, Gain = 2X, and Configuration B Bit 0 0 0 0 0 1 1 1 0 Bit 7 JTAG / SPI Hardware Considerations In this section a short discussion of the hardware pins is provided. As can be seen in Figure 1, six signals are required to support both JTAG and SPI. Some of the signals have dual roles in both JTAG and SPI, while a few do not. Table 3 summarizes the pins and their respective functions. Table 3. JTAG / SPI Pin Descriptions Calibrate, CFG-B, & Gain = 2X [01110000] 70 Hex Pin JTAG / SPI Name Description JTAG Test Mode Select Controls the test access port (TAP) state machine. Both Test Clock Shifts data in on the rising edge and out on the falling edge. Both Test Data In Data is clocked into the device on the rising edge of. Both Test Data Out Data is valid at the output after the falling edge of. High impedance when =1 and =0. SPI Enable SPI Places the device in SPI mode when HIGH, and JTAG mode when LOW. SPI Chip Select Set LOW to shift data in, and HIGH to latch the eight bits from the input shift register. : Test Mode Select is used in JTAG mode, in conjunction with, to transition from state to state in the Test Access Port (TAP) state machine within the device. The level presented to this pin is clocked in on the rising edge of. : Test Clock is used in both JTAG and SPI modes as the clock input. On the rising edge data (and ) is clocked in, and on the falling edge data is clocked out. : Test Data In is used in both JTAG and SPI for data and command input. Data bits are shifted in one bit at a time with the rising edge of. : Test Data Out is used in both JTAG and SPI as the data output. In JTAG mode, this pin is used to read data out of the device. In SPI mode, it can be thought of as the output of an eight-bit shift register, where is the input to the register. In either mode, it can be connected to the pin of the next device in a chain. In SPI mode this pin will be high-z output when is high. : Enable SPI is used to switch the device into SPI mode, when HIGH, and JTAG mode, when LOW. When both the SPI register and the E 2 CMOS have been written to, this pin can be used to switch between the two setups. : Chip Select is used only in SPI mode, and must be LOW in order to clock data into the input register. When it is returned HIGH, the SPI register is parallel loaded from the input register and the pin is placed in high-z. 5
The SPI (and JTAG) pins on the PAC devices can be driven by any micro port, expansion card, CPLD, or FPGA, etc. A special processor with a built in SPI port is not required, but would also work. JTAG Programming While the focus of this application note has been on the behavior and usage of SPI, a short discussion of the JTAG issues is required to give the complete picture. From Figure 1, it can be seen that both the JTAG and SPI circuits, within the isppac80/81, share the,, and pins. Thus, if the device is to be programmed in system using the ispdownload cable and controlled dynamically with SPI, a hardware multiplexer (MUX) will be needed. The main function of the MUX is to provide a path to the ispdownload cable for programming, and a path to the signals that will control the isppac80/81. In these cases, the E 2 CMOS programming is accomplished using PAC-Designer or ispvm (Lattice Semiconductor Corporation s full-featured IEEE 1532 compliant programming tool). This MUX could be as simple as a set of jumpers, or it could be as sophisticated as a programmable logic device. In Figure 6, three jumpers are placed between pins 1 and 2 to program the device and then moved to pins 2 and 3 to support the SPI signals. Another valid solution can also be realized using tri-state buffers. In Figure 7, the tri-state buffers support SPI when is active (driven from the port pin) and JTAG when is low. Figure 6. JTAG / SPI Jumper MUX ispdownload Cable 1 2 3 4 5 6 7 8 VS NC PLUG GND +5V Jumpers 1-2 2-3 1 2 3 Function JTAG SPI PORT isppac80/81 6
Figure 7. JTAG / SPI Tri-state Buffer MUX 74xx244 +5V ispdownload Cable 1 2 3 4 5 6 7 8 VS NC PLUG GND PORT isppac80/81 Embedded Programming In contrast to hardware, a software MUX could be implemented with separate drivers for JTAG and SPI. The JTAG driver would satisfy the requirement to program the non-volatile E 2 CMOS memory, thus taking place of the programming that would have occurred using either PAC-Designer or ispvm. The JTAG driver would also place the and pins in an inactive state while sending commands and data to the test access port (TAP) state machine. Likewise, the SPI driver would activate the and pins while clocking in the eight bits of data. Figure 8 illustrates how the hardware interface is simplified when using a more flexible software solution. For examples and support code to implement this type of a system, please contact the Lattice isppac Applications department at the factory. Figure 8. JTAG / SPI Software MUX PORT JTAG Driver SPI Driver isppac80/81 7
Multiple Devices In cases where multiple devices are used, it is possible to bus a portion of the common signals together, and daisy-chain the data lines. This is illustrated in Figure 9 where three isppac80/81s are connected in a JTAG / SPI chain. When programming using JTAG, all three pins need to be inactive and programming may occur either serially or in turbo mode. In serial mode, each device is programmed while the others are in bypass mode. When in bypass, each device acts like a single bit flip-flop, adding a bit to the data stream. In turbo mode, all devices are programmed at the same time, and the data stream grows by the size of each device s data register. However, when using SPI only the turbo mode is available and all the devices in the chain are updated at the same time. This is shown in Figure 10, where a stream of 24 bits (8 bits X 3 devices) are shifted into the pin of isppac80/81 #3. Thus all the pins are bussed together, but the pins are available individually. This is so that after all the devices have been configured (both E 2 CMOS and SPI), each one can be individually switched from the SPI configuration to the E 2 CMOS configuration. Although isppac80/81 #3 is connected to the pin of the port, the LSB of device #1 is shifted out first, as shown in Figure 10, and the MSB of device #3 is shifted out last. Figure 9. JTAG / SPI Chain of Three isppac80/81 Devices JTAG Chain Driver _3 SPI Chain Driver isppac80/81 #3 PORT _2 isppac80/81 #2 _1 isppac80/81 #1 8
Figure 10. Timing Digagram for Chain of Three isppac80/81 Devices x x x x 0 1 0 0 x x x x 0 1 1 0 x x x x 0 1 0 1 isppac80/81 #1 CFG=B Gain=1 [00000100] 20 H isppac80/81 #2 CFG=B Gain=2 [00000110] 60 H isppac80/81 #3 CFG=B Gain=5 [00000101] A0 H Conclusion In this application note we have seen how to change the gain, alter filter configurations, and initiate an auto-cal using SPI. The pin can be used, after the SPI register and E 2 CMOS have been written, to switch between two sets of gains, filter types, and/or corner frequencies. Both the SPI and JTAG signals can be chained together to support multiple devices in an embedded environment. By timing examples, we have seen that any digital or parallel can be used to clock data into the SPI pins, and that a processor with integral SPI hardware is not required. Using SPI, one can truly take advantage of the two 5 th order low-pass filters built into one chip and the time saving design software from Lattice Semiconductor Corporation. Technical Support Assistance Hotline: e-mail: 1-800-LATTICE (Domestic) 1-408-826-6002 (International) isppacs@latticesemi.com Related Literature AN6017, Using the isppac 80 Programmable Lowpass Filter IC AN6019, Differential Signaling AN6030, Using the isppac81 to Suppress Out-of-Band Sensor Resonance isppac80 Data Sheet isppac81 Data Sheet ispvm System Software Version 9.0 and Higer Data Sheet Lattice Releases Industry s First Full-Featured IEEE 1532 Compliant Programming Tool 9