International Journal for Science and Emerging

International Journal for Science and Emerging ISSN No. (Online):2250-3641 Technologies with Latest Trends 6(1): 1-6 (2013) ISSN No. (Print): 2277-8136 Multi-Objective Genetic Algorithm for FPGA Testing Vinay Chopra* and Dr. Amardeep Singh** A.P. (Department of Computer Science)* DAV Institute of Engg & Tech. Jalandhar, India Professor (Department of Computer Science)** UCoE Punjabi University. Patiala, India (Received 10 March 2013 Accepted 14 March 2013) Abstract:This paper gives a concise introduction to Multi-Objective Genetic Algorithms and FPGAs and it reveals that how Automatic Test Pattern Generation method can be formulated in terms of CNF form which in turn used to generate test patterns using Multi-Objective Genetic Algorithm. By applying a Multi-Objective Genetic Algorithm on this CNF form, it has been observed from the experiments that as the problem size are increased by increasing number of variables and clauses, the fault coverage ratio increases. It also has been shown that Multiobjective Genetic Algorithm can be applied to variety of SAT instances of FPGA test pattern generation problem, which gives competitive results. Keywords: FPGAs, CNF, MOGA, DAG, SAT, ATPG, PODEM, FAN 1. Introduction to FPGA Testing FPGA testing or ATPG[1] is a major research topic which is used in semiconductor electrical testing in which the vectors or input patterns are required to check a device for faults that are automatically generated by a program. The input vector patterns are sequentially applied to the device under test and its corresponding response is compared with the expected response from a good circuit. If any error occurs it means that the circuit is faulty. The effectiveness of the ATPG is considered largely by the fault coverage achieved and the cost of conducting the test. Mainly three types of approaches have been recommended for sequential circuits The Topological Approach [2, 3], Symbolic Approach [4] and the Simulation based Approach [5, 6]. Automatic Test Pattern Generation (ATPG) consist of two distinct phases, firstly a creation of the test vector and secondly an application of the test vector. In the first phase, suitable models for the FPGA circuit are developed at gate or transistor level in a way so that the output responses of a faulty device for a given set of inputs will be different from those of good devices [7]. An efficient test vector is which make an efficient use of memory space, time taken during fault coverage and minimum set of test vectors must generated to detect all the important faults of a device [8]. The parameters that should be kept in mind during the design of test vector suit are the time needed to construct the minimal test set, size of the pattern generator( hardware/software system needed to properly stimulate the devices under test),size of the testing process itself, time needed to load the test patterns,external equipment etc. Automatic Test Pattern Generation (ATPG) methods that are mostly used include the D-Algorithm [9], the PODEM [10], and the FAN [11]. 2. Introduction to Multi-objective Genetic Algorithm Multi-objective optimization problems (MOPs) [12, 13] are common Optimization Problem. A general MOP includes a set of parameters (decision variables), a set of k objective functions, and a set of m constraints. Objective functions and constraints are functions of the decision variables. Multi-Objective Genetic Algorithms (GA) imitate the biological processes fundamental classic Darwinian evolution for finding solutions to optimization or classification

2 Chopra and Singh problems. The implementation is based on finding a population of candidate solutions (or chromosomes) which is evaluated using a fitness function and ranked. From the ranking, candidates are selected from which the next generation is created [14]. The fitness function is a measure of how well a candidate solves the problem. Implementations vary in the choice and practice of the selection method; i.e. the purpose of the selection method is to choose candidates whose Multiobjective Genetic mix will tend to lead to improved candidate solutions in the next generation. The common selection methods are random, Elitist [14], Roulette Wheel Tournament [15], etc. Multiobjective genetic operators provide mixing of chromosome portions from the parent or parents to form the offspring of the next generation. Examples of Multiobjective Genetic operators include crossover, mutation, inversion, etc [16]. The process repeats until either the number of iterations is exceeded or an acceptable solution is found. A generic view of a GA includes: a) Initialization of the initial population. b) Ranking is determined on the evaluation of the fitness functions on each chromosome. c) Mating rights are determined using application of the selection method on the population. d) Application of the multi-objective genetic operators on the chromosomes selected for mating. e) Return to Step #2. The following flowchart shows the main phases used to simulate the working of Multi-objective Genetic Algorithm [17]. 3. Applying Genetic Algorithm to FPGA Test Pattern Generation For applying Genetic Algorithm to FPGA circuit, it is first converted to CNF form. For a given gate, a CNF formula ᵠ is a set of clauses and is represented by conjunction of the CNF formulas of each gate. One of the most illustrious applications of SAT is FPGA routing [18], logic synthesis [19], Automatic Test Pattern Generation (ATPG) [20], testing include delay fault testing and redundancy identification and elimination, functional vector generation.to generate a test pattern for a single fault. a) First extract a formula that defines the set of test patterns that detect the fault. b) Then use a Boolean satisfiability algorithm to satisfy the formula. To extract a formula, a directed acyclic graph [21] is constructed as follows that represents the topological description of the circuit: a) The nodes of the graph are circuit inputs, outputs, gates, and fan-out points and the edges of the graph are circuit lines i.e. wires. b) The sources of the graph are circuit outputs c) And the sinks of the graph are the circuit inputs. Every edge has an associated variable. Fig. 1.20 shows an example circuit and its associated DAG [22]. Fig 2: Example Circuit [22] Fig 1: Flow Chart of Multi-objective genetic Algorithm

Chopra and Singh 3 Fig 3: Associated Directed Acyclic Graph (DAG) [22] 3.1 SAT Representation for FPGA Testing An individual is represented for a SAT instance with variables is a string of bits where each variable is associated to one bit [21]. The search space consist of the set S (i.e. all the possible strings n of bits) and an individual X& clearly corresponds to an assignment.x i represents the truth value of the ith atom and X [i α] represents an individual X& where the ith atom has been set to the value α0. Given an individual X& and a clause c, we use SAT(X, c) to denote the fact that the assignment associated X & satisfies the clause c. 3.2 Fitness Function Given a formula φ and an individual X, the fitness of X is defined to be the number of clauses which are not satisfied by X [119]. eval: S Ɲ eval (X) =card ({c sat(x,c)^ c ε φ}) Where card represents the cardinality of a set. This fitness function will be used in the selection process and stimulate an order on the population [124]. 3.3 Selection Process The selection process [23] takes as input a given population and extracts some individual s assignments according to that selection criterion. The selected individuals are the elected as parents for the evolution process and evolve by crossover operations. It is necessary to keep some diversity in the population to insure an efficient search so that if the selected parents are too close, some region of the search space will not be explored. This diversity of the selected population is achieved by introducing the notion of hamming distance between strings of bits. This distance gives the number of different bits between two strings and can be defined here as: ham: S*S Ɲ ham (X, Y) =card({ X i X X i Y i }) Therefore the function is defined as select: 2S * Ɲ* Ɲ 2S such that select (P, n, d) is the set of the n best X in P according to eval and such that X, Y select (P, n, d), ham(x, Y)>=d. typically, the first generation consists of randomly generated individuals. Next generation individuals are selected on the basis of their fitness values i.e. the more the individual is fit the more it has probability to come into the next generation. Then do crossover operation between the two individuals of the chosen ones. In this work two point and three point crossover is used to obtain the next 10 individuals. Fitness proportionate selection also known as roulette wheel selection is a genetic operator used in Genetic Algorithm for selecting potentially useful solutions for recombination. In this method fitness function assigns fitness to possible solutions or chromosomes which is used to associate a probability of selection with each individual chromosome. While candidate solution with a higher fitness will be less likely to be eliminated, there is still a chance that they may be. A

4 Chopra and Singh roulette wheel with each slice proportional in size to the fitness, [see table 1] shows the selection probability for 11 individuals, linear ranking and selective pressure of 2 together with the fitness value. Individual 1 is the fit individual and occupies the largest interval, whereas individual 10 as the second least fit individual has the smallest interval on the line. Individual 11, the least fit interval, has a fitness value of 0 and get no chance for reproduction. Table 1: Selection probability and fitness value For selecting the mating population the appropriate number of uniformly distributed random numbers (uniform distributed between 0.0 and 1.0) is independently generated [24]. Fig 4: Roulette wheel selection method [25] After selection the mating population consists of the individuals: 1, 2, and 3,5,6,9. The roulette-wheel selection algorithm provides a zero bias but does not guarantee minimum spread. 4. Conclusion This work has revealed that FPGA testing in the form of Boolean SAT, which is a NP complete problem can be proficiently solved using the Multi-Objective Genetic Algorithm by first converting it into the Boolean SAT and representing it as a constraint satisfaction problem. This simulation work reads the BLIF files representing the Xilinx MCNC Benchmark circuits as word file and dynamically circuit graphs are created for above used circuits. Then these graphs are used for FPGA circuit testing using GA procedure and results have shown that as the problem size are increased by increasing number of variables and clauses, the fault coverage ratio increases. Also as the numbers of generations are increased, fault coverage ratio and CPU time to test the circuit for each FPGA circuit has improved. 5. References 1) Görschwin Fey, Junhao Shi and Rolf Drechsler Efficiency of Multi-Valued Encoding in SAT-based ATPG 36th International Symposium on Multiple- Valued Logic Singapore. ISBN: 0-7695- 2532-6, May 17-May 2006. 2) Jie Qin A Brief Introduction to Application-Dependent FPGA Testing Dept. of Electrical and Computer Engineering 200 Broun Hall, Auburn University, AL 36849-5201. 3) Junhao Shi, Görschwin Fey,Rolf Drechsler, Andreas Glowatz, Jürgen Schlöffel and Friedrich Hapke Experimental Studies on SAT-Based Test Pattern Generation for Industrial Circuits 6th International Conference ASICON Vol.2, pp:970-972,24 Oct 2005.

Chopra and Singh 5 4) Paolo Prinetto, Maurizio Rebaudengo, and Matteo Soriza GATTO: A Genetic Algorithm for Automatic Test Pattern Generation for Large Synchronous Sequential Circuits IEEE Transactions on Computer Aided Design Of Integrated Circuits And Systems, Vol. 15, Issue No. 8, August, 1996. 5) Gregor Papa, Tomasz Garbolino,Franc Novak and Andrzej H lawiczka Deterministic Test Pattern Generator Design With Genetic Algorithm Approach Journal of Electrical Engineering, Vol. 58, Issue No. 3, pp:121-127, 2007. 6) Jin-Kao Hao, Frédéric Lardeux and Frédéric Saubion A Hybrid Genetic Algorithm for the Satisfiability Problem LERIA, Bd Lavoisier, F- 49045 Angers Cedex 01, 1998. 7) Tracy Larrabee, member IEEE Test Pattern Generation using Boolean Satisfiability IEEE Transactions on Computer-Aided Design, Vol. 11, Issue No. 1, January 1992. 8) J. Shi G. Fey R. Drechsler A. Glowatz F. Hapke J. Schlöffel PASSAT: Efficient SAT-based Test Pattern Generation for Industrial Circuits Proceedings of IEEE Computer Society Annual Symposium on VLSI, pp: 212-217, 11-12 May 2005. 9) V.D. Aggrawal Test Generation for MOS Circuits Using D-Algorithm 20th IEEE Conference on Design Automation pp: 64-70, 27-29 June 1983. 10) P. Goel, PODEM-X: An Automatic Test Generation System for VLSI Logic Structures 18th IEEE Conference on Design Automation pp: 260-268, 29 June 1981. 11) Fujiwara, H. On the Acceleration of Test Generation Algorithms IEEE Transactions on Computers Vol. C -32, Issue No. 12, pp: 1137-1144, Dec. 1983. 12) Carlos A Coello. A Comparative survey of Evolutionary based Multiobjective Optimization International Journal of Knowledge and information Systems, Vol. 1, pp: 269-308, December 1999. 13) Carlos M. Fonsecay, Peter J. Flemingz, An Overview of Evolutionary Algorithms in Multiobjective Optimization International Journal of Evolutionary Computation, Vol. 3, Issue No.1, pp 1-16,April 7,1995. 14) Kalyanmoy Deb, Associate Member IEEE, Amrit Pratap, Sameer Agarwal, and T. Meyarivan A Fast and Elitist Multiobjective Genetic Algorithm: NSGA-II IEEE Transaction on Evolutionary Computation, Vol.6, pp: 182-197, April 2002. 15) Haiming Lu, Gary G.Yen Member IEEE Multiobjective Optimization Design using Genetic Algorithm Proceedings of the IEEE International Conference on Control Applications pp:1190-1195,september 5-7,2001. 16) Ujjwal Maulik, Sanghamitra Bandyopadhyay, Anirban Mukhopadhyay Multiobjective Genetic Algorithms for Clustering book published by Springer Heidelberg Dordrecht London New York, ISBN 978-3-642-16614-3,e-ISBN 978-3-642-16615-0,2011. 17) Jin-Kao Hao, Frédéric Lardeux and Frédéric Saubion A Hybrid Genetic Algorithm for the Satisfiability Problem LERIA, Bd Lavoisier, F- 49045 Angers Cedex 01, 1998. 18) Gi-Joon Nam and Karem A. Sakallah. Detailed Routing of Complex FPGAs via Search-Based Boolean SAT Symposium on Field Programmable Gate Arrays, Monterey, CA, pp: 167-175, December 2004. 19) L. Andrew C. Field Programmable Gate Array Logic Synthesis using Boolean Satisfiability, M. Tech. Thesis submitted to Graduate Department of Electrical and Computer Engineering Department, University of Toronto 2005. 20) Fadi A. Aloul and Assim Sagahyroon SAT-Based Techniques in Test Vectors

6 Chopra and Singh Generation" International Journal of Advances in Information Technology, Vol. 1, Issue No. 4, November 2010. 21) Fahiem Bacchus, Toby Walash (Eds.) Theory and Applications of Satisfiability Testing 8th Springer International Conference, SAT June 19-23, 2005. 22) Y.L. Wu, S. Tsukiyama, and M. Marek-Sadowska, Graph Based Analysis of 2-D FPGA Routing IEEE Transactions on Computer-Aided Design, pp: 33-44, Jan. 1996. 23) Ujjwal Maulik, Sanghamitra Bandyopadhyay, Anirban Mukhopadhyay Multiobjective Genetic Algorithms for Clustering book published by Springer Heidelberg Dordrecht London New York, ISBN 978-3-642-16614-3,e-ISBN 978-3-642-16615-0,2011. 24) Haiming Lu, Gary G.Yen Member IEEE Multiobjective Optimization Design using Genetic Algorithm Proceedings of the IEEE International Conference on Control Applications pp:1190-1195,september 5-7,2001. 25) Rolf Drechsler, Stephan Eggersglub, Gorschwin Fey and Daniel Tille SATbased Automatic Test Pattern Generation Dagstuhl Seminar Proceedings 08351, Evolutionary test Generation 2009.