a FEATURES High CMRR: db Typ Low Nonlinearity:.% Max Low Distortion:.% Typ Wide Bandwidth: MHz Typ Fast Slew Rate: 9.5 V/ s Typ Fast Settling (.%): s Typ Low Cost APPLICATIONS Summing Amplifiers Instrumentation Amplifiers Balanced Line Receivers Current-Voltage Conversion Absolute Value Amplifier to ma Current Transmitter Precision Voltage Reference Applications Lower Cost and Higher Speed Version of INA5 GENERAL DESCRIPTION The is a monolithic unity-gain, high speed differential amplifier. Incorporating a matched thin film resistor network, the features stable operation over temperature without requiring expensive external matched components. The is a basic analog building block for differential amplifier and instrumentation applications. The differential amplifier topology of the both amplifies the difference between two signals and provides extremely high rejection of the common-mode input voltage. By providing common-mode rejection (CMR) of db typical, the solves common problems encountered in instrumentation design. As an example, the is ideal for performing either addition or subtraction of two signals without using expensive externally matched precision resistors. The large common-mode rejection is made possible by matching the internal resistors to better than.% and maintaining a thermally symmetric layout. Additionally, due to high CMR over frequency, the is an ideal general amplifier for buffering signals in a noisy environment into data acquisition systems. The is a higher speed alternative to the INA5. Featuring slew rates of 9.5 V/µs and a bandwidth of MHz, the offers superior performance to the INA5 for high speed current sources, absolute value amplifiers, and summing amplifiers. REV. F Precision, Unity-Gain Differential Amplifier FUNCTIONAL BLOCK DIAGRAM IN +IN PIN CONNECTIONS REFERENCE IN +IN V REFERENCE IN +IN V REFERENCE IN +IN 8-Lead PDIP (P Suffix) TOP VIEW (Not to Scale) NC = NO CONNECT 8-Lead SOIC (S Suffix) TOP VIEW (Not to Scale) NC = NO CONNECT Header (J Suffix) NC 8 V NC = NO CONNECT 5 7 8 NC 7 V+ OUTPUT 5 SENSE 8 NC 7 V+ OUTPUT 5 SENSE 7 V+ OUTPUT 5 SENSE SENSE +V CC OUTPUT V EE REFERENCE Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9, Norwood, MA -9, U.S.A. Tel: 78/9-7 www.analog.com Fax: 78/-87 Analog Devices, Inc. All rights reserved.
SPECIFICATIONS ELECTRICAL CHARACTERISTICS F B G Parameter Symbol Conditions Min Typ Max Min Typ Max Min Typ Max Unit Offset Voltage V OS V CM = V + + 7 + +7 75 +5 +75 µv Gain Error No Load, V IN = ± V, R S = Ω..8..8..8 % Input Voltage Range IVR (Note ) ± ± ± V Common-Mode Rejection CMR V CM = ± V 85 8 95 8 95 db Power Supply Rejection Ratio PSRR V S = ± V to ± 8 V...7 µv/v Output Swing V O R L = kω ± ±.7 ± ±.7 ± ±.7 V Short-Circuit Current Limit I SC Output Shorted to Ground +5/ 5 +5/ 5 +5/ 5 ma Small-Signal Bandwidth ( db) BW R L = kω MHz Slew Rate SR R L = kω 9.5 9.5 9.5 V/µs Capacitive Load Drive Capability C L No Oscillation pf Supply Current I SY No Load.5.5.5.5.5.5 ma NOTES Input voltage range guaranteed by CMR test. Specifications subject to change without notice. ELECTRICAL CHARACTERISTICS B Parameter Symbol Conditions Min Typ Max Unit Offset Voltage V OS V CM = V 5 +5 +5 µv Gain Error No Load, V IN = ± V, R S = Ω.. % Input Voltage Range IVR ± V Common-Mode Rejection CMR V CM = ± V 75 95 db Power Supply Rejection Ratio PSRR V S = ± V to ± 8 V.7 µv/v Output Swing V O R L = kω ± ±.7 V Slew Rate SR R L = kω 9.5 V/µs Supply Current I SY No Load.. ma Specifications subject to change without notice. ELECTRICAL CHARACTERISTICS F G Parameter Symbol Conditions Min Typ Max Min Typ Max Unit Offset Voltage V OS V CM = V + + + + µv Gain Error No Load, V IN = ± V, R S = Ω.8.5.. % Input Voltage Range IVR ± ± V Common-Mode Rejection CMR V CM = ± V 8 95 75 9 db Power Supply Rejection Ratio PSRR V S = ± V to ± 8 V.7 5. 5 µv/v Output Swing V O R L = kω ± ±.7 ± ±.7 V Slew Rate SR R L = kω 9.5 9.5 V/µs Supply Current I SY No Load.... ma Specifications subject to change without notice. (@ V S = 5 V,, unless otherwise noted.) (@ V S = 5 V, 55 C T A +5 C for B Grade) (@ V S = 5 V, C T A +85 C for F and G Grades) REV. F
WAFER TEST LIMITS (@ V S = 5 V, T A = 5 C, unless otherwise noted.)* GBC Parameter Symbol Conditions Limit Unit Offset Voltage V OS V S = ±8 V.5 mv max Gain Error No Load, V IN = ± V, R S = Ω.8 % max Input Voltage Range IVR ± V min Common-Mode Rejection CMR V CM = ± V 8 db min Power Supply Rejection Ratio PSRR V S = ± V to ±8 V 8 µv/v max Output Swing V O R L = kω ± V max Short-Circuit Current Limit I SC Output Shorted to Ground +5/ 5 ma min Supply Current I SY No Load.5 ma max *Electrical tests are performed at wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed for standard product dice. Consult factory to negotiate specifications based on dice lot qualifications through sample lot assembly and testing. ABSOLUTE MAXIMUM RATINGS Supply Voltage............................... ±8 V Input Voltage......................... Supply Voltage Output Short-Circuit Duration.............. Continuous Storage Temperature Range P, J Package....................... 5 C to +5 C Lead Temperature (Soldering, sec)............ C Junction Temperature......................... 5 C Operating Temperature Range B......................... 55 C to +5 C F, G.................. C to +85 C DICE CHARACTERISTICS. REFERENCE. IN. +IN. V EE 5. SENSE. OUTPUT 7. +V CC 8. NC Package Type JA JC Unit Header (J) 5 8 C/W 8-Lead PDIP (P) C/W 8-Lead SOIC (S) 55 C/W NOTES Absolute maximum ratings apply to both DICE and packaged parts, unless otherwise noted. For supply voltages less than ± 8 V, the absolute maximum input voltage is equal to the supply voltage. θ JA is specified for worst-case mounting conditions, i.e., θ JA is specified for device in socket for header and PDIP packages and for device soldered to printed circuit board for SOIC package. ORDERING GUIDE Temperature Package Package Model Range Description Option GP C to +85 C 8-Lead PDIP P-8 BJ C to +85 C Header H-8B FJ C to +85 C Header H-8B BJ/88C 55 C to +5 C Header H-8B GS C to +85 C 8-Lead SOIC S-8 GS-REEL C to +85 C 8-Lead SOIC S-8 59-959MGA 55 C to +5 C Header H-8B GBC Die NOTES Burn-in is available on commercial and industrial temperature range parts in PDIP and header packages. Consult factory for /88 data sheet. BURN-IN CIRCUIT DIE SIZE.7 inch.7 inch, 5,77 sq. mm (.9 mm.9 mm,.7 sq. mm) SLEW RATE TEST CIRCUIT V IN = V +8V 8V +5V 5V. F. F V OUT = V CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as V readily accumulate on the human body and test equipment and can discharge without detection. Although the features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. WARNING! ESD SENSITIVE DEVICE REV. F
Typical Performance Characteristics COMMON-MODE REJECTION (db) 9 8 7 5 THD+N (%)... A V = R L = R L = k TPC. Small Signal Transient Response k k k M TPC. Common-Mode Rejection vs. Frequency. k k k TPC. Total Harmonic Distortion vs. Frequency TPC. Large Signal Transient Response POWER SUPPLY REJECTION (db) T A = +5 C 9 8 PSRR 7 5 +PSRR k k k M TPC 5. Power Supply Rejection vs. Frequency DIM (%).... k A V = R L =, k k TPC. Dynamic Intermodulation Distortion vs. Frequency 5k INPUT OFFSET VOLTAGE ( V) 8 8 75 5 5 5 5 75 5 5 TEMPERATURE ( C) TPC 7. Input Offset Voltage vs. Temperature CLOSED-LOOP GAIN (db) 5 T A = +5 C k k k M M TPC 8. Closed-Loop Gain vs. Frequency OUTPUT IMPEDANCE ( ) 8 T A = +5 C k k k M TPC 9. Closed-Loop Output Impedance vs. Frequency REV. F
.. R S = R L = k 5 GAIN ERROR (%)... SLEW RATE (V/ s) 9 8 SUPPLY CURRENT (ma). 7. 75 5 5 5 5 75 5 5 TEMPERATURE ( C) TPC. Gain Error vs. Temperature 75 5 5 5 5 75 5 TEMPERATURE ( C) TPC. Slew Rate vs. Temperature 75 5 5 5 5 75 5 TEMPERATURE ( C) TPC. Supply Current vs. Temperature 5 SUPPLY CURRENT (ma) 5 5 SUPPLY VOLTAGE (V) TPC. Supply Current vs. Supply Voltage MAXIMUM OUTPUT VOLTAGE (V) 7.5 5..5. 7.5 5..5 V S = 8V V S = V V S = 9V V S = 5V 8 OUTPUT SOURCE CURRENT (ma) TPC. Maximum Output Voltage vs. Output Current (Source) MAXIMUM OUTPUT VOLTAGE (V) 7.5 5..5. 7.5 5. V S = 8V V S = V V S = 9V.5 V S = 5V 8 OUTPUT SINK CURRENT (ma) TPC 5. Maximum Output Voltage vs. Output Current (Sink) Hz) VOLTAGE NOISE DENSITY (nv/ 8 + V V V + V V V k k TPC. Voltage Noise Density vs. Frequency. TO Hz PEAK-TO-PEAK NOISE TPC 7. Low Frequency Voltage Noise NOTE: EXTERNAL AMPLIFIER GAIN = ; THEREFORE, VERTICAL SCALE = V/DIV. TPC 8. Voltage Noise from khz to khz + V V V REV. F NOTE: EXTERNAL AMPLIFIER GAIN = ; THEREFORE, VERTICAL SCALE = V/DIV. TPC 9. Voltage Noise from khz to khz 5
V SIGNAL ECM +V. F V. F GROUND REFERENCE GROUND REFERENCE (GROUND REFERENCE ) V OUT = V SIGNAL Figure. Serves to Reject Common-Mode Voltages in Instrumentation Systems. Common-Mode Voltages Occur Due to Ground Current Returns. V SIGNAL and E CM Must Be within the Common-Mode Range of. APPLICATIONS INFORMATION The represents a versatile analog building block. In order to capitalize on the fast settling time, high slew rate, and high CMR, proper decoupling and grounding techniques must be employed. Figure illustrates the use of. µf decoupling capacitors and proper ground connections. MAINTAINING COMMON-MODE REJECTION In order to achieve the full common-mode rejection capability of the, the source impedance must be carefully controlled. Slight imbalances of the source resistance will result in a degradation of dc CMR even a 5 Ω imbalance will degrade CMR by db. Also, the matching of the reactive source impedance must be matched in order to preserve the CMRR over frequency. APPLICATION CIRCUITS +5V. F IN E R R REF +5V OUT E = E E 5V OUT +IN E R R Figure. Precision Difference Amplifier. Rejects Common-Mode Signal = (E + E )/ by db Figure 5. 5 V Precision Voltage Reference E E = E E E = E + E E Figure. Precision Unity-Gain Inverting Amplifier Figure. Precision Summing Amplifier +5V. F R R +V OUT REF V OUT E E = (R/R+) E = E E Figure. V Precision Voltage Reference Figure 7. Precision Summing Amplifier with Gain REV. F
E E I = (E E )/R OP8EJ LOAD Figure 8. Differential Input Voltage-to-Current Converter for Low I OUT. OP8EJ maintains 5 fa max input current, allowing I O to be less than pa. IN E +IN E R A R R A E = ( + R/R) (E E ) I R E OUTPUT System Design Requirement Source Impedance Low, Need Low Voltage Noise Performance Source Impedance High OP8 (R S 5 kω). Need Low Current OP Noise OP OP9 OP97 Require Ultrahigh Input Impedance Need Wider Bandwidth and High Speed Suggested Op Amp For A and A OP7, OP7 OP7 (Dual Matched) OP7 (Dual) OP7 OP7 OP7 OP8 OP97 OP OP OP OP OP9 Figure 9. Suitable Instrumentation Amplifier Requirements Can Be Addressed by Using an Input Stage Consisting of A, A, R, and R. The following matrix suggests a suitable amplifier. REV. F 7
OUTLINE DIMENSIONS.8 (.57) MAX 8-Lead Plastic Dual In-Line Package [PDIP] [P Suffix] (N-8) Dimensions shown in inches and (millimeters).75 (9.5).5 (9.7).55 (9.) 8 5.95 (7.9).85 (7.).75 (.98). (.5) BSC.5 (.8) MIN.5 (.8). (.) SEATING PLANE. (.79). (.5). (.5).5 (.7).8 (.).5 (.). (.).5 (8.). (7.87). (7.).5 (.8).5 (.). (.5).5 (.8). (.5).8 (.). (.57).8 (.97).5 (.98). (.) COPLANARITY. 8-Lead Small Outline Package [SOIC] [S Suffix] (R-8) Dimensions shown in millimeters and (inches) 5. (.98).8 (.89) 8 5 SEATING PLANE.7 (.5) BSC. (.) 5.8 (.8).75 (.88).5 (.5).5 (.). (.).5 (.98).7 (.7) 8.5 (.9).5 (.99) 5.7 (.5). (.57) COMPLIANT TO JEDEC STANDARDS MS-AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN C9 /(F) COMPLIANT TO JEDEC STANDARDS MO-95AA CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN 8-Lead Metal Can [TO-99] [J Suffix] (H-8B) Dimensions shown in inches and (millimeters).7 (9.).5 (8.5).5 (8.5).5 (7.75).85 (.7).5 (.9). (.) MAX. (.). (.5) REFERENCE PLANE.5 (.7) MIN.5 (.5) MIN. (.5) BSC.5 (.7) MAX. (5.8) BSC.9 (.8). (.). (.5). (.). (.5) BSC BASE & SEATING PLANE 5 8 7. (.8).8 (.7). (.). (.5) 5 BSC.5 (.).7 (.9) Revision History COMPLIANT TO JEDEC STANDARDS MO-AK CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETERS DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN Location Page / Data Sheet changed from REV. E to REV. F. Changes to ELECTRICAL CHARACTERISTICS............................................................. Changes to ORDERING GUIDE........................................................................... Updated OUTLINE DIMENSIONS........................................................................ 7 8 REV. F