Features n IEEE 802.3af/at and LTPoE Powered Device (PD) Controer n LTPoE Supports Power Leves Up to 90W n LT4275A Supports A of the Foowing Standards: n LTPoE 38.7W, 52.7W, 70W and 90W n IEEE 802.3at 25.5W Compiant n IEEE 802.3af Up to 13W Compiant n LT4275B is IEEE 802.3at/af Compiant n LT4275C is IEEE 802.3af Compiant n 100V Absoute Maximum Input Votage n Wide Junction Temperature Range (40 C to 125 C) n Overtemperature Protection n Integrated Signature Resistor n Externa Hot Swap N-Channe MOSFET for Lowest Power Dissipation and Highest System Efficiency n Programmabe Aux Power Support as Low as 9V n Optiona Support of Non-Standard Low Votage PoE n Avaiabe in 10-Lead MSOP and 3mm 3mm DFN Packages Appications n High Power Wireess Data Systems n Outdoor Security Camera Equipment n Commercia and Pubic Information Dispays n High Temperature Industria Appications LT4275 LTPoE/PoE/PoE PD Controer Description The LT 4275 is a pin-for-pin compatibe famiy of IEEE 802.3 and LTPoE powered device (PD) controers. The LT4275A empoys a proprietary LTPoE cassification scheme, deivering 38.7W, 52.7W, 70W or 90W of power at the PD RJ45 connector. The LT4275A is fuy compatibe with IEEE 802.3. The LT4275B is an IEEE 802.3at compiant, Type 2 (PoE) PD deivering up to 25.5W. The LT4275C is an IEEE 802.3af compiant, Type 1 (PoE) PD deivering up to 13W. The LT4275 interna charge pump provides an N-channe MOSFET soution, eiminating a arger and more costy P-channe MOSFET. A ow R DS(ON) MOSFET aso maximizes power deivery and efficiency, reduces power and heat dissipation, and eases therma design. Startup inrush current is adjustabe with an externa capacitor. The LT4275 aso incudes a power good output, on-board signature resistor, undervotage ockout, and therma protection. The LT4275A/LT4275B drives a singe opto-couper to indicate the power eve of the attached PSE. Pin-seectabe support for non-standard ow votage operation is provided. Auxiiary power override is supported with the pin. The LT4275A can be configured to support a possibe LTPoE, 802.3at and 802.3af power eves with externa component changes. L, LT, LTC, LTM, Linear Technoogy and the Linear ogo are registered trademarks and LTPoE and Hot Swap are trademarks of Linear Technoogy Corporation. A other trademarks are the property of their respective owners. Typica Appication LTPoE 90W Powered Device Interface V (9V TO 60V) DATA PAIR SPARE PAIR C PD 0.1µF HSGATE FDMC86102 3.3k 47nF C PORT V IN ISOLATED POWER SUPPLY RUN V OUT LT4275 Famiy MAX DELIVERED POWER LTPoE 90W LTPoE 70W LTPoE 52.7W LTPoE 38.7W LT4275 GRADE A B C R CLS R CLS RCLASS IEEEUVLO LT4275A T2P OPTO PSE TYPE (TO µp) 25.5W 13W 4275 TA01a 1
LT4275 Absoute Maximum Ratings (Notes 1, 3), Votages... 0.3V to 100V HSGATE Current... ±20mA IEEEUVLO, RCLASS, RCLASS Votages... 0.3V to 8V (and ) Current... ±1.4mA T2P, Votage... 0.3V to 100V T2P, Current...5mA Operating Junction Temperature Range (Note 4) LT4275AI/LT4275BI/LT4275CI...40 C to 85 C LT4275AH/LT4275BH/LT4275CH... 40 C to 125 C Storage Temperature Range... 65 C to 150 C Lead Temperature (Sodering, 10 sec.)...300 C Pin Configuration IEEEUVLO RCLASS RCLASS/NC* TOP VIEW 1 10 2 9 HSGATE 3 11 8 4 7 5 6 T2P/NC* DD PACKAGE 10-LEAD (3mm 3mm) PLASTIC DFN T JMAX = 150 C, θ JC = 5 C/W EXPOSED PAD (PIN 11) IS, MUST BE SOLDERED TO PCB IEEEUVLO RCLASS RCLASS/NC* * RCLASS is not connected in the LT4275B/C versions. T2P is not connected in the LT4275C version. 1 2 3 4 5 TOP VIEW 10 9 8 7 6 MS PACKAGE 10-LEAD PLASTIC MSOP T JMAX = 150 C, θ JC = 45 C/W HSGATE T2P/NC* Order Information LEAD FREE FINISH TAPE AND REEL PART MARKING* 2 MAX PD POWER PACKAGE DESCRIPTION TEMPERATURE RANGE LT4275AIDD#PBF LT4275AIDD#TRPBF LGBS 90W 10-Lead (3mm 3mm) Pastic DFN 40 C to 85 C LT4275AHDD#PBF LT4275AHDD#TRPBF LGBS 90W 10-Lead (3mm 3mm) Pastic DFN 40 C to 125 C LT4275AIMS#PBF LT4275AIMS#TRPBF LTGBT 90W 10-Lead Pastic MSOP 40 C to 85 C LT4275AHMS#PBF LT4275AHMS#TRPBF LTGBT 90W 10-Lead Pastic MSOP 40 C to 125 C LT4275BIDD#PBF LT4275BIDD#TRPBF LGBV 25.5W 10-Lead (3mm 3mm) Pastic DFN 40 C to 85 C LT4275BHDD#PBF LT4275BHDD#TRPBF LGBV 25.5W 10-Lead (3mm 3mm) Pastic DFN 40 C to 125 C LT4275BIMS#PBF LT4275BIMS#TRPBF LTGBW 25.5W 10-Lead Pastic MSOP 40 C to 85 C LT4275BHMS#PBF LT4275BHMS#TRPBF LTGBW 25.5W 10-Lead Pastic MSOP 40 C to 125 C LT4275CIDD#PBF LT4275CIDD#TRPBF LGBX 13W 10-Lead (3mm 3mm) Pastic DFN 40 C to 85 C LT4275CHDD#PBF LT4275CHDD#TRPBF LGBX 13W 10-Lead (3mm 3mm) Pastic DFN 40 C to 125 C LT4275CIMS#PBF LT4275CIMS#TRPBF LTGBY 13W 10-Lead Pastic MSOP 40 C to 85 C LT4275CHMS#PBF LT4275CHMS#TRPBF LTGBY 13W 10-Lead Pastic MSOP 40 C to 125 C Consut LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a abe on the shipping container. Consut LTC Marketing for information on nonstandard ead based finish parts. For more information on ead free part marking, go to: http://www.inear.com/eadfree/ For more information on tape and ree specifications, go to: http://www.inear.com/tapeandree/
Eectrica Characteristics LT4275 The denotes the specifications which appy over the fu operating temperature range, otherwise specifications are at T A = 25 C. (Note 3) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Operating Input Votage At Pin 23 60 V V SIG Signature Range At Pin 1.5 10 V V CLASS Cassification Range At Pin 12.5 21 V V MARK Mark Range At Pin, Preceded by V CLASS 5.6 10 V Aux Mode Range At Pin, > V T 8 60 V Signature/Cass Hysteresis Window 1.0 V V RESET Reset Threshod 2.6 5.6 V V HSON Hot Swap Turn-On Votage IEEEUVLO = 0V IEEEUVLO Open V HSOFF Hot Swap Turn-Off Votage IEEEUVLO = 0V IEEEUVLO Open Hot Swap On/Off Hysteresis Window 3 V Suppy Current Suppy Current = = 57V 2 ma Suppy Current During Cassification = 17.5V, RCLASS and RCLASS Open 0.4 0.7 1.1 ma Suppy Current During Mark Event V MARK 0.5 2.2 ma Signature and Cassification Signature Resistance V SIG (Note 2) 23.7 24.4 25.2 kω Signature Resistance During Mark Event V MARK (Note 2) 5.8 8.3 11 kω V RCLS RCLASS/RCLASS Operating Votage 10mA I RCLASS 36mA, V CLASS 1.32 1.40 1.43 V Cassification Stabiity Time Step to 17.5V, RCLASS = 34.8Ω 2 ms Anaog/Digita Interface V T Threshod 6.1 6.3 6.5 V I H Pin Hysteresis Current = 6.1V 4 5.8 8 µa T2P Output Low 1mA Load (LT4275A/LT4275B Ony) 0.8 V Output Low 1mA Load 0.8 V Leakage Current = 60V 5 µa T2P Leakage Current T2P = 60V 5 µa Hot Swap Contro I GPU HSGATE Pu-Up Current V HSGATE V = 5V, > 42V, Out of Pin 18 22 27 µa V GOC HSGATE Open Circuit Votage V HSGATE V, 0µA to 10µA Load with Respect 10 18 V to HSGATE Pu-Down Current V HSGATE V = 5V 200 µa Timing f T2P T2P Frequency After Vaid, if LTPoE PSE Is Mutuay Identified 690 840 990 Hz 30 21.5 35 27 31 22.5 37 29 V V V V Note 1: Stresses beyond those isted under Absoute Maximum Ratings may cause permanent damage to the device. Exposure to any Absoute Maximum Rating condition for extended periods may affect device reiabiity and ifetime. Note 2: Signature resistance specifications do not incude resistance added by the externa diode bridge which can add as much as 1.1k to the port resistance. Note 3: A votages with respect to uness otherwise noted. Positive currents are into pins; negative currents are out of pins uness otherwise noted. Note 4: This IC incudes overtemperature protection that is intended to protect the device during momentary overoad conditions. Junction temperature wi exceed 150 C when overtemperature protection is active. Continuous operation above the specified maximum operating junction temperature may impair device reiabiity. 3
LT4275 Typica Performance Characteristics CURRENT (ma) 0.5 0.4 0.3 0.2 0.1 Current vs Votage 25k Detection Range Hot Swap Threshods Suppy Current During Power-On T = 40 C T = 25 C T = 75 C T = 125 C VOLTAGE (V) 37 36 35 34 33 32 31 IEEEUVLO = 0V Hot Swap ON Hot Swap OFF SUPPLY CURRENT (ma) 2.0 1.5 1.0 0.5 T = 40 C T = 25 C T = 75 C T = 125 C 0 0 2 4 6 VOLTAGE (V) 8 10 4275 G01 30 50 25 0 25 50 75 TEMPERATURE ( C) 100 125 4275 G02 0 35 40 45 50 VOLTAGE (V) 55 60 4275 G03 SIGNATURE RESISTANCE (kω) 26.25 25.75 25.25 24.75 24.25 Signature Resistance vs Input Votage Hot Swap Threshods Reset Threshod T = 40 C T = 25 C T = 75 C T = 125 C VOLTAGE (V) 29.0 27.5 26.0 24.5 23.0 IEEEUVLO = FLOAT Hot Swap ON Hot Swap OFF VOLTAGE (V) 5.6 5.1 4.6 4.1 3.6 3.1 23.75 1 3 5 7 VOLTAGE (V) 9 4275 G04 21.5 50 25 0 25 50 75 TEMPERATURE ( C) 100 125 4275 G05 2.6 50 25 0 25 50 75 TEMPERATURE ( C) 100 125 4275 G06 VOLTAGE (V) 4 3 2 1, T2P Output Low Votage vs Current Cassification Threshods T2P Frequency T = 40 C T = 25 C T = 75 C T = 125 C VOLTAGE (V) 12.5 12.0 11.5 11.0 10.5 DETECT OR MARK TO CLASS CLASS TO MARK T2P FREQUENCY (Hz) 990 940 890 840 790 740 0 0 1 2 3 CURRENT (ma) 4 5 4275 G07 10.0 50 25 0 25 50 75 TEMPERATURE ( C) 100 125 4275 G08 690 50 25 0 25 50 75 TEMPERATURE ( C) 100 125 4275 G09 4
Pin Functions IEEEUVLO (Pin 1): Hot Swap Turn-on Threshod Leve Contro. Connect to ground for IEEE compiant turn-on and turn-off (UVLO) votage threshods. Leave open for ower turn-on and turn-off votage threshods. (Pin 2): Auxiiary Sense. Assert via a resistive divider from the auxiiary power input to set the votage at which the auxiiary suppy takes over. Asserting pus down HSGATE, disconnects the signature resistor, disabes cassification and foats the pin. The pin sinks I H when beow its threshod votage of V T to provide hysteresis. Tie to when not used. RCLASS (Pin 3): Programmabe PoE Cassification Resistor. See Tabe 1. RCLASS (Pin 4, LT4275A Ony): Programmabe LTPoE Cassification Resistor. This pin is not connected on the LT4275B/LT4275C. See Tabe 1. (Pin 5): Ground Pin. Must be sodered to PCB. LT4275 T2P (Pin 6, LT4275A/LT4275B Ony): PSE Type Indicator, Open-Drain Output. T2P foats for a 13W PSE. T2P pus down for a 25.5W PSE. T2P pus down at f T2P with a 50% (typica) duty cyce to indicate the presence of an LTPoE PSE. T2P is vaid after is active. This pin is not connected on the LT4275C. See the Appications Information section for behavior when using the pin. (Pin 7): Power Good Indicator, Open-Drain Output. Pus down during V CLASS and inrush. (Pin 8): Externa Hot Swap MOSFET Source. Connect to source of the externa MOSFET. HSGATE (Pin 9): Externa Hot Swap MOSFET Gate Contro, Output. Connect to gate of the externa MOSFET. (Pin 10): PD interface upper power rai and externa Hot Swap MOSFET drain connection. Exposed Pad (Pin 11, DFN Package Ony):. Must be sodered to PCB. Bock Diagram VOLTAGE AND CURRENT REFERENCES IEEEUVLO CONTROL LOGIC ON CHARGE PUMP HSGATE V GOC 6.3V OVERTEMP T2P RCLASS CLASSIFICATION 1.4V 1.4V LOGIC EN EN RCLASS 4275 BD 5
LT4275 Appications Information Overview POWER ON Power over Ethernet (PoE) continues to gain popuarity as products take advantage of DC power and high speed data avaiabe from a singe RJ45 connector. Powered device (PD) equipment vendors are running into the 25.5W power imit estabished by the IEEE 802.3 standard. The LT4275A aows higher power whie maintaining backwards compatibiity with existing PSE systems. The LT4275 utiizes a ow R DS(ON) N-channe MOSFET to maximize efficiency and deivered power. Heat is aso reduced, easing therma design. V HSON V HSOFF V CLASSMIN V SIGMAX V RESET V SIGMIN DETECT CLASS 4275 F01 Modes of OPERATION The LT4275 has severa modes of operation depending on the input votage sequence appied to the pin. These modes incude 25kΩ signature detection, cassification, mark, inrush and powered on. Detection During detection, the PSE ooks for a 25kΩ signature resistor which identifies the device as a PD. The PSE wi appy two votages in the range of 2.8V to 10V and measure the corresponding currents. Figure 1 shows the detection votages. The PSE cacuates the signature resistance using a V/ I measurement technique. The LT4275 presents its precision, temperature-compensated 24.4k resistor between the and pins, aowing the PSE to recognize a PD is present and requesting power to be appied. The LT4275 signature resistor is smaer than 25k to compensate for the additiona series resistance introduced by the IEEE required bridge. Figure 1. Type 1 Detect/Cass Signaing Waveform A Type 2 PSE may decare the avaiabiity of high power by performing 2-event (Physica Layer) cassification or by communicating over the (Data Link Layer) high speed data ine. A Type 2 PD must recognize both types of communication. Since Layer 2 communications takes pace directy between the PSE and the PD appication, the LT4275A/LT4275B responsibiity ends with supporting 2-event cassification. In 2-event cassification, a Type 2 PSE probes for power cassification twice as shown in Figure 2. The LT4275A or LT4275B recognizes this and pus the T2P pin down to signa the oad that Type 2 power is avaiabe. If an LT4275A senses an LTPoE PSE it aternates between puing T2P down and foating T2P at a rate of f T2P. V HSON V HSOFF POWER ON CLASSIFICATION The detection/cassification process varies depending on whether the PSE is Type 1, Type 2, or LTPoE. A Type 2 PSE may use Type 1 cassification signaing and ater renegotiate a higher power cassification with the PD over the data ayer. A Type 1 PSE, after a successfu detection, may appy a cassification probe votage of 15.5V to 20.5V and measure current. 1ST CLASS 2ND CLASS V CLASSMIN V SIGMAX DETECT V RESET 1ST MARK 2ND MARK V SIGMIN 4275 F01 Figure 2. Type 2 Detect/Cass Signaing Waveform 6
Appications Information Tabe 1. Cassification Codes, Power Leves and Resistor Seection LT4275 PD POWER NOMINAL CLASS LT4275 GRADE CAPABILITY RESISTOR CLASS AVAILABLE PD TYPE CURRENT A B C R CLS R CLS 0 13W Type 1 <0.4mA Open Open 1 3.84W Type 1 10.5mA 140Ω Open 2 6.49W Type 1 18.5mA 76.8Ω Open 3 13W Type 1 28mA 49.9Ω Open 4 25.5W Type 2 40mA 34.8Ω Open 4* 38.7W LTPoE 40mA Open 34.8Ω 4* 52.7W LTPoE 40mA 140Ω 46.4Ω 4* 70W LTPoE 40mA 76.8Ω 64.9Ω 4* 90W LTPoE 40mA 49.9Ω 118Ω *An LTPoE PD wi be cassified as cass 4 by an IEEE 802.3 compiant PSE. LTPoE CLASSIFICATION The LT4275A aows higher power aocation whie maintaining backwards compatibiity with existing PSE systems by extending the cassification signaing of IEEE 802.3. Linear Technoogy PSE controers that are capabe of LTPoE are isted in the Reated Parts section. IEEE PSEs wi cassify an LTPoE PD as a Type 2 PD. SIGNATURE CORRUPT During Mark During the mark state, the LT4275 presents <11kΩ to the port as required by the IEEE specification. power deivery and efficiency, reduces power and heat dissipation, and eases therma design. The pin is hed ow by its open drain output unti HSGATE charges up to approximatey 7V above. The pin is used to hod off the isoated power suppy unti inrush is compete and the externa MOSFET is fuy enhanced. The HSGATE pin wi remain high and the pin pued down unti the port votage fas beow V HSOFF or the pin is above V T. I INRUSH 3.3k C PORT Inrush and Powered On Once the PSE detects and optionay cassifies the PD, the PSE then powers on the PD. When the port votage rises above the V HSON threshod, it begins to source I GPU out of the HSGATE pin. This current fows into an externa capacitor (C GATE in Figure 3) that causes a votage to ramp up the gate of the externa MOSFET. The externa MOSFET acts as a source foower and ramps the votage up on the output buk capacitor (C PORT in Figure 3) thereby determining the inrush current (I INRUSH in Figure 3). To meet IEEE requirements, design I INRUSH to be approximatey 100mA. See equation beow: I INRUSH = I GPU C PORT C GATE The LT4275 interna charge pump provides an N-channe MOSFET soution, eiminating a arger and more costy P-channe FET. The ow R DS(ON) MOSFET aso maximizes HSGATE LT4275A 4275 F03 C GATE Figure 3. Programming I INRUSH ILIARY SUPPLY Override If the pin is hed above V T, the LT4275 enters auxiiary power suppy override mode. In this mode the signature resistor is disconnected, cassification is disabed, HSGATE is pued down, and the pin is aowed to foat. The T2P pin pus down on the LT4275A/ LT4275B when no R CLS resistor is present. The T2P pin aternates between puing down and foating at f T2P on the LT4275A when the R CLS resistor is present. 7
LT4275 Appications Information The pin aows for setting the auxiiary suppy turn on (V ON ) and turn off (V OFF ) votage threshods. The auxiiary suppy hysteresis votage (V HYS ) is set by sinking current (I H ) ony when the pin votage is ess than V T. Use the foowing equations to set V ON and V OFF via R1 and R2 in Figure 4. R1= V ON V OFF I H R1 R2 = V OFF 1 V T R1 V (MAX) V T 1.4mA 8 = V HYS I H V LT4275A Figure 4. Threshod and Hysteresis Cacuation Therma Protection R1 R2 4275 F04 The IEEE 802.3 specification requires a PD to withstand any appied votage from 0V to 57V indefinitey. During cassification, however, the power dissipation in the LT4275 may be as high as 1.5W. The LT4275 can easiy toerate this power for the maximum IEEE timing but wi overheat if this condition persists abnormay. The LT4275 incudes a therma protection feature which protects itsef from excessive heating. If the junction temperature exceeds the overtemperature threshod, the LT4275 pus down the HSGATE and pins and disabes cassification. Externa INTERFACE and Component Seection Input Diode Bridge The input diode bridge introduces a votage drop that affects the votage range for each mode of operation. The LT4275 is designed to toerate these votage drops. The votages shown in the Eectrica Specifications are measured at the LT4275 package pins. Input Capacitor A 0.1µF capacitor is needed from to to meet an input impedance requirement in IEEE 802.3. Transient Votage Suppressor The LT4275 specifies an absoute maximum votage of 100V and is designed to toerate brief overvotage events. However, the pins that interface to the outside word can routiney see excessive peak votages. To protect the LT4275, insta a unidirectiona transient votage suppressor (TVS) such as an SMAJ58A between the port votage and. This TVS must be mounted near the LT4275. For extremey high cabe discharge and surge protection contact Linear Technoogy Appications. Cassification Resistor (R CLS and R CLS ) The R CLS resistors set the cassification oad current corresponding to the PD power cassification. Seect the vaue of R CLS from Tabe 1 and connect the resistor between the RCLASS pin and, or foat the RCLASS pin if cass 0 is required. The resistor toerance must be 1% or better to avoid degrading the overa accuracy of the cassification circuit. For LTPoE use the LT4275A and seect the vaue of R CLS from Tabe 1 in addition to R CLS. Power Good Interface The LT4275 provides a power good signa () to simpify the isoated power suppy design. The power good signa is used to deay isoated power suppy startup unti the C PORT capacitor is fuy charged. Exposed Pad The LT4275A/LT4275B/LT4275C DFN package has an exposed pad that is internay eectricay connected to. The exposed pad may ony be connected to on the printed circuit board. LAYOUT CONSIDERATIONS Avoid excessive parasitic capacitance on the RCLASS pin and pace resistor R CLS cose to the LT4275. For the LT4275A, pace R CLS nearby as we. It is stricty required for maximum protection to pace the input capacitor (C PD ) and transient votage suppressor as cose to the LT4275 as possibe.
Typica Appications LT4275 IEEE 802.3af (Type 1) 13W Powered Device ETHERNET MAGNETICS C PD 0.1µF SMAJ58A FDN8601 HSGATE 3.3k 47nF LT4275A/LT4275B/LT4275C C PORT V IN ISOLATED POWER SUPPLY RUN V OUT R CLS RCLASS IEEEUVLO T2P 4275 TA02 IEEE 802.3at (Type 2) 25.5W Powered Device ETHERNET MAGNETICS C PD 0.1µF SMAJ58A FDN8601 HSGATE 3.3k 47nF C PORT V IN ISOLATED POWER SUPPLY RUN V OUT R CLS LT4275A/LT4275B RCLASS IEEEUVLO T2P OPTO PSE TYPE (TO µp) 4275 TA03 LTPoE 38.7W to 90W Powered Device WÜRTH 749022016 C PD 0.1µF FDMC86102 SMAJ58A 3.3k HSGATE 47nF C PORT V IN ISOLATED POWER SUPPLY RUN V OUT R CLS R CLS LT4275A RCLASS IEEEUVLO T2P OPTO PSE TYPE (TO µp) 4275 TA04 9
LT4275 Package Description Pease refer to http://www.inear.com/designtoos/packaging/ for the most recent package drawings. DD Package 10-Lead Pastic DFN DD (3mm Package 3mm) 10-Lead Pastic DFN (3mm 3mm) (Reference LTC DWG # 05-08-1699 Rev C) (Reference LTC DWG # 05-08-1699 Rev C) 0.70 ±0.05 3.55 ±0.05 2.15 ±0.05 1.65 ±0.05 (2 SIDES) PACKAGE OUTLINE 0.25 ±0.05 0.50 BSC 2.38 ±0.05 (2 SIDES) RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS R = 0.125 TYP 6 10 0.40 ±0.10 PIN 1 TOP MARK (SEE NOTE 6) 0.200 REF 3.00 ±0.10 (4 SIDES) 0.75 ±0.05 0.00 0.05 1.65 ±0.10 (2 SIDES) (DD) DFN REV C 0310 5 1 0.25 ±0.05 0.50 BSC 2.38 ±0.10 (2 SIDES) BOTTOM VIEW EXPOSED PAD PIN 1 NOTCH R = 0.20 OR 0.35 45 CHAMFER NOTE: 1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-2). CHECK THE LTC WEBSITE DATA SHEET FOR CURRENT STATUS OF VARIATION ASSIGNMENT 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 10
Package Description Pease refer to http://www.inear.com/designtoos/packaging/ for the most recent package drawings. LT4275 MS Package 10-Lead Pastic MSOP (Reference LTC DWG # 05-08-1661 Rev E) 0.889 ± 0.127 (.035 ±.005) 5.23 (.206) MIN 3.20 3.45 (.126.136) 0.305 ± 0.038 (.0120 ±.0015) TYP 0.50 (.0197) BSC RECOMMENDED SOLDER PAD LAYOUT 3.00 ± 0.102 (.118 ±.004) (NOTE 3) 10 9 8 7 6 0.497 ± 0.076 (.0196 ±.003) REF GAUGE PLANE 0.18 (.007) 0.254 (.010) DETAIL A DETAIL A NOTE: 1. DIMENSIONS IN MILLIMETER/(INCH) 2. DRAWING NOT TO SCALE 0 6 TYP 0.53 ± 0.152 (.021 ±.006) SEATING PLANE 4.90 ± 0.152 (.193 ±.006) 1.10 (.043) MAX 0.17 0.27 (.007.011) TYP 1 2 3 4 5 0.50 (.0197) BSC 3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX 3.00 ± 0.102 (.118 ±.004) (NOTE 4) 0.86 (.034) REF 0.1016 ± 0.0508 (.004 ±.002) MSOP (MS) 0307 REV E Information furnished by Linear Technoogy Corporation is beieved to be accurate and reiabe. However, no responsibiity is assumed for its use. Linear Technoogy Corporation makes no representation that the interconnection of its circuits as described herein wi not infringe on existing patent rights. 11
LT4275 Typica Appication 25W PD Soution with 12VDC and 24VAC Auxiiary Input V 9V TO 57VDC OR 24VAC MMSD4148 (2pcs) B2100 (4pcs) 470µF TO ISOLATED POWER SUPPLY MMSD4148 158k 0.1µF FDN8601 13 WÜRTH 7499511001 8.2Ω 15 SMAJ58A 0.1µF HSGATE 3.3k 16 14 112 TO PHY B2100 (8pcs) 931k 34.8Ω RCLASS IEEEUVLO LT4275A/LT4275B T2P 4275 TA05 OPTO 47nF TO ISOLATED POWER SUPPLY RUN PSE TYPE (TO µp) Reated Parts PART NUMBER DESCRIPTION COMMENTS LTC4257-1 IEEE 802.3af PD Interface Controer Interna 100V, 400mA Switch, Dua Current Limit, Programmabe Cass LTC4263 Singe IEEE 802.3af PSE Controer Interna FET Switch LTC4265 IEEE 802.3at PD Interface Controer Interna 100V, 1A Switch, 2-Event Cassification Recognition LTC4266 Quad IEEE 802.3at PoE PSE Controer With Programmabe I CUT /I LIM, 2-Event Cassification LTC4266A Quad LTPoE PSE Controer Provides Up to 90W. Backwards Compatibe with IEEE 802.3af and IEEE 802.3at PDs. With Programmabe I CUT /I LIM, 2-Event Cassification LTC4266C Quad IEEE 802.3af PSE Controer With Programmabe I CUT /I LIM, 1-Event Cassification LTC4267-3 IEEE 802.3af PD Interface with Integrated Interna 100V, 400mA Switch, Programmabe Cass, 300kHz Constant Frequency PWM Switching Reguator LTC4269-1 IEEE 802.3af PD Interface with Integrated Fyback Switching Reguator 2-Event Cassification, Programmabe Cass, Synchronous No-Opto Fyback Controer, 50kHz to 250kHz, Aux Support LTC4269-2 IEEE 802.3af PD Interface with Integrated Forward Switching Reguator LTC4270/LTC4271 12-Port PoE/PoE/LTPoE PSE Controer 2-Event Cassification, Programmabe Cass, Synchronous Forward Controer, 100kHz to 500kHz, Aux Support Transformer Isoation, Supports IEEE 802.3af, IEEE 802.3at and LTPoE PDs LTC4274 Singe IEEE 802.3at PoE PSE Controer With Programmabe I CUT /I LIM, 2-Event Cassification LTC4274A Singe LTPoE PSE Controer Provides Up to 90W. Backwards Compatibe with IEEE 802.3 PDs. With Programmabe I CUT /I LIM, 2-Event Cassification LTC4274C Singe IEEE 802.3af PSE Controer With Programmabe I CUT /I LIM, 1-Event Cassification LTC4278 IEEE 802.3af PD Interface with Integrated Fyback Switching Reguator 2-Event Cassification, Programmabe Cass, Synchronous No-Opto Fyback Controer, 50kHz to 250kHz, 12V Aux Support LTC4290/LTC4271 8-Port PoE/PoE/LTPoE PSE Controer Transformer Isoation, Supports IEEE 802.3af, IEEE 802.3at and LTPoE PDs 12 LT 0712 PRINTED IN USA Linear Technoogy Corporation 1630 McCarthy Bvd., Mipitas, CA 95035-7417 (408) 432-1900 FAX: (408) 434-0507 www.inear.com LINEAR TECHNOLOGY CORPORATION 2012