High Speed, Low Power Monolithic Op Amp AD847

a FEATURES Superior Performance High Unity Gain BW: MHz Low Supply Current:.3 ma High Slew Rate: 3 V/ s Excellent Video Specifications.% Differential Gain (NTSC and PAL).9 Differential Phase (NTSC and PAL) Drives Any Capacitive Load Fast Settling Time to.% ( V Step): 6 ns Excellent DC Performance High Open-Loop Gain. V/mV (R LOAD = k ) Low Input Offset Voltage:. mv Specified for V and V Operation Available in a Wide Variety of Options Plastic DIP and SOIC Packages Cerdip Package Die Form MIL-STD-883B Processing Tape & Reel (EIA-8A Standard) Dual Version Available: AD827 (8 Lead) Enhanced Replacement for LM636 Replacement for HA2, HA2/2/ and EL APPLICATIONS Video Instrumentation Imaging Equipment Copiers, Fax, Scanners, Cameras High Speed Cable Driver High Speed DAC and Flash ADC Buffers PRODUCT DESCRIPTION The AD87 represents a breakthrough in high speed amplifiers offering superior ac & dc performance and low power, all at low cost. The excellent dc performance is demonstrated by its ± V High Speed, Low Power Monolithic Op Amp AD87 CONNECTION DIAGRAM Plastic DIP (N), Small Outline (R) and Cerdip (Q) Packages specifications which include an open-loop gain of 3 V/V ( Ω load) and low input offset voltage of. mv. Commonmode rejection is a minimum of 78 db. Output voltage swing is ±3 V into loads as low as Ω. Analog Devices also offers over 3 other high speed amplifiers from the low noise AD829 (.7 nv/ Hz) to the ultimate video amplifier, the AD8, which features.% differential gain and. differential phase. APPLICATION HIGHLIGHTS. As a buffer the AD87 offers a full-power bandwidth of 2.7 MHz ( V p-p with ± V supplies) making it outstanding as an input buffer for flash A/D converters. 2. The low power and small outline package of the AD87 make it very well suited for high density applications such as multiple pole active filters. 3. The AD87 is internally compensated for unity gain operation and remains stable when driving any capacitive load. 6 QUIESCENT CURRENT ma.. SUPPLY VOLTAGE ± Volts Quiescent Current vs. Supply Voltage AD87 Driving Capacitive Loads Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 96, Norwood, MA 62-96, U.S.A. Tel: 67/329-7 Fax: 67/326-873

SPECIFICATIONS (@ T A = +2 C, unless otherwise noted) Model AD87J AD87AR Conditions V S Min Typ Max Min Typ Max Units INPUT OFFSET VOLTAGE ± V.. mv T MIN to T MAX 3. mv Offset Drift µv/ C INPUT BIAS CURRENT ± V, ± V 3.3 6.6 3.3 6.6 µa T MIN to T MAX 7.2 µa INPUT OFFSET CURRENT ± V, ± V 3 3 na T MIN to T MAX na Offset Current Drift.3.3 na/ C OPEN-LOOP GAIN V OUT = ±2. V ± V R LOAD = Ω 2 3. 2 3. V/mV T MIN to T MAX V/mV R LOAD = Ω.6.6 V/mV V OUT = ± V ± V R LOAD = kω 3. 3. V/mV T MIN to T MAX.. V/mV DYNAMIC PERFORMANCE Unity Gain Bandwidth ± V 3 3 MHz Full Power Bandwidth 2 ± V MHz V OUT = V p-p R LOAD = Ω, ± V 2.7 2.7 MHz V OUT = V p-p, R LOAD = kω ± V.7.7 MHz Slew Rate 3 R LOAD = kω ± V V/µs ± V 22 3 22 3 V/µs Settling Time to.%, R LOAD = 2 Ω 2. V to +2. V ± V 6 6 ns V Step, A V = ± V 6 6 ns to.%, R LOAD = 2 Ω 2. V to +2. V ± V ns V Step, A V = ± V ns Phase Margin C LOAD = pf ± V R LOAD = kω Degree Differential Gain f. MHz, R LOAD = kω ± V.. % Differential Phase f. MHz, R LOAD = kω ± V.9.9 Degree COMMON-MODE REJECTION V CM = ±2. V ± V 78 9 78 9 db V CM = ±2 V ± V 78 9 78 9 db T MIN to T MAX 7 7 db POWER SUPPLY REJECTION V S = ± V to ± V 7 86 7 86 db T MIN to T MAX 72 72 db INPUT VOLTAGE NOISE f = khz ± V nv/ Hz INPUT CURRENT NOISE f = khz ± V.. pa/ Hz INPUT COMMON-MODE VOLTAGE RANGE ± V +.3 +.3 V 3. 3. V ± V +.3 +.3 V 3. 3. V OUTPUT VOLTAGE SWING R LOAD = Ω ± V 3. 3.6 3. 3.6 ±V R LOAD = Ω ± V 2. 3 2. 3 ±V R LOAD = kω ± V 2 2 ±V R LOAD = Ω ± V ±V Short-Circuit Current ± V 32 32 ma INPUT RESISTANCE 3 3 kω INPUT CAPACITANCE.. pf OUTPUT RESISTANCE Open Loop Ω POWER SUPPLY Operating Range. 8. 8 V Quiescent Current ± V.8 6..8 6. ma T MIN to T MAX 7.3 7.3 ma ± V.3 6.3.3 6.3 ma T MIN to T MAX 7.6 7.6 ma NOTES l Input Offset Voltage Specifications are guaranteed after minutes at T A = +2 C. 2 Full Power Bandwidth = Slew Rate/2 π V PEAK. 3 Slew Rate is measured on rising edge. All min and max specifications are guaranteed. Specifications in boldface are % tested at final electrical test. Specifications subject to change without notice. 2

Model AD87AQ AD87S Conditions V S Min Typ Max Min Typ Max Units INPUT OFFSET VOLTAGE ± V.. mv T MIN to T MAX mv Offset Drift µv/ C INPUT BIAS CURRENT ± V, ± V 3.3 3.3 µa T MIN to T MAX 7. 7. µa INPUT OFFSET CURRENT ± V, ± V 3 3 na T MIN to T MAX na Offset Current Drift.3.3 na/ C OPEN-LOOP GAIN V OUT = ±2. V ± V R LOAD = Ω 2 3. 2 3. V/mV T MIN to T MAX V/mV R LOAD = Ω.6.6 V/mV V OUT = = ± V ± V R LOAD = kω 3. 3. V/mV T MIN to T MAX.. V/mV DYNAMIC PERFORMANCE Unity Gain Bandwidth ± V 3 3 MHz ± V MHz Full Power Bandwidth 2 V OUT = V p-p R LOAD = Ω, ± V 2.7 2.7 MHz V OUT = V p-p, R LOAD = kω ± V.7.7 MHz Slew Rate 3 R LOAD = kω ± V V/µs ± V 22 3 22 3 V/µs Settling Time to.%, R LOAD = 2 Ω 2. V to +2. V ± V 6 6 ns V Step, A V = ± V 6 6 ns to.%, R LOAD = 2 Ω 2. V to +2. V ± V ns V Step, A V = ± V ns Phase Margin C LOAD = pf ± V R LOAD = kω Degree Differential Gain f. MHz, R LOAD = kω ± V.. % Differential Phase f. MHz, R LOAD = kω ± V.9.9 Degree COMMON-MODE REJECTION V CM = ±2. V ± V 8 9 8 9 db V CM = ±2 V ± V 8 9 8 9 db T MIN to T MAX 7 7 db POWER SUPPLY REJECTION V S = ± V to ± V 7 86 7 86 db T MIN to T MAX 72 72 db INPUT VOLTAGE NOISE f = khz ± V nv/ Hz INPUT CURRENT NOISE f = khz ± V.. pa/ Hz INPUT COMMON-MODE VOLTAGE RANGE ± V +.3 +.3 V 3. 3. V ± V +.3 +.3 V 3. 3. V OUTPUT VOLTAGE SWING R LOAD = Ω ± V 3. 3.6 3. 3.6 ±V R LOAD = Ω ± V 2. 3 2. 3 ±V R LOAD = kω ± V 2 2 ±V R LOAD = Ω ± V ±V Short-Circuit Current ± V 32 32 ma INPUT RESISTANCE 3 3 kω INPUT CAPACITANCE.. pf OUTPUT RESISTANCE Open Loop Ω POWER SUPPLY Operating Range. 8. 8 V Quiescent Current ± V.8.7.8.7 ma T MIN to T MAX 7. 7.8 ma ± V.3 6.3.3 6.3 ma T MIN to T MAX 7.6 8. ma 3

ABSOLUTE MAXIMUM RATINGS Supply Voltage................................ ±8 V Internal Power Dissipation 2 Plastic (N)...............................2 Watts Small Outline (R)..........................8 Watts Cerdip (Q)............................... Watts Input Voltage................................... ±V S Differential Input Voltage........................ ±6 V Storage Temperature Range (Q)......... 6 C to + C (N, R)........................... 6 C to +2 C Junction Temperature.......................... 7 C Lead Temperature Range (Soldering 6 sec)....... +3 C NOTES Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 Mini-DIP Package: θ JA = C/Watt; θ JC = 33 C/Watt Cerdip Package: θ JA = C/Watt; θ JC = 3 C/Watt Small Outline Package: θ JA = C/Watt; θ JC = 33 C/Watt ESD SUSCEPTIBILITY ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as volts, which readily accumulate on the human body and on test equipment, can discharge without detection. Although the AD87 features proprietary ESD protection circuitry, permanent damage may still occur on these devices if they are subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid any performance degradation or loss of functionality. METALIZATION PHOTOGRAPH Contact factory for latest dimensions. Dimensions shown in inches and (mm). ORDERING GUIDE Temperature Package Package Models* Range C Description Option AD87JN to +7 Plastic N-8 AD87JR to +7 SOIC R-8 AD87AQ to +8 Cerdip Q-8 AD87AR to +8 SOIC R-8 AD87SQ to +2 Cerdip Q-8 AD87SQ/883B to +2 Cerdip Q-8 962-8967PA to +2 Cerdip Q-8 *AD87 also available in J and S grade chips, and AD87JR and AD87AR are available *in tape and reel.

Typical Characteristics (@ +2 C and V S = V, unless otherwise noted) INPUT COMMON-MODE RANGE ± Volts +V IN V IN OUTPUT VOLTAGE SWING Volts +V OUT V OUT R LOAD = Ω SUPPLY VOLTAGE ± Volts Figure. Input Common-Mode Range vs. Supply Voltage SUPPLY VOLTAGE ± Volts Figure 2. Output Voltage Swing vs. Supply Voltage 3 6 OUTPUT VOLTAGE SWING Volts p-p 2 ± V SUPPLIES ±V SUPPLIES QUIESCENT CURRENT ma.. k k LOAD RESISTANCE Ω Figure 3. Output Voltage Swing vs. Load Resistance SUPPLY VOLTAGE ± Volts Figure. Quiescent Current vs. Supply Voltage INPUT BIAS CURRENT µa 3 V = ± V S OUTPUT IMPEDANCE Ω. 2 6 6 8 TEMPERATURE C Figure. Input Bias Current vs. Temperature. k k M M M FREQUENCY Hz Figure 6. Output Impedance vs. Frequency

Typical Characteristics (@ +2 C and V S = V, unless otherwise noted) 7 3 QUIESCENT CURRENT ma 6 V = ± V S SHORT CIRCUIT CURRENT LIMIT ma 3 2 3 6 6 8 TEMPERATURE C Figure 7. Quiescent Current vs. Temperature 6 6 8 AMBIENT TEMPERATURE C Figure 8. Short-Circuit Current Limit vs. Temperature 2 + UNITY GAIN BANDWIDTH MHz 9 OPEN -LOOP GAIN db 8 6 ±V SUPPLIES Ω LOAD ±V SUPPLIES kω LOAD +8 +6 + + PHASE MARGIN DEGREES 8 6 6 8 TEMPERATURE C Figure 9. Gain Bandwidth Product vs. Temperature k k k M FREQUENCY Hz M Figure. Open-Loop Gain and Phase Margin vs. Frequency M 8 OPEN-LOOP GAIN db 7 7 6 6 V = ±V S V = ± V S POWER SUPPLY REJECTION db 8 6 +SUPPLY SUPPLY k k LOAD RESISTANCE Ω Figure. Open-Loop Gain vs. Load Resistance k k k M M M FREQUENCY Hz Figure 2. Power Supply Rejection vs. Frequency 6

3 CMR db 8 6 V CM = ±V p-p OUTPUT VOLTAGE Volts p p 2 R = kω L k k k M M M FREQUENCY Hz Figure 3. Common-Mode Rejection vs. Frequency M M M INPUT FREQUENCY Hz Figure. Large Signal Frequency Response 7 OUTPUT SWING FROM TO ± V 8 6 2 2 6 %.% %.% HARMONIC DISTORTION db 8 9 2ND HARMONIC 3V RMS R =kω L 3RD HARMONIC 8 6 8 6 SETTLING TIME ns Figure. Output Swing and Error vs. Settling Time 3 k k k FREQUENCY Hz Figure 6. Harmonic Distortion vs. Frequency INPUT VOLTAGE NOISE nv/ Hz 3 SLEW RATE V/µs 3 3 2 k k k M M FREQUENCY Hz Figure 7. Input Voltage Noise Spectral Density 6 6 8 TEMPERATURE C Figure 8. Slew Rate vs. Temperature 7

Figure 9. Inverting Amplifier Configuration Figure 9a. Inverter Large Signal Pulse Response Figure 9b. Inverter Small Signal Pulse Response Figure. Noninverting Amplifier Configuration Figure a. Noninverting Large Signal Pulse Response Figure b. Noninverting Small Signal Pulse Response 8

OFFSET NULLING The input offset voltage of the AD87 is very low for a high speed op amp, but if additional nulling is required, the circuit shown in Figure 2 can be used. +V S C F OUTPUT IN +IN Figure 2. Offset Nulling INPUT CONSIDERATIONS An input resistor (R IN in Figure ) is required in circuits where the input to the AD87 will be subjected to transient or continuous overload voltages exceeding the ±6 V maximum differential limit. This resistor provides protection for the input transistors by limiting the maximum current that can be forced into their bases. For high performance circuits it is recommended that a resistor (R B in Figures 9 and ) be used to reduce bias current errors by matching the impedance at each input. The offset voltage error will be reduced by more than an order of magnitude. THEORY OF OPERATION The AD87 is fabricated on Analog Devices proprietary complementary bipolar (CB) process which enables the construction of pnp and npn transistors with similar f T s in the 6 MHz to 8 MHz region. The AD87 circuit (Figure 22) includes an npn input stage followed by fast pnps in the folded cascode intermediate gain stage. The CB pnps are also used in the current amplifying output stage. The internal compensation capacitance that makes the AD87 unity gain stable is provided by the junction capacitances of transistors in the gain stage. The capacitor, C F, in the output stage mitigates the effect of capacitive loads. At low frequencies and with low capacitive loads, the gain from the compensation node to the output is very close to unity. In this case C F is bootstrapped and does not contribute to the compensation capacitance of the part. As the capacitive load is increased, a pole is formed with the output impedance of the output stage. This reduces the gain, and therefore, C F is incompletely bootstrapped. Some fraction of C F contributes to the compensation capacitance, and the unity gain bandwidth falls. As the load capacitance is increased, the bandwidth continues to fall, and the amplifier remains stable. NULL NULL 8 Figure 22. AD87 Simplified Schematic GROUNDING AND BYPASSING In designing practical circuits with the AD87, the user must remember that whenever high frequencies are involved, some special precautions are in order. Circuits must be built with short interconnect leads. A large ground plane should be used whenever possible to provide a low resistance, low inductance circuit path, as well as minimizing the effects of high frequency coupling. Sockets should be avoided because the increased interlead capacitance can degrade bandwidth. Feedback resistors should be of low enough value to assure that the time constant formed with the capacitance at the amplifier summing junction will not limit the amplifier performance. Resistor values of less than kω are recommended. If a larger resistor must be used, a small (< pf) feedback capacitor in parallel with the feedback resistor, R F, may be used to compensate for the input capacitances and optimize the dynamic performance of the amplifier. Power supply leads should be bypassed to ground as close as possible to the amplifier pins. Ceramic disc capacitors of. µf are recommended. V S 9

VIDEO LINE DRIVER The AD87 functions very well as a low cost, high speed line driver for either terminated or unterminated cables. Figure 23 shows the AD87 driving a doubly terminated cable in a follower configuration. The termination resistor, R T, (when equal to the cable s characteristic impedance) minimizes reflections from the far end of the cable. While operating from ± V supplies, the AD87 maintains a typical slew rate of V/µs, which means it can drive a ± V, 3 MHz signal into a terminated cable. Figure 2 shows the AD87 driving pf and pf loads. +V S V IN 7Ω COAX R IN Ω 7Ω AD87 V S. µf. µf R BT 7Ω Ω 7Ω COAX R T 7Ω VOUT Figure 2. AD87 Driving Capacitive Loads FLASH ADC INPUT BUFFER The 3 MHz unity gain bandwidth of the AD87 makes it an excellent choice for buffering the input of high speed flash A/D converters, such as the AD98. Figure 2 shows the AD87 as a unity inverter for the input to the AD98. C C SEE TABLE I Ω. AD89 2k.2V Figure 23. Video Line Driver Table I. Video Line Driver Performance Chart Over- V IN * V SUPPLY C C 3 db B W shoot db or ± mv Step ± pf 23 MHz % db or ± mv Step ± pf 2 MHz % db or ± mv Step ± pf 3 MHz % db or ± mv Step ± pf 8 MHz 2% db or ± mv Step ± pf 6 MHz % db or ± mv Step ± pf MHz % * 3 db bandwidth numbers are for the dbm signal input. Overshoot numbers are the percent overshoot of the volt step input. A back-termination resistor (R BT, also equal to the characteristic impedance of the cable) may be placed between the AD87 output and the cable input, in order to damp any reflected signals caused by a mismatch between R T and the cable s characteristic impedance. This will result in a flatter frequency response, although this requires that the op amp supply ±2 V to the output in order to achieve a ± V swing at resistor R T. ANALOG INPUT (V TO +2V) TTL CONVERT SIGNAL.kΩ Ω.kΩ. k AD87 kω AD7 3Ω.µF V IN 27 2N396 R B.µF AD98 CONVERT V EE.2V Figure 2. Flash ADC Input Buffer k R T V CC +.V D (MSB) D8 (LSB).µF

A High Speed, Three Op-Amp In-Amp The circuit of Figure 26 lends itself well to CCD imaging and other video speed applications. It uses two high speed CB process op-amps: Amplifier A3, the output amplifier, is an AD87. The input amplifier (A and A2) is an AD827, which is a dual version of the AD87. This circuit has the optional flexibility of both dc and ac trims for common-mode rejection, plus the ability to adjust for minimum settling time. +V µf.µf +V S EACH AMPLIFIER µf.µf PIN 7 AD87, PIN 8 AD827 COMM V µf.µf V S µf.µf PIN AD87 & AD827 V IN 3 2 R G 6 /2 AD827 A kω kω pf 2kΩ 2kΩ 2 8pF SETTLING TIME AC CMR ADJUST 2 3.87kΩ 2kΩ A3 6 AD87 V OUT R L 2kΩ INPUT FREQUENCY Hz khz khz khz MHz CMRR 88.3dB 87.dB 86.2dB 67.dB 7.dB +V IN A2 7 /2 AD827 DC CMR ADJUST Ω Ω CIRCUIT GAIN = + R G BANDWIDTH, SETTLING TIME AND TOTAL HARMONIC DISTORTION VS. GAIN GAIN R G CADJ (pf) SMALL SIGNAL BANDWIDTH SETTLING TIME TO.% THD + NOISE BELOW INPUT LEVEL @ khz 2 OPEN 2kΩ 226Ω Ω 2 8 2 8 2 8 2 8 6.MHz.7MHz.MHz 66kHz ns ns 37ns 2.µs 82dB 82dB 8dB 7dB Figure 26. A High Speed In-Amp Circuit for Data Acquisition

HIGH SPEED DAC BUFFER The wide bandwidth and fast settling time of the AD87 makes it a very good output buffer for high speed current-output D/A converters like the AD668. As shown in Figure 27, the op amp establishes a summing node at ground for the DAC output. The output voltage is determined by the amplifier s feedback resistor (.2 V for a kω resistor). Note that since the DAC generates a positive current to ground, the voltage at the amplifier output will be negative. A Ω series resistor between the noninverting amplifier input and ground minimizes the offset effects of op amp input bias currents. 2 3 MSB VCC 2 REFCOM 23 REFIN 22 +V µf.µf TO ANALOG GROUND PLANE V NOMINAL + REFERENCE INPUT C9f 9/92 DIGITAL INPUTS REFIN2 2 I OUT AD668 6 RLOAD 9 7 ACOM 8 8 LCOM 7 9 IBPO 6 Ω k k AD87 ANALOG GROUND PLANE.µF µf ANALOG OUTPUT ANALOG SUPPLY GROUND VEE V 2 LSB THCOM VTH 3 pf kω +V Figure 27. High Speed DAC Buffer OUTLINE DIMENSIONS Dimensions shown in inches and (mm). Mini-DIP (N-8) Package Cerdip (Q-8) Package Small Outline (R-8) Package PIN 8.39 (9.9) MAX.2 (6.3).3 (7.87). (.3) MIN. (.) MAX PIN 8.3 (7.87).2 (.9).2 (6.).228 (.79) PIN. (3.8) 8.7 (3.99). (3.8).6±. (.9±.2).2 (3.8) MIN.8±.3 (.6±.8). (2.) BSC.3 (7.62) REF.±.3 (.28±.8).33 (.8) NOM.3±. (.89±.2).8±.3 (.7±.76) SEATING PLANE. (.8) MAX. (.8).2 (3.8).23 (.8). (.36). (.29) MAX. (2.) BSC.3 (8.3).29 (7.37). (.38).8 (.).7 (.78).3 (.76).6 (.2). (.38). (3.8) MIN SEATING PLANE. (.2). (.).97 (.).89 (.8). (.27) BSC. (.) x CHAMF 8.98 (.282).7 (.9).9 (.8). (.36).9 (.82).7 (.32).2 (2.9).9 (2.39).9 (2.29).3 (.76).8 (.6) PRINTED IN U.S.A. All brand or product names mentioned are trademarks or registered trademarks of their respective holders. 2