(19) Europäisches Patentamt European Patent Office Office européen des brevets (11) EP 1 280 033 B1 (12) EUROPEAN PATENT SPECIFICATION (4) Date of publication and mention of the grant of the patent: 31.0.2006 Bulletin 2006/22 (1) Int Cl.: G0F 3/26 (2006.01) G0F 3/24 (2006.01) (21) Application number: 0140203.8 (22) Date of filing: 26.07.2001 (4) EMC immune low drop regulator EMV gerechter Spannungsregler mit kleiner Verlustspannung Régulateur de tension à faible tension de déchet assurant une compatibilité électromagnétique (84) Designated Contracting States: DE FR (43) Date of publication of application: 29.01.2003 Bulletin 2003/0 (73) Proprietor: AMI Semiconductor Belgium BVBA 9700 Oudenaarde (BE) (72) Inventor: Kamenicky, Petr 641 00 Brno (CZ) (74) Representative: Bird, William Edward et al Bird Goen & Co., Klein Dalenstraat 42A 3020 Winksele (BE) (6) References cited: US-A- 436 2 US-A- 699 EP 1 280 033 B1 Note: Within nine months from the publication of the mention of the grant of the European patent, any person may give notice to the European Patent Office of opposition to the European patent granted. Notice of opposition shall be filed in a written reasoned statement. It shall not be deemed to have been filed until the opposition fee has been paid. (Art. 99(1) European Patent Convention). Printed by Jouve, 7001 PARIS (FR)
1 EP 1 280 033 B1 2 Description Field of the invention [0001] The present invention is related to supply regulators. More particularly, the present invention is related to electromagnetic compliant supply regulators. State of the art [0002] Electrical noise has been recognised as a problem for electrical and electronic devices as from the start of electrical engineering itself. Electrical interference and the frequencies at which it occurs are growing with the rapid spread of electrical and electronic devices. [0003] Today, one must recognise that almost any device which operates on the principle of moving an electron from one point to another can be either a source or receiver of Electromagnetic interference (EMI). [0004] When two electrical or electronic devices must operate together in the same environment or in the same system, the potential for conflict between these unintended transmitters and receivers can present significant, and challenging problems. Some problems are obvious in the first prototype of a new device if it tends to self interfere. This can happen when the design results in a strong emitter and a sensitive receiver in the same package. [000] However, if a circuit is only a strong transmitter, or only a sensitive receiver, the potential for later problems is there, but may not be discovered until the design has left the engineering development laboratory, unless the device is tested for electromagnetic compatibility (EMC). [0006] Traditional transconductance regulators are not EMC safe. They can usually be considered as sensitive receivers. Electromagnetic interference will therefore usually lead to instability of the output. Traditional solutions consist of adding filters in the input line for filtering out the EMC noise on this input signal. Such filters are very expensive and require external components. US-A- 436 2 describes clamping circuit clamping a potential level of boost signal Vpp which appears at a node. The clamping circuit of this document comprises a constant current source comprising transistors. The circuit furthermore comprises current mirror consisting of 2 p channel MOS transistors, both having their substrate and source connected together through the node. The clamping transistor has its source and substrate coupled together to the node and its drain connected to reference potential supply node. When the voltage of the node exceeds a constant value, the gate voltage holds a substantially constant value. Since clamping operations are carried out by using one transistor element, a clamping circuit can be implemented with a voltage-current characteristic having rapid rising. In US-A- 699 a voltage regulator is described, 1 20 2 30 3 40 4 0 comprising current source and number of current mirrors. The source terminal of a first p-channel transistor is coupled to the output line. The P-channel transistor has it source connected to its substrate and is connected as a source-follower stage. As a result, RF interference is suppressed more effectively in the voltage regulator and the electromagnetic compatibility (EMC) of the voltage regulator is improved. With the voltage regulator described in this document, effective suppression of effects of the supply voltage is provided from the beginning. As a result, interference due to incoming radio-frequency energy or conducted interference is suppressed. Aims of the invention [0007] The present invention aims to provide EMC immunity to transconductance regulators with a p-type active component. Summary of the invention [0008] The present invention is a voltage regulator circuit for providing a regulated output voltage at an output terminal, said regulator circuit comprising a current source, comprising a current source MOS- FET, a current mirror circuit, comprising a driver MOSFET and a follower MOSFET both having the source connected to the substrate, interposed between said current source and said output terminal, operatively linked as to regulate an input voltage V in to said regulated output voltage, characterised in that the circuit further comprises an EMC stabilising PMOS transistor having its drain connected to its substrate and placed in series with any of said driver or follower MOSFETs. [0009] In an embodiment of the present invention, the gate of the EMC stabilising PMOS transistor is coupled to the gate of the follower MOSFET, and the drain of the EMC stabilising PMOS transistor is coupled to the source of the follower MOSFET. [00] In another embodiment, the source of the EMC stabilising PMOS transistor is coupled to the drain of the follower MOSFET. Preferably, the gate of the EMC stabilising PMOS transistor is kept at a predetermined voltage (V bias ). Said predetermined voltage should preferably be external and independent from the input voltage. [0011] In another embodiment, the drain of the EMC stabilising PMOS transistor is connected to the source of the driver MOSFET. [0012] In a preferred embodiment, the voltage regulator circuit of the invention further comprises a second EMC stabilising MOSFET having its drain connected to its substrate and placed in series with the driver or follower MOSFET. Evidently, this second EMC stabilising 2
3 EP 1 280 033 B1 4 MOSFET is placed in series with the MOSFET of the current mirror that wasn t already stabilised by the first EMC stabilising PMOS transistor. [0013] Preferably, the source of the EMC stabilising PMOS transistor is connected to the drain of the follower MOSFET and the source of the second EMC stabilising MOSFET is connected to the drain of the driver MOSFET, both gates of said EMC stabilising PMOS transistor and said second EMC stabilising MOSFET being connected. [0014] Advantageously, the gates of the EMC stabilising PMOS transistor and the second EMC stabilising MOSFET are kept at a predetermined voltage (V bias ), which should preferably be external and independent from the input voltage. [001] Another aspect of the present invention concerns a method for improving EMC stability of an electronic circuit comprising at least one circuit MOSFET having its source connected to its substrate, characterised by the step of providing an EMC stabilising PMOS transistor having its drain connected to its substrate and being placed in series with said circuit MOSFET. Short description of the drawings [0016] Fig. 1 represents the basic load regulator output structure and its EMC equivalent circuit (preceded by an "equivalent sign". [0017] Figs. 2 and 3 represent embodiments of the present invention and their equivalent EMC circuits. [0018] Fig. 4 represents a preferred embodiment of the present invention and its EMC equivalent circuit. Detailed description of the invention 1 20 2 30 [0020] The drain of the EMC protecting pmos transistor is connected with its substrate or bulk, which in most CMOS processes concerns the n-well. This is opposite the transistors used in most active circuitry, such as for instance the current mirror circuitry of the voltage regulator, which have their sources connected to their substrate. The drain contact of the EMC stabilising PMOS is thus for instance connected via a metal line to the n- well contact. However other variant methods for realising this connection can be envisaged. [0021] A regulated supply according to the present invention will stay regulated and constant even under strong EMC conditions on the input supply rail as will be explained in the next paragraphs. [0022] A basic LD regulator output structure with current mirror, as in the prior art, is shown in fig 1. It has no EMC immunity. Indeed, when the input voltage is lower than the output voltage, load capacitor C Load is discharged rapidly via parasitic diode D 1. This capacitor is charged only via limited current from M 2 when the input voltage is higher than the output voltage. In the case of electromagnetic interference, C Load is thus more discharged than charged and output voltage drops down, which may lead to instability problems. The EMC equivalent of this prior art topology is shown at the right hand side of Fig. 1 [0023] The invention will now be further clarified by means of several non-limiting examples and figures. Example 1: [0024] An improved circuit can be seen in fig.2 (left), together with its EMC equivalent circuit (right). When the input voltage is lower than the output voltage, C Load is discharged via D 1 and M 3 in series; when the input voltage is higher than the output voltage, C Load is charged via D 2 and M 2 in series. Due to the symmetrical structure, C Load keeps its dc charge, making the circuit more EMC stable. [0019] EMC immunity becomes more and more important. The solution presented in this application is simple and low-cost. The present invention comprises the use of a PMOS with its bulk or substrate connected to the drain as an EMC protection between the device to be protected and the node with the EMC disturbance. Any diode between the input supply and the regulated supply is thereby eliminated by means of an additional diode in an anti-series connection. - In the output driver structure: one transistor (M3) is added with its substrate connected to its drain, and possibly biased by a fixed bias source (see examples 1 and 2). - In the control structure: transistor M4, also with bulk connected to drain, and biased by the same fixed bias as M3, is used as a shield to N1 (see example 3). 3 40 4 0 Example 2: [002] In the embodiment of example 1 an additional gate (M 3 ) is connected to net1. This can lead to stability problems. This problem can be solved by using the circuit as provided in fig. 3. On the right is provided its EMC equivalent circuit. [0026] Again, discharging of C Load via D 1 and M 3 in series occurs when the input voltage is lower than the output voltage and when the input voltage is higher than the output voltage, C Load is charged via D 2 and M 2 in series. [0027] V bias is an external voltage source. Such a biasing voltage source can be easily made from a current source and a resistor and will therefore not be further described. Example 3: Preferred Embodiment of the invention [0028] The last problem to be avoided to make the circuit fully EMC compliant is the current source device I control. It is usually built from an n-type device and has a parasitic diode (D 4 ) to the substrate. If an additional circuit is not added, D 4 will cause a dc level shift (up) of V(netl) 3
EP 1 280 033 B1 6 and as a consequence, R on of M 2 will increase and C Load will be discharged. [0029] To avoid this, a transistor M 4 is added, as can be seen on the left in fig.4. D 4 is uncoupled from net1: there is no more n-junction on net1. Even if net1 went negative relative to substrate during an EMI event, this would not influence the output voltage significantly. Also shown on fig. 4 is the EMC equivalent circuit (right). Claims 1. A voltage regulator circuit for providing a regulated output voltage at an output terminal, said regulator circuit comprising a current source (I control ), comprising a current source MOSFET, a current mirror circuit, comprising a driver MOSFET (M 1 ) and a follower MOSFET (M 2 ) both having the source connected to the substrate, interposed between said current source and said output terminal, operatively linked as to regulate an input voltage V in to said regulated output voltage, characterised in that the circuit further comprises an electromagnetic compatibility stabilising PMOS transistor having its drain connected to its substrate, connected between a circuit to be protected and a node with electromagnetic compatibility disturbance, and placed in series with any of said driver or follower MOSFETs. 2. The voltage regulator circuit as in claim 1, wherein the drain of the electromagnetic compatibility stabilising PMOS transistor is coupled to the source of the follower MOSFET. 3. The voltage regulator circuit as in claim 2, wherein the gate of the electromagnetic compatibility stabilising PMOS transistor is coupled to the gate of the follower MOSFET. 4. The voltage regulator circuit as in claim 1, wherein the source of the electromagnetic compatibility stabilising PMOS transistor is coupled to the drain of the follower MOSFET.. The voltage regulator circuit as in claim 4, wherein the gate of the electromagnetic compatibility stabilising PMOS transistor is kept at a predetermined voltage (V bias ). 6. The voltage regulator as in claim, wherein the predetermined voltage is external to and independent from the input voltage. 1 20 2 30 3 40 4 0 7. Voltage regulator circuit as in claim 1, wherein the drain of the electromagnetic compatibility stabilising PMOS transistor is coupled to the source of the driver MOSFET. 8. Voltage regulator circuit as in claim 1, further comprising a second electromagnetic compatibility stabilising MOSFET having its drain connected to its substrate and placed in series with any of the driver or follower MOSFET. 9. The voltage regulator circuit as in claim 8, wherein the source of the electromagnetic compatibility stabilising PMOS transistor is coupled to the drain of the follower MOSFET and the source of the second electromagnetic compatibility stabilising MOSFET is connected to the drain of the driver MOSFET, both gates of said electromagnetic compatibility stabilising PMOS transistor and said second electromagnetic compatibility stabilising MOSFET being connected.. The voltage regulator circuit as in claim 9, wherein the gate of the electromagnetic compatibility stabilising PMOS transistor and the second electromagnetic compatibility stabilising MOSFET are kept at a predetermined voltage (V bias ) which is external to and independent from the input voltage. 11. A method for improving electromagnetic compatibility stability of an electronic circuit comprising at least one circuit MOSFET having its source connected to its substrate, characterised by the step of providing an electromagnetic compatibility stabilising PMOS transistor having its drain connected to its substrate and being placed in series with said circuit MOSFET, and said electromagnetic compatibility stabilising PMOS transistor connected between the electronic circuit and a node with EMC disturbance. Patentansprüche 1. Spannungsreglerschaltung zum Bereitstellen einer geregelten Ausgangspannung an einem Ausgangsanschluss, mit: einer Spannungsquelle (I control ) mit einem Stromquellen-MOSFET, einer Stromspiegelschaltung, die einen Treiber- MOSFET (M 1 ) und einen Folger-MOSFET (M 2 ) beinhaltet, die beide die Source mit dem Substrat verbunden haben, welche zwischen der Stromquelle und dem Ausgangsanschluss zwischengeschaltet ist, der betriebsmäßig verknüpft ist, um eine Eingangsspannung (V in ) in die geregelte Ausgangsspannung zu regeln, 4
7 EP 1 280 033 B1 8 dadurch gekennzeichnet, dass die Schaltung ferner einen elektromagnetisch kompatibilitätsstabilisierenden PMOS-Transistor beinhaltet, dessen Drain mit seinem Substrat verbunden ist, der zwischen eine zu schützende Schaltung und einen Knoten mit elektromagnetischen Kompatibilitätsstörungen verbunden ist und in Serie mit einem der Treiber- oder Folger-MOSFETS angeordnet ist. 2. Spannungsreglerschaltung nach Anspruch 1, wobei Drain des elektromagnetisch kompatibilitätsstabilisierenden PMOS-Transistors mit der Source des Folger-MOSFET gekoppelt ist. 3. Spannungsreglerschaltung nach Anspruch 2, wobei das Gate des elektromagnetisch kompatibilitätsstabilisierenden PMOS-Transistors mit dem Gate des Folger-MOSFET gekoppelt ist. 4. Spannungsreglerschaltung nach Anspruch 1, wobei die Source des elektromagnetisch kompatibilitätsstabilisierenden PMOS-Transistors mit dem Drain des Folger-MOSFET gekoppelt ist.. Spannungsreglerschaltung nach Anspruch 4, wobei das Gate des elektromagnetisch kompatibilitätsstabilisierenden PMOS-Transistors auf eine vorbestimmte Spannung (V bias ) gehalten ist. 6. Spannungsregler nach Anspruch, wobei die vorbestimmte Spannung extern von der Eingangsspannung und unabhängig von der Eingangsspannung ist. 7. Spannungsreglerschaltung nach Anspruch 1, wobei der Drain des elektromagnetisch kompatibilitätsstabilisierenden PMOS-Transistors mit der Source des Treiber-MOSFETS gekoppelt ist. 8. Spannungsreglerschaltung nach Anspruch 1, die ferner einen zweiten elektromagnetisch kompatibilitätsstabilisierenden MOSFET aufweist, dessen Drain mit seinem Substrat verbunden ist und der in Serie mit einem der Treiber- oder Folger-MOSFETS angeordnet ist. 9. Spannungsreglerschaltung nach Anspruch 8, wobei die Source des elektromagnetisch kompatibilitätsstabilisierenden PMOS-Transistors mit dem Drain des Folger-MOSFETS gekoppelt ist und wobei die Source des zweiten elektromagnetisch kompatibilitätsstabilisierenden MOSFETS mit dem Drain des Treiber-MOSFETS verbunden ist, wobei die Gates des elektromagnetisch kompatibilitätsstabilisierenden PMOS-Transistors und des zweiten elektromagnetisch kompatibilitätsstabilisierenden MOSFETS verbunden sind. 1 20 2 30 3 40 4 0. Spannungsreglerschaltung nach Anspruch 9, wobei das Gate des elektromagnetisch kompatibilitätsstabilisierenden PMOS-Transistors und des zweiten elektromagnetisch kompatibilitätsstabilisierenden MOSFETS auf eine vorbestimmte Spannung (V bias ) gehalten sind, welche extern von der Eingangsspannung und unabhängig von der Eingangsspannung ist. 11. Verfahren zum Verbessern einer elektromagnetischen Kompatibilitätsstabilität einer elektronischen Schaltung, die mindestens einen Schaltungs-MOS- FET aufweist, dessen Source mit seinem Substrat verbunden ist, gekennzeichnet durch den Schritt eines Bereitstellens eines elektromagnetisch kompatibilitätsstabilisierenden PMOS-Transistors, dessen Drain mit seinem Substrat verbunden ist und der in Serie mit dem Schaltungs-MOSFET angeordnet ist, wobei der elektromagnetisch kompatibilitätsstabilisierende PMOS-Transistor zwischen der elektronischen Schaltung und einem Knoten mit einer elektromagnetischen Kompatibilitätsstörung verbunden ist. Revendications 1. Circuit régulateur de tension pour fournir une tension de sortie régulée au niveau d une borne de sortie, ledit circuit régulateur comprenant : une source de courant (I control ), comprenant un MOSFET de source de courant, un circuit de miroir de courant, comprenant un MOSFET de pilotage (M 1 ) et un MOSFET suiveur (M 2 ) ayant tous deux la source reliée au substrat, interposés entre ladite source de courant et ladite borne de sortie, lié de manière opérationnelle pour réguler une tension d entrée V in à ladite tension de sortie régulée, caractérisé en ce que le circuit comprend de plus un transistor PMOS stabilisant la compatibilité électromagnétique ayant son drain relié à son substrat, relié entre un circuit à protéger et un noeud subissant une perturbation de compatibilité électromagnétique, et placé en série avec n importe lequel desdits MOSFET de pilotage ou suiveur. 2. Circuit régulateur de tension selon la revendication 1, dans lequel le drain du transistor PMOS de stabilisation de compatibilité électromagnétique est relié à la source du MOSFET suiveur. 3. Circuit régulateur de tension selon la revendication 2, dans lequel la grille du transistor PMOS de stabilisation de compatibilité électromagnétique est reliée à la grille du MOSFET suiveur.
9 EP 1 280 033 B1 4. Circuit régulateur de tension selon la revendication 1, dans lequel la source du transistor PMOS de stabilisation de compatibilité électromagnétique est reliée au drain du MOSFET suiveur.. Circuit régulateur de tension selon la revendication 4, dans lequel la grille du transistor PMOS de stabilisation de compatibilité électromagnétique est maintenue à une tension prédéterminée (V bias ). 6. Régulateur de tension selon la revendication, dans lequel la tension prédéterminée est externe à et indépendante de la tension d entrée. 7. Circuit régulateur de tension selon la revendication 1, dans lequel le drain du transistor PMOS de stabilisation de compatibilité électromagnétique est relié à la source du MOSFET de pilotage. 1 8. Circuit régulateur de tension selon la revendication 1, comprenant de plus un second MOSFET de stabilisation de compatibilité électromagnétique ayant son drain relié à son substrat et placé en série avec n importe lequel des MOSFET de pilotage ou suiveur. 20 2 9. Circuit régulateur de tension selon la revendication 8, dans lequel la source du transistor PMOS de stabilisation de compatibilité électromagnétique est reliée au drain du MOSFET suiveur et la source du second MOSFET de stabilisation de compatibilité électromagnétique est reliée au drain du MOSFET de pilotage, les deux grilles dudit transistor PMOS de stabilisation de compatibilité électromagnétique et dudit second MOSFET de stabilisation de compatibilité électromagnétique étant reliées. 30 3. Circuit régulateur de tension selon la revendication 9, dans lequel les grilles du transistor PMOS de stabilisation de compatibilité électromagnétique et du second MOSFET de stabilisation de compatibilité électromagnétique sont maintenues à une tension prédéterminée (V bias ) qui est externe à et indépendante de la tension d entrée. 11. Procédé pour améliorer la stabilité de compatibilité électromagnétique d un circuit électronique comprenant au moins un circuit MOSFET ayant sa source reliée à son substrat, caractérisé par l étape consistant à prévoir un transistor PMOS de stabilisation de compatibilité électromagnétique ayant son drain relié à son substrat et étant placé en série avec ledit MOSFET de circuit, et ledit transistor PMOS de stabilisation de compatibilité électromagnétique étant relié entre le circuit électronique et un noeud subissant une perturbation de compatibilité électromagnétique (EMC). 40 4 0 6
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