S12XE IPLL Calculator

Freescale Semiconductor User Guide Rev. 1, 08/2009 S12XE IPLL Calculator Suitable to use with the S12XE, XF, XS, and S12P, HY, HA amilies by: Michael Galda Freescale Roznov CSC (TIC Team) 1 Introduction The S12XE (S12XF, S12XS, S12P, S12HY) amily o MCU s include an internal phase-locked loop (IPLL) requency multiplier with an internal ilter as a part o the S12XECRG (or S12CPMU) module. The purpose o the PLL is to generate an internal timebase rom the external resonator signal or rom the internal-reerence clock (S12P and S12HY only). The IPLL allows the internal timebase (usually called the bus clock) to be generated at higher or lower requency than the oscillator signal. The usage o a low-requency resonator acilitates lower power consumption in low-power modes (pseudo stop mode). The usage o a cheaper low-requency resonator with PLL to increase the internal MCU bus clock instead o usage o high-requency external (canned) oscillator, may reduce the inal costs o design. The PLL adds more lexibility in order to generate a wide range o internal MCU bus clock requencies rom the ixed external resonator requency. The user can easily switch between the bus requencies, depending on application perormance or power consumption requirements. Contents 1 Introduction................................... 1 2 IPLL Register Setting Description.................. 2 2.1 PLL Setting Equations....................... 3 3 The IPLL Calculator Application................... 5 3.1 Data Entry................................ 5 4 PLL Sotware Initialization Examples............... 7 4.1 S12XE PLL Init Examples.................... 7 4.2 S12P PLL Init Examples..................... 9 5 Reerences.................................. 12 6 Glossary...13 Freescale Semiconductor, Inc., 2009. All rights reserved.

IPLL Register Setting Description The IPLL allows to set an appropriate internal MCU bus clock, in order to achieve correct timing or the internal MCU modules (like SCI, timer modules, and so on), even i the external resonator requency is not suitable or proper timing. The IPLL (unlike the PLL module on S12(X) ) doesn t require any external ilter components. NOTE Sections reerring to S12P are generally valid also or the S12HY amily, due to module compatibility. 2 IPLL Register Setting Description The SYNR, REFDV, and POSTDIV registers are responsible or the PLL requency settings. The ollowing rules, equations, and requency limitations are considered by the IPLL calculator utility to achieve maximum stability and shortest PLL locking time. Figure 1. The S12XE(XS) SYNR / S12P CPMUSYNR Register The VCOFRQ[1:0] bits are used to conigure the VCO gain or optimal stability and lock time. For correct IPLL operation, the VCOFRQ[1:0] bits have to be selected according to the actual target VCOCLK requency, as shown in the ollowing table: Table 1. VCO Frequency Selection VCOCLK Frequency Ranges VCOFRQ[1:0] 32 MHz <= vco <= 48 MHz 00 48 MHz < vco <= 80 MHz 01 Reserved 10 80 MHz < vco <=120 MHz 11 Setting the VCOFRQ[1:0] bits wrongly can result in a non-unctional IPLL (no locking and/or insuicient stability). Figure 2. The S12XE(XS) CRG Reerence Divider Register (REFDIV) 2 Freescale Semiconductor

IPLL Register Setting Description Figure 3. The S12P CPMU Reerence Divider Register (CPMUREFDIV) The REFFRQ[1:0] bits are used to conigure the internal IPLL ilter or optimal stability and lock time. For correct IPLL operation, the REFFRQ[1:0] bits have to be selected according to actual REFCLK requency as shown in the ollowing table: Table 2. Reerence Clock Frequency Selection REFCLK Frequency Ranges REFFRQ[1:0] 1 MHz <= re <= 2 MHz 00 2 MHz < re <= 6 MHz 01 6 MHz < re <= 12 MHz 10 re > 12 MHz 11 Figure 4. The S12XE(XS ) CRG / S12P CPMU Postdiv Register NOTE I POSTDIV = $00, the PLL is identical to VCO (divide by one). 2.1 PLL Setting Equations 2.1.1 Equations Valid or S12XE VCO = 2 OSC ( SYNDIV + 1) ( REFDIV + 1) Eqn. 1 REF OSC = ( REFDIV +1) Eqn. 2 PLL = 2 VCO ( POSTDIV ) Eqn. 3 Freescale Semiconductor 3

IPLL Register Setting Description I PLL is selected (PLLSEL = 1): = BUS 2 PLL Eqn. 4 2.1.2 Formulas Valid or S12P (S12HY) I PLL is locked (LOCK = 1), then: I PLL is not locked (LOCK = 0), then: PLL = 1+ ( CRG ) ( POSTDIV ) I the external oscillator is enabled (OSCE = 1) PLL engaged external mode (PEE), then: VCO PLL( CPMU ) = 4 REF VCO OSC = ( REFDIV +1) I the external oscillator is disabled (OSCE = 0) PLL Engaged Internal Mode (PEI), then: REF = IRC1 M = 1. 000MHz I PLL is selected (PLLSEL = 1), then: Eqn. 5 Eqn. 6 Eqn. 7 Eqn. 8 = BUS 2 PLL Eqn. 9 Table 3. Frequency Limitations or S12XE, XS, S12P, and S12HY S12XE(XF) S12XS S12P (S12HY) NOTE requency min. max. min. max. min. max. OSC (LCP) 4 16 4 16 4 16 MHz loop-controlled pierce OSC (FSP) 2 40 2 40 - MHz ull-swing pierce OSC (ext.) 2 50 2 50 - MHz external square clock BUS 0.5 50 0.5 40 0.5 32 MHz REF 1 40 1 40 1 40 MHz VCO 32 120 32 120 32 64 MHz NOTE: OSC is limited to 4 16 MHz in LCP mode, 2 40 MHz in FSP mode, and 2 50 MHz or external clk. 4 Freescale Semiconductor

NOTE The ollowing rules help to achieve optimum stability and shortest lock time possible: Use the lowest possible VCO / REF ratio (SYNDIV value). Use the highest possible REFCLK requency REF. 3 The IPLL Calculator Application The IPLL Calculator Application The S12XE IPLL ilter calculator application has been written in ree Borland Turbo C++ Explorer IDE, available at http://www.turboexplorer.com/cpp. Calculator is run by executing the ile S12XE_IPLL_Calc.exe on a PC, running a Windows TM XP OS. The application window shown in Figure 5 is presented. 3.1 Data Entry Figure 5. The S12XE IPLL Calculator The ollowing data is required in order to calculate the correct register values. Freescale Semiconductor 5

The IPLL Calculator Application 3.1.1 The MCU Family Since there are some dierences between S12XE, XS, S12P, and S12HY register settings and requency limitations (See Section 2.1, PLL Setting Equations ), the user has to select the appropriate MCU amily by the radio button. 3.1.2 Oscillator Frequency The oscillator requency in units o MHz is picked rom the Oscillator listbox. A PC mouse or keyboard input can be used. The basic set o the most oten manuactured resonator requencies in range 2 50 MHz are stored in the internal database. Only the integer requency values are available in the list by deault. Uncheck the checkbox window to show the complete list o all manuactured and user-deined requencies rom the internal database. The user can add a new oscillator requency by clicking the Add New Osc button. The user-deined oscillator requency will be stored in the myosc.cg ile in the application directory. The newly-added oscillator requency will appear at the end o the Oscillator list ater restarting the calculator application. Depending on the selected MCU amily, only the valid and suitable oscillator requencies are shown in the Oscillator listbox window. See Table 3 or more details. NOTE I the S12P (S12HY) MCU amily is selected and 1.000 MHz internal reerence clock (IRC) is picked, REF is ixed to IRC1M. REF = IRC1 M = 1. 000MHz Eqn. 10 3.1.3 Bus Frequency The required MCU-bus requency is selected rom the Bus Freq listbox window. Depending on the selected MCU amily, only the bus requencies rom the allowed bus ranges are shown in the Oscillator listbox window. See Table 3 or more details. 3.1.4 Output Results I any bus requency is picked, the correct register settings are calculated by the application, allowed VCO and REF ranges are considered by the application. The SYNR, REFDV, and POSTDIV register values are displayed in hexadecimal ormat in the appropriate boxes. The VCO requency, reerence requency, and maximum PLL lock time are calculated and displayed in the Statistic window. The FDIV (FCLKDIV) register value is important or proper internal lash state-machine timing, in case the internal lash or emulated EEPROM is used by the embedded application. Correct FDIV is chosen rom the appropriate lookup table, depending either on the selected oscillator requency (S12XE, XF, XS), or the internal bus requency (S12P, S12HY). Correct lash clock requency range is checked. 6 Freescale Semiconductor

PLL Sotware Initialization Examples The PLL locking time is deined as ollows: t lock [ μs] = 150 + --------------------------- 256 REF [ MHz] Eqn. 11 4 PLL Sotware Initialization Examples 4.1 S12XE PLL Init Examples 4.1.1 Basic S12XE PLL Init // **** S12XE PLL_init example **** void PLL_init(unsigned char synr, unsigned char redv, unsigned char postdiv) PLLCTL = 0B00000001; // CME=0,PLLON=0,FM1=0,FM2=0,FSTWKP=0,PRE=0,PCE=0,SCME=1 CLKSEL = 0B00000011; // PLLSEL=0,PSTP=0,PLLWAI=0,RTIWAI=1,COPWAI=1 SYNR = synr; // Set the multiplier register REFDV = redv; // Set the divider register POSTDIV = postdiv; // Set the post divider register PLLCTL_PLLON = 1; // Enable the Phase Lock Loop while(!crgflg_lock); // Wait till the PLL VCO is within tolerance CLKSEL_PLLSEL = 1; // Select clock source rom PLLCLK //ECLKCTL_NECLK=0; // Enable the BusClk output at ECLK pin Freescale Semiconductor 7

PLL Sotware Initialization Examples 4.1.2 S12XE PLL Init with Timeout and Status Checking // **** S12XE PLL_init example with status checking and timeout **** // return 0 - OK // 1 - Error - PLL not locked unsigned char PLL_init(unsigned char synr, unsigned char redv, unsigned char postdiv) unsigned int timeout=0x; // aux. var. to make small SW delay PLLCTL = 0B00000001; // CME=0,PLLON=0,FM1=0,FM2=0,FSTWKP=0,PRE=0,PCE=0,SCME=1 CLKSEL = 0B00000011; // PLLSEL=0,PSTP=0,PLLWAI=0,RTIWAI=1,COPWAI=1 SYNR = synr; // Set the multiplier register REFDV = redv; // Set the divider register POSTDIV = postdiv; // Set the post divider register PLLCTL_PLLON = 1; // Enable the Phase Lock Loop // Wait till the PLL VCO is within tolerance while((!crgflg_lock)&&( timeout--!= 0)); i(timeout == 0) // PLL didn't lock or some reason return(1); // return error CRGFLG = 0x10; // Ensure clearing o LOCKIF lag CRGINT_LOCKIE = 1; // Enable PLL lock interrupt to know i it loses clock CLKSEL_PLLSEL = 1; // Select clock source rom PLLCLK i(clksel_pllsel!= 1) // will only be set i the PLL was still locked return(1); // return error i loss o lock return(0); // else return OK // PLL_LOCK_ISR // Triggered when PLL lock status changed (locked / unlocked) #pragma CODE_SEG NON_BANKED interrupt 28 void PLL_LOCK_ISR(void) CRGFLG = 0x10; i(crgflg_lock == 0) //do something here else //do something here // Clear LOCKIF lag #pragma CODE_SEG DEFAULT 8 Freescale Semiconductor

PLL Sotware Initialization Examples 4.2 S12P PLL Init Examples 4.2.1 S12P PLL Init in PEI Mode // **** S12P PLL_init in PEI mode **** // - PLL Engaged, Internal Reerence Clock used void PLL_init_PEI(unsigned char synr, unsigned char redv, unsigned char postdiv) CPMUSYNR = synr; // Set the multiplier register CPMUREFDIV = redv; // Set the re. divider register CPMUPOSTDIV = postdiv;// Set the post divider register while(!cpmuflg_lock); // Wait till the PLL VCO is within tolerance (PLL locked) //now the PLL has been locked and pll = vco / (POSTDIV + 1) //ECLKCTL_NECLK=0; // Enable the BusClk output at ECLK pin 4.2.2 S12P Basic Init in PEE Mode // **** S12P PLL_init in PEE mode **** // - PLL Engaged, External Reerence Clock used void PLL_init_PEE(unsigned char synr, unsigned char redv, unsigned char postdiv) CPMUSYNR = synr; // Set the multiplier register CPMUREFDIV = redv; // Set the re. divider register CPMUPOSTDIV = postdiv;// Set the post divider register //i(osce = 0) then re = IRC1M //i(osce = 1) then re = osc / (REFDIV + 1) CPMUOSC_OSCE = 1; //enable external oscillator OSCE //Wait or the UPOSC bit to be set, indicating the oscillator start up while(cpmuflg_uposc == 0); while(!cpmuflg_lock); // Wait till the PLL VCO is within tolerance (PLL locked) //now the PLL has been locked and pll = vco / (POSTDIV + 1) //ECLKCTL_NECLK=0; // Enable the BusClk output at ECLK pin Freescale Semiconductor 9

PLL Sotware Initialization Examples 4.2.3 S12P Init in PEE Mode with Timeout & Status Checking // **** S12P PLL_init in PEE mode with status checking and timeout **** // - PLL Engaged, External Reerence Clock used // return 0 - OK // 1 - Error - PLL not locked, oscillator start up error unsigned char PLL_init_PEE(unsigned char synr, unsigned char redv, unsigned char postdiv) unsigned int timeout=0x; // aux. var. to make small SW delay unsigned char i; // aux. var. CPMUSYNR = synr; // Set the multiplier register CPMUREFDIV = redv; // Set the re. divider register CPMUPOSTDIV = postdiv;// Set the post divider register //i external oscillator is disabled (OSCE = 0) then re = IRC1M //i external oscillator is enabled (OSCE = 1) then re = osc / (REFDIV + 1) CPMUOSC_OSCE = 1; //enable external oscillator OSCE //Wait or the UPOSC bit to be set, indicating the oscillator start up while((!cpmuflg_uposc)&&(timeout--!= 0)) or(i=0;i<20;i++)asm nop; // total timeout delay > ~ 100ms i(timeout == 0) return(1); // Oscillator doesn't started properly, return error // Wait till the PLL VCO is within tolerance timeout=0x; while((!cpmuflg_lock)&&( timeout--!= 0)); i(timeout == 0) // PLL didn't lock or some reason return(1); // return error CPMUFLG = 0x10; // Ensure clearing o LOCKIF lag CPMUINT_LOCKIE = 1; // Enable PLL lock interrupt - to know i it loses clock CPMUCLKS_PLLSEL = 1; // Select clock source rom PLLCLK i(cpmuclks_pllsel!= 1) // will only be set i the PLL was still locked return(1); // return error i loss o lock return(0); // else return OK //now the PLL has been locked and pll = vco / (POSTDIV + 1) //ECLKCTL_NECLK=0; // Enable the BusClk output at ECLK pin 10 Freescale Semiconductor

PLL Sotware Initialization Examples 4.2.3.1 PLL Lock Interrupt Service Routine // PLL_LOCK_ISR // Triggered when PLL lock status changed (locked / unlocked) #pragma CODE_SEG NON_BANKED interrupt 28 void PLL_LOCK_ISR(void) CPMUFLG = 0x10; i(cpmuflg_lock == 0) //do something here else //do something here // Clear LOCKIF lag #pragma CODE_SEG DEFAULT 4.2.4 S12P Init in PBE Mode First o all, we have to set a valid PEE mode, and then we can switch to PBE mode. To enter the PBE mode rom PEI (PEE) mode take the ollowing steps: 1. Make sure the PLL coniguration is valid: Program the reerence divider (REFDIV[3:0] bits) to divide down the oscillator requency i necessary. 2. Enable the external oscillator (OSCE bit). 3. Wait or the oscillator to start up (UPOSC = 1). 4. Select the oscillator clock as bus clock (PLLSEL = 0). // **** S12P CLK_init in PBE mode **** // - PLL Bypassed, External Oscillator Clock signal used void CLK_init_PBE(unsigned char synr, unsigned char redv, unsigned char postdiv) //CPMUSYNR = synr; // Set the multiplier register - optional //CPMUREFDIV = redv; // Set the re. divider register - optional //CPMUPOSTDIV = postdiv;// Set the post divider register - optional //i (OSCE = 0) then re = IRC1M //i (OSCE = 1) then re = osc / (REFDIV + 1) CPMUOSC_OSCE = 1; //enable external oscillator OSCE //Wait or the UPOSC bit to set, indicating the oscillator start up while(cpmuflg_uposc == 0); //Set the PLLSEL to 0. System clock derived rom OSC now.(bus = osc/2) CPMUCLKS_PLLSEL = 0; //ECLKCTL_NECLK=0; // Enable the BusClk output at ECLK pin Freescale Semiconductor 11

Reerences 4.2.5 Important Notes or S12P PLL Init Writing into the CPMUSYNR or CPMUREFDIV will unlock the PLL.While PLL is unlocked, pll = vco /4 to protect the system rom high-core clock requencies during the PLL stabilization time. I PLL is locked, then pll = vco / (POSTDIV + 1). Since the adaptive spike ilter uses the VCOCLK (rom PLL) to continuously qualiy the external oscillator clock, losing the PLL lock status (LOCK = 0) means losing the oscillator status inormation as well (UPOSC = 0). The impact o losing the oscillator status in PBE mode is as ollows: The MSCAN module, which can be conigured to run on the oscillator clock, may need to be reconigured. The PLLSEL is set automatically and the bus clock is switched back to the PLL clock. Application sotware needs to be prepared to deal with the impact o losing the oscillator status at any time. I external oscillator is disabled (OSCE = 0), then re = IRC1M. I external oscillator is enabled (OSCE = 1), then re = osc / (REFDIV + 1). 5 Reerences MC9S12XEP100 Reerence Manual, MC9S12XEP100RMV1.pd MC9S12XS256 Reerence Manual, MC9S12XS256RMV1.pd MC9S12P Reerence Manual, MC9S12P128.pd Comparsion o the S12XS CRG Module with S12P CPMU Module, AN3622.pd 12 Freescale Semiconductor

Glossary 6 Glossary Term Table 4. Glossary Table Deinition Resonator Oscillator External oscillator OSC BUS VCO REF PEI PEE PBE Common term used or the external ceramic resonator, quartz crystal, or active oscillator clock (canned oscillator). External or internal reerence clock source, used by MCU. external clock reerence source requency o oscillator requency o internal MCU bus clock requency o PLL voltage-controlled oscillator PLL reerence requency PLL engaged Internal 1 MHz reerence clock is used by PLL to derive MCU bus clock (S12P, S12HY only). PLL engaged External reerence clock is used by PLL to derive MCU bus clock (S12P, S12HY only). PLL bypassed External reerence clock is directly used or MCU timing. Freescale Semiconductor 13

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