Serial ATA Seminar SATA II Thorsten Scholz thorsten.scholz@ibs-networks.de 1
Serial ATA Seminar SATA II 2008 Ingenieurbüro T. Scholz, www.ibs-networks.de, all rights reserved No part or whole of this document may be reproduced, transmitted, transcribed, stored in a retrieval system or translated into any language without prior permission of Ingenieurbüro Scholz. This document is provided "as is", without warranty of any kind, neither expressed nor implied, including but not limited to a particular purpose. Ingenieurbüro Scholz may make improvements and/or changes in this document without notice at any time. 2
Contents General Overview Electrical l Interface Data Communication Application Layer SATA Link Expansion SATA Integrated Circuits 3
Serial ATA General Overview Standards Topology Terms and Definitions 4
SATA Overview Responsibilities s Serial ATA International Organization (SATA-IO) www.sata-io.org Dell, HP, Hitachi, Intel, Seagate, Western Digital, Connectors: SFF, www.sffcommittee.com (P)ATA Standards InterNational Committee for Information Technology Standards, T13 Group www.incits.org it www.t13.org 5
SATA Overview Parallel aae ATA ATA = Advanced Technology Attachment Parallel ATA (PATA) 40/80 Pin cable 16 Bit bus width Up to 66 MHz max. Data Rate of 133 MB/s 2 Connections per Controller (Master & Slave) in bus connection 8
SATA Overview Serial ATA Register-compatible with Parallel ATA Command set from PATA-6 used LVD Signaling g Data rates of 1,5 Gbps and 3,0 Gbps Line coding for fault-tolerance and signal integrity Point-to-Point connections (no Master/Slave) 7-Pin Interface May use Spread dspectrum Clocking to reduce EMI 9
SATA Overview Compatibility ty SATA is Software compatible to Parallel ATA Identical Register Interface OS OS Application Application Application Parallel ATA Driver Adapter M S Application Application Application Driver Serial ATA HBA Parallel lata Serial lata 10
SATA Overview Serial ATA Link Speed Data rates of 1,5 Gbps and 3,0 Gbps 20% used for line code Link layer speed of 150/300 MB/s Separate Transmit and Receive Pairs Full-Duplex -operation BUT: only one frame active at a given time Only Handshake/Error Control in backward direction 12
SATA Overview Terms and Definitions to Gen1 Defines SATA Interface with transmission rate of 1,5 Gbps Gen2 Defines SATA Interface with transmission rate of 3,0 Gbps GenX Defines SATA Interface with any transmission rate 13
Serial ATA Electrical Interface Usage Models Cables and Connectors Analog Frontend (AFE) 14
Electrical Interface Usage Models Internal connection Host to Device Short Backplane to Device Long Backplane to Device Internal Cabled Disk Arrays System to System Interconnects Serial Attached SCSI (SAS) 15
Electrical Interface Reference eee Points Layer Association: Physical Interface (PHY) Divided into two Generations: 1 (1,5 Gbps) and 2 (3 Gbps) Reference/Compliance e e Points described by Electrical c Specification: c Gen1i: Gen1m: Gen1x: Internal host to device applications Short backplane and external single-lane lane cabling applications Extended length for long backplane and external multi-lane applications Same association for Generation 2 specifications (Gen2i, ) 16
Electrical Interface Internal Power Cable Cable consists of Pin P1 Contact Description 3,3 Volt 3,3 Volt power and pre-charge 5 Volt power and pre-charge P2 P3 P4 33Vlt 3,3 Volt 3,3 Volt Pre-Charge GND 12 Volt power and pre-charge Ground (GND) P5 P6 P7 GND GND 5 Volt Pre-Charge Device Activity Signal (DAS) or Disable Staggered Spinup (DDS) P8 P9 P10 5 Volt 5 Volt GND 5 AWG 18 wires (1 mm²) P11 P12 DAS/DSS GND 3 wires for voltage 2 wires for GND P13 P14 P15 12 Volt Pre-Charge 12 Volt 12 Volt 35
Electrical Interface Cable Electrical ca Specificationcat Description Gen1i/Gen2i Gen1m/Gen2m Gen1x/Gen2x Connector Impedance 100 Ohms ±15% 100 Ohms ±15% 100 Ohms ±10% Cable Impedance 100 Ohms ±10% 100 Ohms ±10% 100 Ohms ±5% Pair Matching Impedance ±5 Ohms ±5 Ohms ±5 Ohms Common Mode Impedance 20 40 Ohms 20 40 Ohms 25 40 Ohms Maximum Insertion Loss (10-4500 MHz) 6 db 8 db 16 db Maximum Crosstalk (Single Lane) 26 db 26 db - Maximum Crosstalk (Multilane) 30 db 30 db 30 db Maximum Rise Time 25 ps (20/80) 150 ps (20/80) 150 ps (20/80) Maximum Intersymbol Interference 50 ps 50 ps 60 ps Maximum Intra-Pair Skew 10 ps 20 ps 20 ps 47
Electrical Interface Voltage otagelevels es Input and Output voltage levels dependant on usage model Description (all values in mv) Gen_i Gen_m Gen_x Output Voltage 500 (400-600) 400-1600 Gen1 Input Voltage 400 (325-600) 400 (240-600) 275-1600 Output Voltage 400-700 400-1600 Gen2 Input Voltage 275-750 240-750 275-1600 57
Electrical Interface Hot-Plug Surprise Hot-Plug capable Insertion or Removal under power GenXx, GenXm and GenXi in Short Backplane applications AC coupling OS-Aware Hot-Plug capable Insertion or Removal with unpowered or powered backplane Data connector is in defined state The removal of a rotating device should be prevented by the system designer! 58
Electrical Interface Impedance Calibration at Host and Device may employ on-chip impedance matching Host launches a step-waveform Impedance measurement using TDR techniques Adjusts impedance settings as necessary Device assumes calibrated far-end Uses this calibration as reference for its own calibration 59
PHYRDY Electrical Interface Interface Power States Phy logic and PLL are on and active Interface is synchronized and capable of transmitting and receiving data Partial Phy logic in reduced power state Signal lines are at common mode voltage (neutral) Transition latency to PHYRDY no longer than 10 µs Slumber Phy logic in reduced power state Transition latency to PHYRDY no longer than 10 ms 68
Electrical Interface Elasticity ty Buffer Serial ATA allows clock tracking as well as non-tracking implementations For non-tracking implementations an Elasticity Buffer is required Phy layer supports unlimited frame size, Elasticity Buffer is finite Phy layer solution needed Maximum frequency difference is up to 0,5% for an SSC device talking to a non-ssc device Phy layer inserts two ALIGN primitives every 254 DWORDS Elasticity Buffer of 64 Bits (2 DWords) is sufficient 69
Serial ATA Data Communication Task Overview Encoding/Decoding Primitives and Frames Data Flow Frame Information Structure 70
Framing Data Communication Link Layer: Tasks s CRC Generation and Check Flow Control o and Handshaking Encoding and Decoding Scramble / Descrambling for EMI purposes 71
Data Communication Link Layer: Encoding Character to be transmitted consists of 8 Data Bits and Control indicator Control indicator bit is D for data and K for control information Total of 8+1 Bit to be encoded to 10 Bit (8B/10B code) Unencoded Bits are named A to H, Control indicator named Z Each character is given a name by Zxx.y with Z is the value of the control indicator xx is the decimal value of bits A to E y is the decimal value of bits F to H Bit 7 6 5 4 3 2 1 0 Ctrl Unencoded H G F E D C B A Z Ntti Notation y xx Z 72
Data Communication Link Layer: Notation o Notation of 0xBC Control 0b10111100 K K28.5 Notation ti of f0x4a 4AData 0b01001010 D D10.2 Only 2 control characters exist: K28.3 and K28.5 If not stated otherwise Control variable Z is always D Bit 7 6 5 4 3 2 1 0 Ctrl Unencoded H G F E D C B A Z Ntti Notation y xx Z 73
Data Communication Link Layer: Encoding Scheme e Widmer and Franaszek 8B/10B Code Two-stage coding: 5B/6B and 3B/4B 5B/6B has s5 bits input plus running gdisparity 3B/4B has 3 bits input plus running disparity Running disparity is Negative Positive Same if output bits contain more zeroes than ones if output bits are 111000 or 1100 if output bits contain more ones than zeroes if output bits are 000111 or 0011 if output bits have equal number of ones and zeroes 74
Data Communication Link Layer: Encoding Scheme e Code guarantees to generate always opposite disparity or neutral Aim of Code DC free output Clock containment of output Output notation in small letters EDCBA HGF encoded to abcdei encoded ddto fghj fhj Final coded word is abcdeifghj a is transmitted first 75
Data Communication Link Layer: Code Table 5B/6B rd indicates whether incoming disparity is changed (-rd) or not (rd) 76
Data Communication Link Layer: Code Table 3B/4B rd indicates whether incoming disparity is changed (-rd) or not (rd) Special case for input Dxx.7: Coding depends on previous 2 bits 77
Data Communication Link Layer: Code Table Control o Codes Existence of 2 Control characters K28.3 and K28.5 Any control characters inverts the running disparity rd is always -rd 78
Data Communication Link Layer: Encoding Encoding of Data Byte: 0x9A, last rd should be negative (rd-) Binary representation 0x9A Character notation o D. Binary 5B/6B output Binary 3B/4B output Resulting 8B/10B output, rd, rd, rd 79
Data Communication Link Layer: Encoding/LUT Encoding Examples Incoming rd-, 0x4A D10.2 Incoming rd+, 0xEB D11.7 Incoming rd-, 0x00 D0.0 Incoming rd+, 0xF8 D24.7 010101 0101 rd- (neutral encoding) 110100 1000 rd- (P7 replacement) 100111 0100 rd- 001100 1110 rd+ Three previous tables may be combined to one lookup table 256 plus 2 entries 80
Data Communication Primitive Format All Primitives begin with a Control character K28.3 or K28.5 Followed by 3 non-control characters to complete DWord 8B/10B Encoding applies ALIGNP (D27.3 D10.2 D10.2 K28.5) is special primitive Command: Phy layer re-adjusts internal operations Only primitive that uses the K28.5 Control character Has neutral disparity, can be injected without changing rd May be consumed by Phy layer or dropped by Link layer 85
Data Communication Primitives: Frame Example pe Frame transmission Host Device Description fromhosttodevice to X_RDY R_RDYRDY Device decodes X_RDY and answers R_RDYRDY X_RDY R_RDY SOF R_RDY Host has decoded R_RDY and starts frame Data R_RDY Data R_IP Device has decoded SOF and sends R_IP Data EOF WTRM R_IP R_IP R_IP WTRM R_IP Device has received EOF and computes CRC WTRM R_OK CRC OK device sends R_OK WTRM R_OK SYNC R_OK Host has decoded R_OK and sends Idle SYNC R_OK 94
Data Communication Primitives: Flow Control o Example pe Frame transmission Host Device Description fromhosttodevice to SOF R_RDYRDY Host has decoded R_RDY RDY and starts frame Data R_RDY Data R_IP Device has decoded SOF and sends R_IP Data R_IP HOLD R_IP Host send buffer empty sending HOLD HOLD R_IP HOLD HOLDA Device has decoded HOLD and sends HOLDA Data HOLDA Host resumes data transfer Data EOF HOLDA R_IP WTRM R_IP Device has received EOF and computes CRC WTRM R_OK CRC OK device sends R_OK WTRM R_OK 95
Data Communication Primitives: Continue Example pe Frame transmission Host Device Description fromhosttodevice to X_RDY R_RDYRDY Device decodes X_RDY and answers R_RDYRDY X_RDY R_RDY SOF CONT Host has decoded R_RDY and starts frame Data any Data R_IP Device has decoded SOF and sends R_IP Data EOF WTRM R_IP CONT any WTRM any Device has received EOF and computes CRC CONT R_OK CRC OK device sends R_OK any R_OK SYNC CONT Host has decoded R_OK and sends Idle SYNC any 96
Data Communication Primitives: Connection ecto Init Initialization of Communication Not temp. correct Host Device Description COMRESET Idle Host issues COMRESET (informative) Idle COMINIT Device issues COMINIT (informative) COMWAKE Idle Host issues COMWAKE (informative) Idle COMWAKE Device issues COMWAKE (informative) D10.2 ALIGN Host tries to lock on devices ALIGN ALIGN ALIGN Host locked on ALIGN sends ALIGN now Temporally correct ALIGN SYNC Device locked on Host-ALIGN, sending SYNC ALIGN SYNC ALIGN SYNC Host detected 1st SYNC from Device ALIGN SYNC ALIGN SYNC Host detected 3rd SYNC from Device X_RDY SYNC Host wants to transmit data X_RDY SYNC 93
Data Communication Primitives: Collision so Frame transmission fromhosttodevice to SYNC SYNC Idle Host Device Description X_RDY SYNC Host signals transmission X_RDY X_RDY Device signals transmission X_RDY X_RDY Device detects hosts transmission R_RDY X_RDY Host detects device transmission R_RDY X_RDY R_RDY SOF Device detected R_RDY, sends data R_RDY R_IP R_IP R_IP R_IP R_OK Data Data EOF WTRM WTRM WTRM 97
Data Communication ATA Registers s and Signals Serial ATA is compatible with ATA Software ATA emulation needed Host thinks of writing to ATA registers e s No direct access possible in SATA SATA holds copy of devices register block Named Shadow Register Block Writing to this block triggers Register Transfer to Device Signal INTRQ is reflected by a bit in a register 113
Data Communication ATA Signals Sg as Pin Signal Name Description Pin Signal Name Description 1 /RESET Reset 21 DMARQ DMA Request 2 GND Ground 22 GND Ground 3 DD7 Data 7 23 /DIOW Write Strobe 4 DD8 Data 8 24 GND Ground 5 DD6 Data 6 25 /DIOR Read Strobe 6 DD9 Data 9 26 GND Ground 7 DD5 Data 5 27 IORDY I/O Ready (obsolete) 8 DD10 Data 10 SPSYNC:CSE Spindle Sync or Cable 28 9 DD4 Data 4 L Select 10 DD11 Data 11 29 /DMACK DMA Acknowledge 11 DD3 Dt Data 3 30 GND Ground 12 DD12 Data 12 31 INTRQ Interrupt Request 13 DD2 Data 2 32 /IOCS16 IO Chip Select 16 14 DD13 Data 13 33 DA1 Address 1 15 DD1 Data 1 34 PDIAG 80-pin cable detect. 16 DD14 Data 14 35 DA0 Address 0 17 DD0 Data 0 36 DA2 Address 2 18 DD15 Data 15 37 /IDE_CS0 Chip Select 19 GND Ground 38 /IDE_CS1 Chip Select 20 KEY Key (Pin missing) 39 /ACTIVE Led driver 40 GND Ground 114
Data Communication FIS: Register Host Device Transfers contents of Shadow Register Block to device FIS Type 0x27, Length of 5 DWords (20 Bytes) PM Port Device port address (e.g. Port Multiplier) C Command, set if command register addressed, not set if control r. 115
Data Communication FIS: Register Host Device Command, Features, LBA Low/Mid/High, Device, Control and Sector Count correspond to the appropriate registers in the Shadow Register Block LBA Low/Mid/High (exp), Features (exp) and Sector Count (exp) correspond to the appropriate expanded fields in the Shadow Register Block All reserved field should be cleared on write and ignored on read 116
Data Communication FIS: Register Device Host FIS Type of 0x34 Used by device to indicate command completion I is Interrupt Bit and reflects the interrupt line of the device Status and Error contain the appropriate values of the Shadow Register Block 117
Data Communication FIS: Data (Bidirectional) ecto a) Transportation of payload data Data read or written to number of sectors, no register transfers Generated e ed by Host or Device Generally one element of sequence of transactions leading to data transfer In DMA operation multiple Data FIS may follow With PIO mode number of bytes transferred shall be equal to bytes indicated in Transfer Count field Recipient is not expected to buffer data for CRC checking 126
Data Communication FIS: Overview e FIS H->D D->H Type Register X X 0x27 / 0x34 Set Device Bits X 0xA1 DMA Setup X X 0x41 DMA Activate X 0x39 PIO Setup X 0x5F Data X X 0x46 BIST Activate t X X 058 0x58 127
Data Communication Protocol: Device Power-On Hardware reset detected by Phy (Power-on or COMRESET) State: Device Hardware Reset (DHR) After COMRESET is negated ed hardware is initialized and power-ono self-test is executed POST successful: Device sends Register FIS with Sector Count = 1, LBA = 1, Device = 0, Error = 1, Status 0x00-0x70 POST failure: Device sends Register FIS with Sector Count = 1, LBA = 1, Device = 0, Error = any but 1, Status 0x00-0x70 Device transitions to Device Idle (DI) state 128
Data Communication Protocol: Device Software Reset State: Device Software Reset (DSR) Software reset by Register FIS (SRST-Bit set in control register) C-Bit must be set to zero to address control o register e Software reset by Register FIS (SRST-Bit cleared) Device initializes and executed diagnostics (same as DHR) Result is transferred to Host via Register FIS Transition to Device Idle (DI) 129
Data Communication Example: Software Reset Host Device Transmit C=0, SRST=1 Transmit C=0, SRST=0 Register FIS Register FIS Process command Process command Initialization and Self-Test Update Shadow Register Block Register FIS 130
Data Communication Protocol: Device Idle Device waits for FIS, state is Device Idle (DI) While idle device or Host send SYNC primitives FIS reception: Register FIS, C-Bit cleared, SRST set Register FIS, C-Bit cleared, SRST cleared Register FIS, C-Bit set DSR (Reset) DI (Idle) DI2 (CheckCmd) DMA Setup FIS DI (Idle) Unexpected FIS DI (Idle) 131
Data Communication Protocol: Device Idle Check Command Device received Register FIS State is Device Idle 2:Check_command (DI2:Check_command) Determine e e required ed command protocol oco Non-data command PIO data-in PIO data-out READ DMA WRITE DMA DEVICE RESET DND0: Non-data DPIOI0: PIO_in DPIOO0: PIO_out DDMAI0: DMA_in DDMAO0: DMA_out DDR0: Device_reset 132
Data Communication Protocol: PIO In 0. Successfully parsed PIO In command 1. Prepare a data block for transfer 2. Transmit PIO OSeup Setup FIS to Host 3. Transmit Data FIS If more data than 8192 Bytes (2048 DWords) requested proceed to 1. 4. Transition to Device Idle (DI) 133
Data Communication Example: pe PIO Read from Device Host Initialization of Shadow Control Registers Transfer Shadow Control Registers Register FIS Update Status Register Update Status Register with E_Status PIO Setup FIS Data FIS Device Process command Update Status Register Update Status Register with E_Status PIO Setup FIS Data FIS Real lfinal status t is not ttransferred 134
Data Communication ATAPI PIO In 1. Host sends PACKET command via Register FIS 2. After device is ready to receive ATAPI command packet PIO Setup FIS is transmitted to Host 3. Host writes command to Shadow Data Register and sends Data FIS containing the command to device 4. Device processes command packet and starts delivering data Data transfer announced with PIO Setup FIS to Host (Multiple) Data FIS follow 5. Device transmits Register FIS at end of ftransfer 149
Data Communication Example: pe ATAPI PIO Read from Device Host Device PACKET command Send command packet Receive data Update Shadow Registers Register FIS PIO Setup FIS Data FIS PIO Setup FIS Data FIS Register FIS Request command packet Process command Send data announcement Send data Send register update 150
DMA PIO Data Communication PIO vs. DMA Transfers s Data from/for Data FIS is handled by Host DMA controller Data is written to (serial) FIFO that is attached to Shadow Data Register Host reads Shadow Data Register to get/set data A FIFO overflow or underflow is prevented by SATA Flow Control Host register access time defined by PIO mode setting 151
Serial ATA Application Layer Host Adapter Register Interface Parallel ATA Emulation Native Command Queuing HDD Activity Indication 152
Application Layer Feature: e Native Command Queuing Allows commands to be accepted even if one or more previously accepted commands are not completed All commands send must carry a NCQ tag NCQ tag is identifier for command slot in queue Queue size is defined in IDENTIFY DEVICE Word 75 Status of queue is returned to Host in Set Device Bits FIS Set Device Bits FIS is send to Host after each successful command completion Unsuccessful command completion is indicated d by Register FIS or Set Device Bits FIS (both with ERR-Bit set) to Host 180
Application Layer Feature: e NCQ Commands NCQ consists of two commands to read and write data First-party DMA (FPDMA) READ FPDMA QUEUED U 0x60 / WRITE FPDMA QUEUED U 0x61 FUA: Prio: Forced Unit Access (Data must be on media) Command Priority: 0 = Normal, 1 = High Register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Features Sector Count Sector Count Prio Reserved NCQ Tag na LBA Low LBA LBA Mid LBA LBA High LBA Device FUA 1 R/0 0 Reserved Command 60h/61h 181
Application Layer Feature: e NCQ Command Sending NCQ Commands are transferred via Register FIS to device BSY Bit and DRQ Bit is not set Register e FIS is used to inform Host of command acceptance ce NCQ and normal commands are not allowed to mix If this is tried all unexecuted commands in queue are marked failed Host implements 32 Bit SActive Register and sets the appropriate Bit position to 1 if a NCQ command is send with this tag Host may issue as many commands as there are empty slots in SActive 182
Application Layer Feature: e NCQ Data Delivery e Device issues DMA Setup FIS when data is ready to be transferred Originating commands tag is used as buffer identifier Host controller o must find appropriate context for this identifier e 183
Application Layer Feature: e NCQ Data Delivery e Only one DMA Setup FIS will be send If transfer spans multiple Data FIS additional DMA Setup FIS not needed For Host to device transfers the DMA Activate FIS may be omitted if Auto-Activate feature is used in DMA Setup FIS Transferring of data depends on two feature settings Non-zero buffer offsets in DMA Setup FIS Guaranteed in-order data delivery If non-zero buffer offsets are not supported or not enabled a command is not allowed to be splitted Data transfer must be satisfied to completion after Setup FIS 184
Application Layer Feature: e NCQ Data Delivery e Non-zero buffer offsets enabled / in-order delivery enabled Data transfer may be interrupted after a specific DMA Setup FIS Interleaving of commands is not allowed Data transfer may be continued with additional DMA Setup FIS Non-zero buffer offsets enabled / in-order delivery disabled Data transfer may be interrupted after a specific DMA Setup FIS Interleaving of commands is allowed Data transfer may be continued with additional DMA Setup FIS 185
Application Layer Feature: e NCQ Success Notification o After last Data FIS of a command device sends Set Device Bits FIS Set Device Bits FIS includes SActive Register in Reserved field Bits set in the SActive fields indicate successful completion of command All bit position set shall be cleared in Hosts SActive Register as completed Host may send command with Tags having value of zero in SActive 186
Application Layer Feature: e NCQ Error Notification o Command raises error condition on reception/processing Device sends Register FIS with ERR-Bit set Command executed in queue raises error Device sends Set Device Bits FIS with ERR-Bit set Bit for failed command (and completed commands if any) also set Stops all command processing until Host action Further commands to the device are aborted with ERR-Bit set Host shall issue a READ LOG EXT command to determine exact error condition 187
Application Layer Example: pe NCQ FPDMA Read READ FPDMA QUEUED Host Register FIS Register FIS Device Non-zero buffer offsets In-order Queuing of command Additional commands with different tags DMA Setup FIS Prepare for reception Offset = 0 Data FIS Data FIS Data FIS Data ready, execution of command Update SActive Data FIS Set Device Bits FIS Command finished update SActive 191
Application Layer Example: pe NCQ FPDMA Read READ FPDMA QUEUED Host Register FIS Register FIS Device Non-zero buffer offsets In-order Queuing of command Prepare for reception Prepare for reception Update SActive Additional commands with different tags DMA Setup FIS Offset = 0 Data FIS Data FIS Additional commands to Device DMA Setup FIS Offset = 16384 Data FIS Data FIS Set Device Bits FIS Data ready, execution of command Data not ready Data ready, further execution of command Command finished update SActive 192
Application Layer Example: pe NCQ FPDMA Read Host Device Non-zero buffer offsets In-order 2 FPDMA READ Both > 8192 Bytes CMD 1 CMD 2 DMA Setup FIS Offset = 8192 Data FIS DMA Setup FIS Offset = 0 Data FIS DMA Setup FIS Offset = 0 Data FIS DMA Setup FIS Offset = 8192 Data FIS Queuing of commands Cmd 2 Bytes 8192 to X Cmd 1 Bytes 0 to 8191 Cmd 2 Bytes 0 to 8191 Cmd 1 Bytes 8192 to X 193
Application Layer HDD Activity ty Indication May be vendor-specific or Parallel ATA emulated by Host Emulation: If BSY or SActive set then Else LED = On LED = Off LED is valid for both Master-only and Master-Slave SATA Hosts If Master-Slave mode LED should be always on ATAPI devices shall not generate LED indication Multiple SATA channels LED indications should be connected by wired-or 201
Application Layer HDD Activity ty Indication Activity signal shall be Active low Open collector/drain SATA controllers may include activity aggregated indication pin and/or pin for each channel 202
Serial ATA SATA Link Expansion Port Multiplier Port Selector 203
Serial ATA SATA Integrated Circuits Port Multiplier PATA Bridge Host controller 232
SATA Integrated Circuits Port otmultiplier utpe SiI 3726 Silicon Image 3726 Port Multiplier 1:5 SATA II Port Multiplier Programmable Tx Voltage 8 kbyte FIFO buffer per device 32 GPIO Pins controlled by SATA (GSCR[130]-Register) Power Mode request support Integrated SATA to I2C Bridge Picture Source: SiI 3726 Prodct Brief, SiI 3726CB364, 2004 Silicon Image, Inc. 233
SATA Integrated Circuits SiI 3726 Block Diagram a Picture Source: SiI 3726 Prodct Brief, SiI 3726CB364, 2004 Silicon Image, Inc. 234
SATA Integrated Circuits PATA-SATA Bridge SiI 3811 Silicon Image 3811 Parallel ATA to SATA Bridge Supports SSC Receive Power Management e Ultra/ATA 133 Parallel Interface Serial ATA 1,5 Gbps Interface 48 Bit LBA addressing (16 Bit Registers) Application: Mainboard or Device Picture Source: SiI 3811 Prodct Brief, SiI PB-58 rev1 8/06, 2004 Silicon Image, Inc. 235
SATA Integrated Circuits SiI 3811 Block Diagram a Picture Source: SiI 3811 Prodct Brief, SiI PB-58 rev1 8/06, 2004 Silicon Image, Inc. 236
Serial ATA Thanks for your Attention 240